TW432647B - Semiconductor wafer package and the packaging method thereof - Google Patents
Semiconductor wafer package and the packaging method thereof Download PDFInfo
- Publication number
- TW432647B TW432647B TW088123432A TW88123432A TW432647B TW 432647 B TW432647 B TW 432647B TW 088123432 A TW088123432 A TW 088123432A TW 88123432 A TW88123432 A TW 88123432A TW 432647 B TW432647 B TW 432647B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- wafer
- conductive
- circuit
- scope
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW088123432A TW432647B (en) | 1999-12-31 | 1999-12-31 | Semiconductor wafer package and the packaging method thereof |
DE10018638A DE10018638A1 (de) | 1999-12-31 | 2000-04-14 | Kompakthalbleiterbauelement und Verfahren zu seiner Herstellung |
JP2000117937A JP2001194424A (ja) | 1999-12-31 | 2000-04-19 | パッケージ型半導体集積回路とその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW088123432A TW432647B (en) | 1999-12-31 | 1999-12-31 | Semiconductor wafer package and the packaging method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
TW432647B true TW432647B (en) | 2001-05-01 |
Family
ID=21643670
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW088123432A TW432647B (en) | 1999-12-31 | 1999-12-31 | Semiconductor wafer package and the packaging method thereof |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP2001194424A (de) |
DE (1) | DE10018638A1 (de) |
TW (1) | TW432647B (de) |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3263859B2 (ja) * | 1992-04-21 | 2002-03-11 | ソニー株式会社 | 半導体装置 |
JP3138343B2 (ja) * | 1992-09-30 | 2001-02-26 | 日本電信電話株式会社 | 光モジュールの製造方法 |
US5436503A (en) * | 1992-11-18 | 1995-07-25 | Matsushita Electronics Corporation | Semiconductor device and method of manufacturing the same |
JPH07231020A (ja) * | 1994-02-16 | 1995-08-29 | Toshiba Corp | エリアパッド付き半導体チップの製造方法 |
US5400950A (en) * | 1994-02-22 | 1995-03-28 | Delco Electronics Corporation | Method for controlling solder bump height for flip chip integrated circuit devices |
DE19507547C2 (de) * | 1995-03-03 | 1997-12-11 | Siemens Ag | Verfahren zur Montage von Chips |
US5598036A (en) * | 1995-06-15 | 1997-01-28 | Industrial Technology Research Institute | Ball grid array having reduced mechanical stress |
KR100222299B1 (ko) * | 1996-12-16 | 1999-10-01 | 윤종용 | 웨이퍼 레벨 칩 스케일 패키지 및 그의 제조 방법 |
US5953814A (en) * | 1998-02-27 | 1999-09-21 | Delco Electronics Corp. | Process for producing flip chip circuit board assembly exhibiting enhanced reliability |
JPH11345905A (ja) * | 1998-06-02 | 1999-12-14 | Mitsubishi Electric Corp | 半導体装置 |
DE19832970A1 (de) * | 1998-07-22 | 1999-11-04 | Siemens Ag | Integrierte elektronische Schaltung und Verfahren zum Versehen einer integrierten elektronischen Schaltung mit Anschlüssen |
-
1999
- 1999-12-31 TW TW088123432A patent/TW432647B/zh not_active IP Right Cessation
-
2000
- 2000-04-14 DE DE10018638A patent/DE10018638A1/de not_active Withdrawn
- 2000-04-19 JP JP2000117937A patent/JP2001194424A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
DE10018638A1 (de) | 2001-07-19 |
JP2001194424A (ja) | 2001-07-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI255022B (en) | Circuit carrier and manufacturing process thereof | |
CN102098876B (zh) | 用于电路基板的制造工艺 | |
US7234218B2 (en) | Method for separating electronic component from organic board | |
JP2500462B2 (ja) | 検査用コネクタおよびその製造方法 | |
JP2014090183A (ja) | 接合層を用いて基板に接続された金属ポストを有する超小型電子基板 | |
CN100573840C (zh) | 安装体及其制造方法 | |
KR20080037740A (ko) | 상호 접속 구조체를 포함하는 마이크로피처 조립체 및 그상호 접속 구조체를 형성하는 방법 | |
JPH07183333A (ja) | 電子パッケージおよびその作製方法 | |
TW200525666A (en) | Bump-on-lead flip chip interconnection | |
KR20010092350A (ko) | 전자 회로 장치 | |
JP2002005960A (ja) | プローブカードおよびその製造方法 | |
US6032852A (en) | Reworkable microelectronic multi-chip module | |
JP4085768B2 (ja) | 上部電極、パワーモジュール、および上部電極のはんだ付け方法 | |
WO2012171320A1 (zh) | 一种新的接触式智能卡的封装方法 | |
JP2715793B2 (ja) | 半導体装置及びその製造方法 | |
JP2013012674A (ja) | 半導体チップの製造方法、回路実装体及びその製造方法 | |
TW432647B (en) | Semiconductor wafer package and the packaging method thereof | |
JP2005123463A (ja) | 半導体装置及びその製造方法、半導体装置モジュール、回路基板並びに電子機器 | |
US20080212301A1 (en) | Electronic part mounting board and method of mounting the same | |
JP2004087670A (ja) | 絶縁性封止樹脂のフィレット及び電子部品の装着方法 | |
JP2002520879A (ja) | 電気的なテストを伴ったチップキャリア配置体及びチップキャリア配置体を製造する方法 | |
TWI776678B (zh) | 半導體封裝件及其製造方法 | |
JP6776490B2 (ja) | 半導体検査装置及びその製造方法 | |
TWI264054B (en) | Method and structure of flip chip bonding | |
JP4124518B2 (ja) | 電子ユニット |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MM4A | Annulment or lapse of patent due to non-payment of fees |