TW432647B - Semiconductor wafer package and the packaging method thereof - Google Patents

Semiconductor wafer package and the packaging method thereof Download PDF

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Publication number
TW432647B
TW432647B TW088123432A TW88123432A TW432647B TW 432647 B TW432647 B TW 432647B TW 088123432 A TW088123432 A TW 088123432A TW 88123432 A TW88123432 A TW 88123432A TW 432647 B TW432647 B TW 432647B
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Taiwan
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substrate
wafer
conductive
circuit
scope
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TW088123432A
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Chinese (zh)
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I-Ming Chen
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Chen I Ming
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Priority to TW088123432A priority Critical patent/TW432647B/en
Priority to DE10018638A priority patent/DE10018638A1/en
Priority to JP2000117937A priority patent/JP2001194424A/en
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Publication of TW432647B publication Critical patent/TW432647B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Abstract

A semiconductor wafer package comprises: an unsliced wafer comprising a plurality of chip areas, each chip area having an insulated pad mounting surface mounted with a pad; a substrate covering at least one chip area of the wafer, and comprising a circuit track layout surface opposite to the mounting surface of at least one chip area and corresponding to the pad of the at least one chip area to form a plurality of welding points electrically connected to the corresponding circuit tracks on the layout surface; a plurality of conductors for electrically connecting the welding points of the substrate to the corresponding pad of the at least one chip area; a plurality of bumps for maintaining a predetermined distance of the substrate with at least one chip region; and, a plurality of conductive contacts located on the substrate surface corresponding to the circuit track layout surface, and electrically connected to the corresponding circuit tracks on the circuit track layout surface of the substrate.

Description

P432647 五、發明說明（1) 本發明係有關於一種半導體晶圓封裝體及其之封裝方 法。 以在’一半導體積體電路元件（semic〇nduct〇i· 1C device)的製成皆是先將一片完整的晶圓（wafer)切割成 數顆裸晶（bare chip)，再將該等裸晶個別封裝及測試俾 成為一半導體積體電路元件。 然而，對裸晶個別進行封裝及測試作業將會使得生產 時間拉長而影響產量，進而使得生產成本增加而降低.競爭 、有，於此，本案發明人遂以其從事該行業之多年經驗 ，’並本著精益求精之精神，積極研究改良，遂有本發明『 半導體晶圓封裝體及其之封裝方法』產生。 本發明之目的是為提供一種半導體晶圓封裝體及豆 封裝與測試方法。 〃 根據本發明之一特徵，一種 未經切割 區域具 區域上 之至少 曰a 片區 至少一 設表面 電路執 焊點與 半導體晶圓 有數個晶片 焊墊安裝表 係與其之内部電路電氣連接； 片區域的基板，該基板具有一 裝表面相對的電路 區域之焊墊形成有 等焊點係與該電路 連接；數個導電體 的晶圓該晶圓具 有一安裝有焊墊之絕緣的 —個晶 域之安： 個晶片 上，該 跡電氣 該至少 執跡佈設表 數個焊點於 軌跡佈設表 ’該等導電 一個晶片區域之對應的焊塾電 區域> 面’於一覆蓋 與該至 面並對 該電路 面上之 體將該 氣連接 ，包含 各晶片 各晶片 該晶圓 少一個 應於該 轨跡佈 對應的 基板的 :數個P432647 V. Description of the Invention (1) The present invention relates to a semiconductor wafer package and a packaging method thereof. In the fabrication of semiconductor integrated circuit components (semiconductor 1C device), a complete wafer is first cut into several bare chips, and then the bare chips are cut. Individual packages and tests become a semiconductor integrated circuit element. However, individually packaging and testing the bare die will increase the production time and affect the output, which will increase the production cost and reduce it. Competition, yes, and hereby, the inventor of this case has used his many years of experience in the industry, 'And in the spirit of excellence, actively research and improve, the invention "semiconductor wafer package and its packaging method" was produced. An object of the present invention is to provide a semiconductor wafer package and a method for packaging and testing a bean. 〃 According to a feature of the present invention, an uncut area has at least one a area on the uncut area. At least one surface circuit soldering point is provided with the semiconductor wafer. Several wafer pad mounting tables are electrically connected to its internal circuits. The substrate has a solder pad with a circuit area opposite to the mounting surface formed with equal solder joints connected to the circuit; a wafer of several conductors; the wafer has an insulating-crystal domain with solder pads mounted thereon. Security: On a wafer, the trace electrical should arrange at least a few solder joints on the trace layout table 'the corresponding soldering area of the conductive one wafer region > surface' This gas is connected to the body on the circuit surface, including each wafer, each wafer, and at least one wafer corresponding to the substrate corresponding to the track cloth: several

f ,432647 五、發明說明（2) 凸塊，該等凸塊係形成於該基板 至少一個晶片區城的安裝表面中 個晶片區域保持一預 係置於 係與該 與該至少 點，該等 相對的表 對應的電 根據 :二未經 區域具有 區域上的 該晶圓之 個晶片區 一個晶片 片區域的 佈設表面 ，該等焊 電氣連接 一個晶片 該等導電 的表面上 的電路執 根據 裝方法， ’該晶圓 導電觸點 面上並且 路轨跡電氣連接。 本發明的另一特徵 該基板 基板之 的電路軌跡佈設表面與該 之—者上，用以將該基板 定距離；及數個導電觸 之與該電路軌跡佈設表面 该電路軌跡佈設表面上之 切割的晶圓，該晶圓具 一安裝有焊墊之絕緣的 焊墊係與其之内部電路 一個晶片區域的黏膠層 表面並且係形 墊的開 域的安裝 區域之焊 基板5該 並對應於 點係與該 ;數個導 區域之對 觸點係置 並且係與 跡電氣連 本發明的 包含如下 包含數個 孔；一 基板具有一黏 該一個 電路軌 電體， 應的焊 於該基 該基板 接。 晶片區 跡佈設 該等導 墊電氣 板之與 之該電 種半導 有數個 焊墊安 電氣連 ，該黏 成有至 覆蓋該 接至該 域的焊 表面上 電體將 連接； 該電路 路軌跡 體晶圓封 晶片區域 裝表面， 接；至少 裝體包含 ,各晶片 於各晶片 一個覆蓋 膠層係黏接至該一 少一個用於暴露該 晶圓之至 黏膠層的 墊形成有 之對應的 該基板的 及數個導 軌跡佈設 佈設表面 少一個 電路執跡 數個烊點 電路執跡 焊點與該 電觸點， 表面相對 上之對應 a曰 再一特徵，一種半導體晶圓封裝體的封 之步驟：提供一未經切割的半導體晶圓 晶片區域’各晶片區域具有·一用以安裝f, 432647 V. Description of the invention (2) The bumps are formed on the mounting surface of at least one wafer area of the substrate. Each wafer area is maintained in a pre-positioned position with the at least point and the like. Corresponding electrical basis of the relative table: the layout surface of one wafer area of one wafer area of the wafer on the non-area area, and the electrical connection of the circuit on the conductive surface of one wafer to the wafer according to the mounting method , 'The wafer is electrically connected on the conductive contact surface and the track. Another feature of the present invention is that the circuit track layout surface of the substrate substrate and the one are used to set a distance between the substrate; and a plurality of conductive contacts and the circuit track layout surface are cut on the circuit track layout surface. The wafer has a pad with an insulating pad mounted thereon and a surface of the adhesive layer of a wafer region of its internal circuit and a solder substrate 5 of the mounting region of the open region of the pad. The present invention includes a plurality of holes as follows; a substrate has an electrical body that is bonded to the circuit rail, and should be soldered to the substrate. Pick up. The wafer area traces the conductive pad electrical boards, and the electrical type semiconductor has several solder pads electrically connected to each other, and the adhesive body is connected to the soldering surface covering the soldering area connected to the domain; the circuit track The surface of the wafer is sealed on the surface of the wafer, and the surface is connected; at least the package includes: each wafer is adhered to each of the wafers with a covering layer that is bonded to the at least one pad for exposing the wafer to the adhesive layer; The substrate and the plurality of conductive traces are arranged on the surface. One circuit is traced, the number of circuit traces, the number of circuit traces, and the electrical contact are relatively corresponding on the surface. Another feature is a semiconductor wafer package. Sealing step: Provide an uncut semiconductor wafer wafer area. Each wafer area has a

第5頁 Ιϋίΐ32^6 4 五、發明說明（3) 焊塾之絕緣的焊墊安裝表 其之内部電路電氣連接； 的鋼板置於該晶圓之上， 專日曰片區域之彈塾的開孔 貫孔’在形成各開孔的孔 電體形成空間，而在形成 的安裝表面之間係形成一 材料利用印刷手段於各導 於各凸塊形成空間内形成 後’對該等導電體和凸塊 硬性的導電體和凸塊；提 區域的基板，該基板具有 面並且係對應於該至少一 佈設表面上形成有數個焊 路轨跡佈設表面上之對應 覆蓋該基板的鋼板置於該 用於暴露該基板之該等焊 該基板之對應的焊點之間 電金屬膠為材料利用印刷 一導電體；在該基板上之 把該晶圓與該基板分隔一 域之焊墊的導電體與該基 —起；及於該基板之與該 面上設置有數個導電觸點 面，於各晶片區域上的焊塾係與 把一用以覆蓋該晶圓之晶片區& 遠鋼板係形成有數個用於暴露該 且係於該等開孔兩側形成有數個 壁與對應的焊墊之間係形成一導 各貫孔的孔壁與對應之晶片區域 凸塊形成空間；以導電金屬膠為 電體形成空間内形成一導電體及 凸塊，在移去§玄晶圓上的鋼板之 進行加熱烤乾處理以使之成為帶 供一覆蓋該晶圓之至少一個晶片 一佈設有電路執跡的電路佈設表 個晶片區域的焊塾於該電路軌跡 點’該基板的該等焊點係與該電 的電路軌跡電氣連接；把一用以 基板之上，該鋼板係形成有數個 的開孔’在形成各開孔的孔壁與 係形成一導電體形成空間；以導 手段於各導電體形成空間内形成 鋼板被移除之後’藉著該等凸塊 預定距離，把該至少一個晶片區 板之對應之焊點的導電體熔接在 電路軌跡佈設表面相對的另一表 ，該等導電觸點係與該基板之對Page 5 Ιϋίΐ32 ^ 6 4 V. Description of the invention (3) Insulation pad installation table for welding pads The internal circuit is electrically connected; the steel plate is placed on the wafer, and the opening of the bomb in the Japanese-Japanese film area is opened. The through-holes' form a space between the hole-forming electrical bodies forming the openings, and a material is formed between the mounting surfaces formed, and after printing is formed in each of the bump forming spaces, the conductive bodies and The bumps are rigid conductors and bumps; the substrate of the lifting region, the substrate has a surface and corresponds to the at least one layout surface where a plurality of welding track traces are formed on the layout surface, and a steel plate corresponding to the substrate is placed in the for A conductive body is printed by using an electric metal glue as a material between the corresponding solder joints of the substrate that are exposed on the substrate; the conductive body of the pad on the substrate that separates the wafer from the substrate with a domain and the And a plurality of conductive contact surfaces are provided on the substrate and the surface, and a plurality of welding pads on each wafer region and a wafer region & far steel plate system for covering the wafer are formed. For exposing this and It is formed between a plurality of walls formed on both sides of the openings and corresponding pads, and a hole wall forming a through hole and a corresponding wafer area bump forming space are formed; the conductive metal glue is used to form the electrical body forming space. An electric conductor and a bump are heated and dried after removing the steel plate on the xuan wafer to make it into at least one wafer covering the wafer, and a circuit layout sheet with circuit traces is arranged. The solder joints in the area are connected to the circuit track points. The solder joints of the substrate are electrically connected to the electrical circuit track; a plate is used on the substrate, and the steel plate is formed with a plurality of openings. The hole wall and the system form a conductive body forming space; after the steel plates are removed in the conductive body forming spaces by means of guides, the corresponding solder joints of the at least one wafer area board are removed by the predetermined distance of the bumps. The conductive body is welded to another table opposite to the surface on which the circuit traces are arranged. The conductive contacts are opposite to the substrate.

第6頁 432647 五、發明說明（4)Page 6 432647 V. Description of the invention (4)

應的電路軌跡電氣連接。 根據本發明之又另一特微，一種半導體晶圓封裝體的 封裝方法，包含如下之步驟：提供一未經切割的半導體晶 圓，該晶圓包含數個晶片區威，各晶片區域具有—用以安 裝焊墊之絕緣的焊墊安裝表面，於各晶片區域上的烊墊係 與其之内部電路電氣連接；把/用以覆蓋該晶圓之晶片區 域的鋼板置於該晶圓之上，該鋼板係形成有數個用於暴露 該等晶片區域之焊墊的開孔，在形成各開孔的孔壁與對應 的焊墊之間係形成一導電體形成空間；以導電金屬膠為材 料利用印刷手段於各導電體形成空間内形成一導電體；在 移去該晶圓上的鋼板之後，對該等導電體進行加熱烤乾處 理以使之成為帶硬性的導電雜’提供至少一個覆蓋該晶圓 之一個晶片區域的黏膠層，該至少—個點勝層黏接至該晶 圓之該一個晶片區域的安裝表面上’並且係形成有至少一 個用於暴露該一個晶片區域之焊墊之導電體的開孔；提供 一覆蓋該晶圓之至少一個晶片區域的基板’該基板具有一 佈設有電路轨跡的電路佈設表面並且係對應於該至少一個 晶片區域的焊墊於該電路軌 點，該基板的該等焊點係與 的電路軌跡電氣連接；把— 基板之上’該鋼板係形成有 的開孔，在形成開孔的孔髮 形成一導電體容置空間；以 段於各導電體形成空間内形 跡佈設表面上形成有數個焊 5亥電路執跡佈設表面上之對應 用以覆蓋該基板的鋼板置於該 數個用於暴露該基板之該等焊 與該基板之對應的焊點之間係 導電金屬膠為材料利用印刷手 成—導電體；在該基板上之鋼The circuit trace should be electrically connected. According to yet another feature of the present invention, a method for packaging a semiconductor wafer package includes the steps of: providing an uncut semiconductor wafer, the wafer including a plurality of wafer regions, each wafer region having- The insulating pad mounting surface for mounting the pads, the pads on each wafer area are electrically connected to their internal circuits; the steel plate / to cover the wafer area of the wafer is placed on the wafer, The steel plate is formed with a plurality of openings for solder pads for exposing these wafer areas. A conductive body forming space is formed between the hole wall forming each opening and the corresponding solder pad; a conductive metal paste is used as a material. A printing method forms a conductive body in each conductive body forming space; after removing the steel plate on the wafer, the conductive bodies are heated and dried to make them hard conductive conductive impurities. An adhesive layer of a wafer region of the wafer, the at least one dot layer is adhered to the mounting surface of the wafer region of the wafer 'and at least one is formed for exposing the Openings of the conductors of the pads of each wafer region; a substrate is provided that covers at least one wafer region of the wafer; the substrate has a circuit layout surface on which circuit traces are arranged and corresponds to the at least one wafer region; The solder pads are on the circuit track points, and the solder points of the substrate are electrically connected to the circuit tracks; the "holes" formed on the steel plate above the substrate are formed, and a conductive body is formed in the holes forming the holes. A plurality of welding plates are formed on the surface of the trace layout in each conductor forming space, and corresponding steel plates for covering the substrate are placed on the plurality of substrates for exposing the substrate. Between the welding and the corresponding solder joints of the substrate, conductive metal glue is used as a material to form a conductive body using printing hands; the steel on the substrate

•432647• 432647

板被移除之後’將該黏膠層與 黏接並把該一個晶片區域之焊 之焊點的導電體熔接在—起； 佈設表面相對的另一表面上設 電觸點係與該基板之對應的電 根據本發明之又再—特徵 封裝方法，包含如下之步驟： 圓’該晶圓包含數個晶片區域 裝焊塾之絕緣的焊塾安裝表面 與其之内部電路電氣連接；利 間内植入一導電體；提供至少 區域的黏膠層，該至少一個黏 晶片區域的安裝表面上，並且 該一個晶片區域之焊塾之導電 圓之至少一個晶片區域的基板 執跡的電路佈設表面並且係對 焊墊於該電路軌跡佈設表面上 該等焊點係與該電路執跡佈設 氣連接，把一用以覆蓋該基板 鋼板係形成有數個用於暴露該 成開孔的孔壁與該基板之對應 容置空間；以導電金屬膠為材 形成空間内形成一導電體；在 ，將該黏膠層與該基板的電路 該基板的電路軌跡佈設表面 墊的導電體與該基板之對應 及於該基板之與該電路執； 置有數個導電觸點，該等導 路轨跡電氣連接。 ，一種半導體晶圓封裝體的 提供一未經切割的半導體晶 ’各晶片區域具有—用以安 ’於各晶片區域上的焊墊係 用打線機於各導電體形成空 個覆蓋s玄晶圓之—個晶片 膠層黏接至該晶圓之該一個 係形成有至少一個用於暴露 體的開孔；提供—覆蓋該晶 ，該基板具有一佈設有電路 應於该至少一個晶片區域的 形成有數個焊點，該基板的 表面上之對應的電路執跡電 的鋼板置於該基板之上，該 基板之該等焊的開孔，在形 的焊點之間係形成一導電體 料利用印刷手段於各導電體 該基板上之鋼板被移除之後 軌跡佈設表面黏接並把該一After the board is removed, 'the adhesive layer is welded together with the conductive body of the solder joint of the one wafer area; an electrical contact is provided on the other surface opposite to the layout surface to the substrate The corresponding electricity according to yet another feature packaging method of the present invention includes the following steps: The wafer contains a plurality of wafer regions, and the solder pads are electrically connected to the internal solder pad mounting surface and the internal circuit; A conductive body; providing an adhesive layer of at least a region on the mounting surface of the at least one wafer region, and a circuit layout surface of a substrate track of at least one wafer region of a conductive circle of a solder pad of the one wafer region and The solder joints on the circuit track layout surface are gas-connected to the circuit track layout. A steel plate system for covering the substrate is formed with a plurality of hole walls for exposing the openings and the substrate. Corresponding to the accommodation space; a conductive body is formed in the space formed by using conductive metal glue; and, the adhesive layer and the circuit of the substrate are arranged on the circuit track of the substrate to guide the surface pad. The electrical body corresponds to the substrate and the substrate is connected to the circuit; there are several conductive contacts, and the conductive paths are electrically connected. A semiconductor wafer package is provided with an uncut semiconductor crystal. Each wafer region has-for mounting pads on each wafer region. A wire bonding machine is used to form an empty cover on each conductor. -One of the wafer adhesive layers adhered to the wafer is formed with at least one opening for an exposed body; provided-covering the crystal, the substrate has a formation of a circuit arranged on the at least one wafer area There are several solder joints. Corresponding steel plates on the surface of the substrate are placed on the substrate. The openings of the solder on the substrate form a conductive material between the solder joints. After the printing method removes the steel plate on the substrate of each conductor, the track layout surface is adhered and the

蘑4 32 6 4 五、發明說明（6) _ 域之焊塾的導電體與該基板之對應之焊點 2另-表面上設置有數個導電觸 ：：對 基板之對應的電路軌跡電氣連接。荨導電觸點係與該 有關本發明為達上述目的、 其功；二列舉較佳實施例並配合圖式：明：㊁術手段及 *法的第體晶圓封裝體之封裝 第八圖係本發明之丰壤坪g · 之其中-例子的示意圓封裝體之導電體之形狀 法之發r半導體晶圓封裝體之封裝方 第权佳貫施例的不意剖視圖；及 衣万 +, JU.. 至十五圖係描繪本發明之丰導體s III 4+ # 封裝方法之第 （牛V體S曰圓封裝體之 ~ #义佳只她例之一部份流程的示意剖又 1半4 # a 元件標號對照表 圖。 干導體晶圓 1 0 0 焊塾 2 鋼板 30導電體 31凸塊 二路執鄉佈設表面 52電鍍貫孔 54導電觸點 6 0 開孔Mushroom 4 32 6 4 V. Description of the invention (6) _ The conductive body of the welding pad of the domain and the corresponding solder joints of the substrate 2 In addition, there are several conductive contacts on the surface :: The electrical connections are made to the corresponding circuit traces of the substrate. The conductive contact is related to the present invention in order to achieve the above-mentioned object and its functions; the second is a list of preferred embodiments and cooperates with the drawings: Ming: the eighth drawing of the first wafer package packaging method and method In the present invention, the abundance of gongpingping g · which-an example of a schematic diagram of the shape of a conductive body of a circular package, a semiconductor wafer package packaging method, the unintentional cross-sectional view of the first preferred embodiment; and Yiwan +, JU .. to fifteen diagrams depicting the abundance conductor s III 4+ of the present invention # of the packaging method (ox V body S said round package ~ ~ Yi Jia only one example of a part of the process flow diagram and a half 4 # a Component reference chart. Dry-conductor wafer 1 0 0 Solder pad 2 Steel plate 30 Conductor 31 Bump two-way ruling surface 52 Plating through hole 54 Conductive contact 6 0 Opening

第9頁 「,432647 :、發明說明⑺ ~ 7 膠質材料 8 治具 1〇2黏膠層 1〇2() 開孔 300延伸部 301擴大部 在本發明被詳細描述之前，應要注意的是在整個說明 書當中’相同的元件係由相同的標號標示。 請參閱第一圖所示，一半導體晶圓1係被顯示包含數 個晶片區域1 0。該等晶片區域1 〇在該晶圓1被切割後便個 別成為所謂的裸晶。如第二圖所顯示般，各晶片區域1 Q具 有一用以安裝悍墊100之絕緣的焊墊安裝表面1〇1 。於各 晶片區域丨0上的焊墊1 〇 〇係與其之内部電路電氣連接。 接著’一用以覆蓋該晶圓之晶片區域1 0的鋼板2係置 於該晶圓1之上。在本實施例中’該鋼板2是為印刷網板 。該鋼板2係形成有數個用於暴露該等晶片區域丨〇之焊墊 1 〇 0的開孔2 0且係於各晶片區域1 〇之開孔2 〇的兩側更形成 有數個貫孔2 1。在形成各開孔2 0的孔壁與對應的焊塾1 〇 〇 之間係形成一導電體形成空間，而在形成各貫孔2 1的孔壁 與對應之晶片區域10的安裝表面1 〇 1之間係形成一凸塊形 成空間。 然後，以導電金屬膠為材料利用印刷手段於各導電體 形成空間内形成一導電體3 0及於各凸塊形成空間内形成有 金屬凸塊31。在本實施例中’該導電金屬膠是為摻雜有銀 的導電銀膠。應要注忍的是，該導電金屬勝亦可以是為摻 雜有金、銅、鐵等導電金屬材料的導電金屬膠。在移去該 鋼板2之後’該荨導電體3 0與該等金屬凸塊31係一起經過Page 9 ", 432647: Description of the invention ⑺ ~ 7 Gel material 8 Fixture 10 2 Adhesive layer 10 2 () Opening 300 Extension 301 Enlarged section Before the present invention is described in detail, it should be noted that Throughout the description, 'the same components are identified by the same reference numerals. Please refer to the first figure, a semiconductor wafer 1 is shown to include several wafer areas 10. These wafer areas 1 〇 in the wafer 1 After being cut, they are individually called so-called bare crystals. As shown in the second figure, each wafer region 1 Q has an insulating pad mounting surface 101 for mounting the pad 100. On each wafer region 丨 0 The solder pad 100 is electrically connected to its internal circuit. Then a steel plate 2 for covering the wafer area 10 of the wafer is placed on the wafer 1. In this embodiment, the steel plate 2 It is a printed stencil. The steel plate 2 is formed with several openings 20 for the pads 100 for exposing the wafer areas, and is attached to both sides of the openings 2 for each of the wafer areas. A plurality of through-holes 21 are formed. The wall of each hole where each opening 20 is formed and the corresponding welding pad 1 00 A conductive body forming space is formed, and a bump forming space is formed between the hole wall forming each through hole 21 and the mounting surface 100 of the corresponding wafer region 10. Then, a conductive metal paste is used as a material. The printing means forms a conductive body 30 in each conductive body forming space and a metal bump 31 is formed in each of the bump forming spaces. In this embodiment, 'the conductive metal paste is a conductive silver paste doped with silver. It should be noted that the conductive metal may also be a conductive metal paste doped with conductive metal materials such as gold, copper, iron, etc. After removing the steel plate 2, the net conductor 30 and the metals The bumps 31 pass by together

第10頁 r 14 3264 7_ 五、發明說明（8) 加熱烤乾處理成為帶硬性的導電體30和金屬凸塊31。 e青參閱第二圖所示’然後，一覆蓋該晶圓;[之至少一 個晶片區域1 0的基板5係被提供。在本實施例中，該基板 5覆蓋該晶圓1的所有晶片區域1 0。該基板5具有一佈設 有電路軌跡（圖中未示）的 5玄專晶片區域10的焊塾1〇〇 成有數個焊點5 1。該基板5 佈設表面5 0上之對應的電路 成有數個電鍍貫孔52。於形 鍵有一層與該基板5之電路 路軌跡電氣連接的電鍍層。 如第四圖所顯示般，接 板6係置於該基板5之上。 露該基板5之該等焊點5 1的 壁與該基板5之對應的焊點 。與鋼板2相同，在本實施 〇 ^ 然後，以導電金屬膠為 开^成空間内形成一導電體4 膠亦是為導電銀膠。 應要注意的是，該等金 圓1上，其亦可以被形成於 板5亦可以覆蓋該晶圓1的 域1 〇。 電路佈設表面5 0並且係對應於 於該電路執跡佈設表面5 〇上形 的該專焊點5 1係與該電路軌跡 轨跡電氣連接。該基板5更形 成各電鑛貫孔52之孔壁上係電 執跡佈設表面5 0上之對應之電 著’一用以覆蓋該基板5的鋼 該鋼板6係形成有數個用於暴 開孔6 0。在形成各開孔6 〇的孔 之間係形成一導電體形成空間 例中’該鋼板6是為印刷網板 材料利用印刷手段於各導電體 在本貫施例中，該導電金屬 屬&塊3 1不限定於形成在該晶 5亥基板5上。另一方面，該基 兩個或者為2之倍數的晶片區Page 10 r 14 3264 7_ V. Description of the invention (8) The heating and drying process becomes a rigid conductor 30 and a metal bump 31. e 青 Refer to the second figure 'Then, a substrate 5 covering at least one wafer region 10 is provided. In this embodiment, the substrate 5 covers all wafer regions 10 of the wafer 1. The substrate 5 has a plurality of solder joints 101 formed on a pad 5 of a wafer region 10 with circuit tracks (not shown) arranged thereon. The corresponding circuit on the surface 5 of the substrate 5 is formed with a plurality of plated through holes 52. The key has a plating layer electrically connected to the circuit track of the substrate 5. As shown in the fourth figure, the adapter plate 6 is placed on the substrate 5. The walls of the solder joints 51 of the substrate 5 and the corresponding solder joints of the substrate 5 are exposed. Similar to the steel plate 2, in this implementation, a conductive body 4 is formed in the space where the conductive metal glue is used to form the glue. The glue 4 is also a conductive silver glue. It should be noted that, on the gold circles 1, they can also be formed on the plate 5 and can also cover the domain 1 of the wafer 1. The circuit layout surface 50 and the special solder joint 51 corresponding to the shape of the circuit layout surface 50 are electrically connected to the circuit trace. The substrate 5 further forms the corresponding electrical writings on the surface of the electric track layout surface 50 of each of the electrical ore through holes 52-a steel for covering the substrate 5 and the steel plate 6 is formed with several for bursting Hole 6 0. In the example of forming a conductor forming space between the holes forming each of the openings 60, the steel plate 6 is a printing screen material using printing means for each conductor. In this embodiment, the conductive metal is & The block 31 is not limited to being formed on the crystal substrate 5. On the other hand, the base area is two or a multiple of two.

一_432647__ 五 '發明說明（5 ' ----- 今Ϊ參閱第五圖所示’在移去該基板5 i的鋼板6之後 ^寺阳片區域10之焊墊1〇〇的導電體3〇係與該基板5之 算I ^焊點51的導電體4溶接在—起。應要注意的是，該 f凸塊31將該晶圓！與該基板5分隔一預定距離，即，該 晶與該基板5之間的距離係由該等凸塊31的高度決定 命二後，如環氧樹脂般的膠質材料7係被灌注至該晶圓i :該基板5之間，俾可進一步避免該晶圓丨與該基板5脫 、及俾可將存在於該晶圓！與該基板5之間的空氣和水份 迫出，使兩者之間成真空狀態。 ^ 如第六圖所顯示般’數個導電觸點5 4然後係被形成於 邊基板5之與該電路軌跡佈設表面5 〇相對的另—表面5 3上 。在本實施例中，該等導電觸點54是為錫球。各導電觸點 54係與該基板5之對應之電鍍貫孔52的電鍍層電氣連接。 如疋’請參閱第七圖所示，透過該等導電觸點54，該 晶圓封裝體便可藉著一測試機台（圖中未示）的治具8進 行傳統的晶圓測試及燒機（burn —丨n)測試。在測試完成後 ’便可將該晶圓封裝體切割而成為個別的c s p ( c h丨p s丨z e Package)成品。因此，製程可以大大地縮短而增加產量， 進而降低生產成本而提升競爭力。 由於半導體製程越來越進步，當半導體製程為〇.1微 朱時’晶圓上之焊墊便會變得非常細小，約為25 X 25 β[ί[ °然而’與之配合之基板的焊點由於印刷製程的限制 係無法製作成如此之細小。因此’如第八圖所顯示般，各 導電體30係被形成具有一從對應之焊墊lQ〇延伸出來的延一 _432647__ Five 'invention description (5' ----- Now refer to the fifth figure 'after the steel plate 6 of the substrate 5 i is removed ^ the pad 100 of the Siyang sheet area 10 conductive body 30 is welded together with the conductor 4 of the solder joint 51 of the substrate 5. It should be noted that the f bump 31 separates the wafer from the substrate 5 by a predetermined distance, that is, The distance between the crystal and the substrate 5 is determined by the height of the bumps 31. After the second life, a glue-like material 7 such as epoxy resin is poured into the wafer i: between the substrates 5 It is further avoided that the wafer is disconnected from the substrate 5 and the air and moisture existing between the wafer 5 and the substrate 5 are forced out, so that the two are in a vacuum state. ^ As shown in the sixth figure As shown, a plurality of conductive contacts 54 are then formed on the other surface 53 of the side substrate 5 opposite to the circuit track layout surface 50. In this embodiment, the conductive contacts 54 are It is a solder ball. Each conductive contact 54 is electrically connected to the plating layer of the corresponding plated through hole 52 of the substrate 5. As shown in FIG. 54. The wafer package can be used for conventional wafer testing and burn-in (burn) testing by means of a jig 8 of a test machine (not shown). The wafer package is cut into individual csp (ch 丨 ps 丨 ze Package) finished products. Therefore, the manufacturing process can be greatly shortened to increase production, which in turn reduces production costs and enhances competitiveness. As semiconductor processes become more and more advanced, when When the semiconductor process is 0.1 microzhu, the solder pads on the wafer will become very small, about 25 X 25 β [ί [° [However] due to the limitation of the printing process, the solder joints of the substrate with which it is used cannot be It is made so small. Therefore, as shown in the eighth figure, each of the electrical conductors 30 is formed to have an extension extending from the corresponding pad lQ.

第12頁 ^432 f： Δ 7 五、發明說明（10) 伸部3 0 〇和形成於該延伸部3 0 〇之自由端的擴大部3 〇五 藉此，基板之焊點的導電體由於係與該導電體3 〇的擴大 30Ϊ電乳連接’故基板之焊點係被允許不必按對鹿於焊 的比例縮小，而解決了印刷製程無法克服的問題。 第九至十三圖顯示本發明之半導體晶圓封裝體及其 封裝方法的第二較佳實施例。 請參閱第九圖所示，一覆蓋該晶圓1之所有晶片區 1 〇的鋼板2’係置於該晶圓1之上。然而，在本實施例中 該鋼板2 ’僅對應於該等晶片區域丨〇的焊墊丨〇 〇形成有開 20。之後，與上述實施例相同，於各導電體容置空間内 形成有導電體30 ,且該等導電體3 0在該鋼板2,被移去之 係經過加熱烤乾處理成為帶硬性的導電體3〇。 請參閱第十圖所示，於該晶圓1之至少一個晶片區 的安裝表面101上係置放有一黏膠層1〇2 。在本實施 中，4晶圓1之所有晶片區域1 〇的安裝表面丨〇 ^皆置放 一黏膠層102 。各黏膠層102係形成有數個用於暴露對 之晶片區域10之焊墊100之導電體30的開孔1〇2〇。 請參閱第十一圖所示，然後，一覆蓋該晶圓丨之至 一個晶^區域10的基板5係被提供。在本實施例中，該 板5覆蓋該晶圓1的所有晶片區域1 0。該基板5具有一 設有電路軌跡（圖中未示）的電路佈設表面5〇並且係對 於該等晶片區域10的焊塾1〇〇於該電路軌跡佈設表面5〇 形成有數個焊點5 1。該基板5的該等焊點5丨係與該電路 跡佈設表面50上之對應的電路轨跡電氣連接。該基板5 部 墊 之 域 t 孔 係 後 域 例 有 應 少 基 佈、 應 上 軌 更 ·4 32 6 4 7 五、發明說明（π) 形成有數個電鍵貫孔52。於形成各電錄貫孔52之孔壁上係 電鍵有一層與該基板5之電路軌跡佈設表面5〇上之對應之 電路軌跡電氣連接的電鍍層。 接著’一用以覆蓋該基板5的鋼板6係置於該基板5 之上。該鋼板6係形成有數個用於暴露該基板之該等焊5 j 的開孔60。在形成開孔6 0的孔壁與該基板5之對應的焊點 之間係形成一導電體形成空間。 然後，與前述實施例相同，於各導電體形成空間内形 成一導電體4 。 請參閱第十二圖所示，在該基板5上之鋼板6被移除 之後’該基板5的電路軌跡佈設表面5〇係與該黏膠層1〇2〇 黏接’而且該等晶片區域10之焊墊丨〇〇的導電體3〇係與該 基板5之對應之焊點5 1的導電體4熔接在一起。其後，如 環氧樹脂般的膠質材料7係被灌注至該黏膠層1 〇 2 0的開孔 20内，俾可進一步避免該晶圓1與該基板5脫離及俾可將 存在於該開孔2 0内的空氣和水份迫出。 如第十三圖所顯示般’數個導電觸點54然後係被置放 於該基板5之與該電路執跡佈設表面5 〇相對的另一表面5 3 上。各導電觸點54係與該基板5之對應之電鍍貫孔52的電 鍍層電氣連接。 如是’與前述實施例相同，透過該等導電觸點5 4，該 晶圓封裝體便可藉著一測試機台的治具（圖中未示）進行 傳統的晶圓測試及燒機（bur n- i η )測試。在測試完成後， 便可將該晶圓封裝體切割而成為個別的csp (Ch i p S丨z ePage 12 ^ 432 f: Δ 7 V. Description of the invention (10) The extended portion 3 0 0 and the enlarged portion 3 5 formed at the free end of the extended portion 3 0 5 As a result, the conductive body of the solder joint of the substrate is It is connected to the expanded 30 'electric emulsion of the electric conductor 30, so the solder joints of the substrate are allowed to be reduced without having to reduce the ratio of soldering to soldering, and the problem that the printing process cannot overcome is solved. The ninth to thirteenth figures show a second preferred embodiment of a semiconductor wafer package and a packaging method thereof according to the present invention. Referring to FIG. 9, a steel plate 2 ′ covering all wafer regions 10 of the wafer 1 is placed on the wafer 1. However, in this embodiment, the steel plate 2 'is formed only with the pads 20 corresponding to the wafer regions 丨 0. Thereafter, as in the above-mentioned embodiment, a conductor 30 is formed in each conductor accommodating space, and the conductors 30 are removed from the steel plate 2 by heating and drying to become a rigid conductor. 3〇. Please refer to the tenth figure. An adhesive layer 102 is placed on the mounting surface 101 of at least one wafer region of the wafer 1. In this implementation, an adhesive layer 102 is placed on the mounting surfaces of all wafer regions 10 of the four wafers 1. Each of the adhesive layers 102 is formed with a plurality of openings 1020 for exposing the conductive body 30 of the bonding pad 100 of the opposite wafer region 10. Please refer to FIG. 11, and then, a substrate 5 covering the wafer to a crystal region 10 is provided. In this embodiment, the board 5 covers all wafer regions 10 of the wafer 1. The substrate 5 has a circuit layout surface 50 provided with a circuit track (not shown), and solder pads 100 for the wafer regions 10 are formed with a plurality of solder joints 51 on the circuit track layout surface 50. . The solder joints 5 of the substrate 5 are electrically connected to corresponding circuit tracks on the circuit track layout surface 50. Examples of the t-hole system and the back-domain of the five pads of the substrate include a base fabric and a rail. 4 32 6 4 7 V. Description of the invention (π) A plurality of through-holes 52 are formed. On the wall of each hole forming each of the through-holes 52, there is an electroplated layer electrically connected to a corresponding circuit track on the circuit track layout surface 50 of the substrate 5. Next, a steel plate 6 for covering the substrate 5 is placed on the substrate 5. The steel plate 6 is formed with a plurality of openings 60 for exposing the welds 5 j of the substrate. A conductor-forming space is formed between the hole wall forming the opening 60 and the corresponding solder joint of the substrate 5. Then, as in the previous embodiment, a conductive body 4 is formed in each conductive body forming space. Please refer to the twelfth figure, after the steel plate 6 on the substrate 5 is removed, 'the circuit trace layout surface 50 of the substrate 5 is bonded to the adhesive layer 1020' and the wafer areas The conductive body 30 of the pad 10 of 10 is welded together with the conductive body 4 of the corresponding pad 51 of the substrate 5. Thereafter, a gluing material 7 such as an epoxy resin is poured into the opening 20 of the adhesive layer 1020, so that the wafer 1 and the substrate 5 can be further prevented from detaching from each other and can exist in the Air and water in the opening 20 are forced out. As shown in the thirteenth figure, a plurality of conductive contacts 54 are then placed on the other surface 5 3 of the substrate 5 opposite to the circuit routing surface 50. Each conductive contact 54 is electrically connected to the electroplated layer of the corresponding plated through-hole 52 of the substrate 5. If it is the same as the previous embodiment, through the conductive contacts 54, the wafer package can perform conventional wafer testing and burn-in (burr) by means of a test fixture (not shown). n- i η) test. After the test is completed, the wafer package can be cut into individual csp (Ch i p S 丨 z e

第14頁 r 14 3 9 G Zl ______ 五、發明說明（12)Page 14 r 14 3 9 G Zl ______ V. Description of the invention (12)

Package)成品 0 應要注意的是，黏膠層1 0 2 0亦可以先與該基板5黏接 而然後再與該晶圓1的該至少一個晶片區域1 0黏接。 請參閱第十四圖所示，於該晶圓1 之晶片區域1 0的各 個焊墊1 00上，係能夠以打線機（圖中未示）植入一導電 體30。在本實施例中，該等導電體30是為導電金球。 接者，如苐十五圖所顯不般，於該晶圓1 之至少一個 晶片區域1 0的安裝表面1 0 1上係置放有一黏膠層丨〇 2 。在 本實施例中’該晶圓1之所有晶片區域1 〇的安裝表面丨〇 i 皆置放有一黏膠層102 。各黏膠層102係形成有數個用於 暴露對應之晶片區域10之焊整100之導電體30的開孔 其後’本實施例之封裝方法餘下的步驟係與第 十三圖所示的相同，於此恕不再贅述。 、 ~至 綜上所述，本發明之『半導體晶圓封裝體及复 方法』’確能藉上述所揭露之構造、裝置，4 t U之封農 的與功效，且申請前未見於刊物亦未公開使二功之目 專利之新穎、進步等要件。 符合發明Package) Finished product 0 It should be noted that the adhesive layer 1020 can also be adhered to the substrate 5 first, and then adhered to the at least one wafer region 10 of the wafer 1. Please refer to the fourteenth figure. On each pad 100 of the wafer area 10 of the wafer 1, a conductor 30 can be implanted by a wire bonding machine (not shown). In this embodiment, the conductive bodies 30 are conductive gold balls. Then, as shown in FIG. 15, an adhesive layer 1 2 is placed on the mounting surface 10 1 of at least one wafer area 10 of the wafer 1. In this embodiment, an adhesive layer 102 is placed on the mounting surfaces of all the wafer regions 10 of the wafer 1. Each of the adhesive layers 102 is formed with a plurality of openings for exposing the conductors 30 of the soldering 100 of the corresponding wafer region 10, and thereafter the remaining steps of the packaging method of this embodiment are the same as those shown in FIG. , I will not repeat them here. ~ To sum up, the "semiconductor wafer package and complex method" of the present invention can indeed use the structure and device disclosed above, 4 t U of the farmer and the efficacy, and has not been seen in the publication before the application. The requirements for the novelty and progress of the patent for the second function are not disclosed. Meet the invention

惟，上述所揭之圖式及說明，僅為本發明 A 已’非為限定本發明之實施例；大凡熟悉該項二允例而 ，其所依本發明之特徵範疇，所作之其他等效槪藝之人仕 ’皆應涵蓋在以下本案之申請專利範圍内。"欠化或修飾However, the drawings and descriptions disclosed above are merely examples of the present invention, and are not intended to limit the embodiments of the present invention. Anyone who is familiar with the second permitted example, and other equivalents made according to the characteristic scope of the present invention, The people of Yiyi should be covered by the scope of patent application in the following case. " Undergraded or modified

Claims (1)

m m 六、申請專利範圍 1. 一種半導體晶圓 一未經切割 晶片區域具有一 各晶片區 一覆 具有一與 跡佈設表 數個焊點 路軌跡佈 數個 一個晶片 數個 設表面與 用以將該 及 ，包含： ，該晶圓 烊墊之絕 與其之内 少—個晶 片區域之 至少一個 佈設表面 應的電路 導電體將 焊墊電氣 塊係形成 片區域的 個 曰曰 域上的 蓋該晶 該至少 面並對 於該電 設表面 導電體 區域之 凸塊， 該至少 基板與 封裴體 的晶圚 安裝有 焊墊係 圓之至 —個晶 應於該 路執跡 上之對 ’該等 對應的 §玄等凸 一個晶 該至少 具有數 緣的焊 部電路 片區域 安裝表 晶片區 上，該 軌跡電 該基板 連接； 於該基 安裝表 區域保 個晶片 墊安裝 電氣連 的基板 面相對 域之焊 等焊點 氣連接 的焊點 面中之 區域*各 表面，於 接； ，該基板 的電路軌 墊形成有 係與該電 _ 與該至少 板的電路軌跡佈 者上， 持一預定距離； — 數個導電觸點，該等導電觸點係置於該基板之與該 電路軌跡佈設表面相對的表面上並且係與該基板之該電 路執跡佈設表面上之對應的電路軌跡電氣連接。 如申請專利範圍第1項所述之封裝體，更包含灌注於碎 基板與該晶圓之該至少一個晶片區域之間，用以進—步 防止該基板從該晶圓脫離及確保該基板與該至少—個晶 片區域之間成真空狀態的膠質材料。 如申請專利範圍第2項所述之封裝體，其中，該膠質材 料是為環氧樹脂。mm 6. Application for Patent Scope 1. A semiconductor wafer, an uncut wafer area, each wafer area is covered with a track layout table, several solder joint paths, track layouts, one wafer, several surfaces, and The sum includes:, the wafer pad is absolutely not within—at least one of the wafer areas should be provided with a circuit conductor, and the pad electrical block is formed to cover the crystal on the individual areas of the wafer area. The at least surface and the bumps on the surface-conductor region of the electrical device, the at least the substrate and the crystal body of the sealing body are installed with solder pads to the circle-one crystal should be on the road track to the corresponding ones § Xuan et al. A chip with at least several edges of the solder chip circuit area mounting surface wafer area, the track is electrically connected to the substrate; in the base installation surface area, a wafer pad is installed to electrically connect the substrate surface to the opposite area of the substrate. The regions on the solder joint surface where the solder joints are gas-connected are connected to each other; the circuit track pads of the substrate are formed with Electrically_ at a predetermined distance from the circuit trace distributor of the at least board;-a number of conductive contacts which are placed on the surface of the substrate opposite to the circuit trace layout surface and are connected to the Corresponding circuit traces on the circuit track layout surface of the substrate are electrically connected. The package according to item 1 of the scope of patent application, further comprising pouring between the broken substrate and the at least one wafer region of the wafer to further prevent the substrate from detaching from the wafer and ensure that the substrate and The colloidal material is in a vacuum state between the at least one wafer region. The package according to item 2 of the scope of patent application, wherein the gum material is epoxy resin. 第16頁 六'申請專利範圍 如申请專利範圍第1項所述之封袈體’其中，該等導電 是t導電金屬膠形成。 ’°申，專利範圍第4項所述之封裝體，其中，該導電金 勝疋為摻雜有金、銀、銅和鐵等導電金屬材料中之一 、種的導電金屬膠。 ^申5青專利範圍第1項所述之封裝體’其中，該等凸塊 『.疋由導電金屬膠形成。 ’ ^ ^專利範圍第6項所述之封裝體，其中，該導電金 穆'疋為推雜有金、銀、銅和鐵等導電金屬材料中之一 3種的導電金屬膠。 自申明專利範圍第1項所述之封裝體’其中，該等導電 觸點是為錫球。 9 士 由 體清專利範圍第1項所述之封裝體，其中，該等導電 具有一從該至少—個晶片區域之對應之焊墊延伸出 來^的^{由立R Ώ 對 T u丨及—形成於該延伸部之自由端且與該基板之 1 〇如W之^旱點之導電體電氣連接的擴大部。 係=h專利範圍第1項所述之封裝體，其中，該基板 I成有數個電鍍貫孔’於形成各電鍍貫孔之孔壁上 係電鍵右_ I* 層與該基板之電路轨跡佈設表面上之對應 Π. —藉跡和對應之導電觸點電氣連接的電鍍層。w 牛導體晶圓封裝體，包含： ' 各晶片ί ί Γ割的晶® ’該晶圓具有數個晶片區域’ ，於各^二了有—安裝有焊墊之絕緣的焊墊安裝表面 區域上的嬋塾係與其之内部電路電氣連接Page 16 VI. Scope of patent application The seal body as described in item 1 of the scope of patent application, wherein the conductivity is formed by t conductive metal glue. The package according to item 4 of the patent application, wherein the conductive gold is a conductive metal paste doped with one or more kinds of conductive metal materials such as gold, silver, copper, and iron. ^ The package described in item 5 of the patent scope of Shen 5 ', wherein the bumps "." Are formed of conductive metal glue. ^ ^ The package according to item 6 of the patent scope, wherein the conductive gold is a conductive metal paste mixed with one of three kinds of conductive metal materials such as gold, silver, copper, and iron. The package ’described in item 1 of the self-declared patent scope, wherein the conductive contacts are solder balls. 9 The package described in item 1 of the patent scope of Titsui, wherein the conductive members have a ^ {extending from the corresponding pads of the at least one wafer area ^^ by 立 R Ώ 对 T u 丨 and -An enlarged portion formed at the free end of the extension portion and electrically connected to a conductive body of the substrate such as a dry point of W. Is the package described in item 1 of the patent scope, wherein the substrate I is formed with a plurality of plated through holes' on the wall of the hole forming each plated through hole is a key _ I * layer and the circuit trace of the substrate Corresponding UI on the laying surface. —Plating layer electrically connected to the borrow track and the corresponding conductive contact. w Titanium conductor wafer package, including: 'Each wafer ί Γ Γ cut crystal' 'This wafer has several wafer areas', each of which is provided—insulation pad mounting surface area with pads installed Electrical connection on the board and its internal circuit Η 麵 第17頁 六、 12. 13. 14. 15. *4 326 4 7 申請專利範圍 ----— 至少一個覆蓋該晶圓之一個晶片區域的黏膠層， 該黏勝層係黏接至該一個晶片區域的安裝表面並且係 形成有至少一個用於暴露該一個晶片區域之焊墊的開 孔； 一覆蓋該晶圓之至少一個晶片區域的基板，該基 板具有一黏接至該黏膠層的電路軌跡佈設表面並對應 於該一個晶片區域的焊墊形成有數個焊點，該等焊點 係與S亥電路軌跡佈設表面上之對應的電路軌跡電氣連 接； 數個導電體’該等導電體將該基板的焊點與該一 個晶片區域之對應的焊墊電氣連接；及 數個導電觸點，該等導電觸點係置於該基板之與 β哀電路執跡佈設表面相對的表面上並且係與該基板之 該電路軌跡佈設表面上之對應的電路軌跡電氣連接。 如申請專利範圍第11項所述之封裝體，更包含灌注於 該等導電體容置空間内，用以進一步防止該基板從該 晶圓脫離及確保該等導電體容置空間成真空狀態的膠 質材料。 如申請專利範圍第u項所述之封裝體，其中’該等導 電體是由導電膠形成。 如申請專利範圍第13項所述之封裝體，其中，該導電 膠是為導電銀膠。 如申請專利範圍第11項所述之封裝體，其中’該基板 r ^4 32 6 4 六、申請專利範圍 _ 係形成有數個電鍍貫孔，於 係電鍍有-層與該基板之雷敗各電鍍貫孔之孔壁上 之電路軌跡和對應之導電 f佈設表面上之對應 1 6. —種半導體晶圓封裝體的裝方=連接的電鍍層。 : 瑕方法，包含如下之步驟 提供一未經切割的车道 晶片區域，各晶片區域具 曰曰圓，該晶圓包含數個 焊墊安裝表面，於各晶片、F :用以安裝焊墊之絕緣的 電路電氣連接； M域上的焊墊係與其之内部 把一用以覆蓋該晶圊之曰 圓之上，該鋼板係形成有=片區域的鋼板置於該晶 之焊墊的開孔且係於該馨鬥用於暴露該等晶片區域 在形成各開孔的孔壁與對庙^ ^側形成有數個貫孔， 體形成空間，而在形成各=|曰墊之間係形成—導電 域的安裝表面之間係形成貝Λ的孔壁與對應之晶片區 成一凸塊形忐* Ρ气. 以導電金屬膠為材料刹田e小成工間， 成空間内形成一導電體及 17刷手段於各導電體形 塊； 於各凸塊形成空間内形成凸 在移去該晶圓上的鋼柄 塊進行加熱烤乾處理以# ’對該等導電體和凸 塊； 成為帶硬性的導電體和凸 提供一覆蓋該晶圓之 — 該基板具有一佈設有電 二：個晶片區域的基板’ 對應於該至少一個晶片F β Μ'的電路佈設表面並且係 Q域的焊墊於該電路軌跡佈設第 Page 17 VI. 12. 13. 14. 15. * 4 326 4 7 Scope of patent application-at least one adhesive layer covering a wafer area of the wafer, the adhesive layer is adhered To the mounting surface of the one wafer region and forming at least one opening for exposing the pads of the one wafer region; a substrate covering at least one wafer region of the wafer, the substrate having an adhesive bonded to the adhesive The circuit trace layout surface of the adhesive layer and a plurality of solder joints formed on the pads corresponding to the one wafer area are electrically connected to the corresponding circuit traces on the circuit trace layout surface of the Hai circuit; And other electrically conductive bodies electrically connect the solder joints of the substrate to the corresponding pads of the one wafer area; and several conductive contacts, which are placed on the substrate opposite to the surface of the beta circuit track On the surface and electrically connected to the corresponding circuit track on the circuit track layout surface of the substrate. For example, the package described in item 11 of the scope of the patent application further includes a perfusion filled in the conductor receiving spaces to further prevent the substrate from detaching from the wafer and to ensure that the conductor receiving spaces are in a vacuum state. Gummy material. The package according to item u of the scope of patent application, wherein the conductive bodies are formed of conductive adhesive. The package according to item 13 of the patent application scope, wherein the conductive paste is a conductive silver paste. The package as described in item 11 of the scope of patent application, where 'the substrate r ^ 4 32 6 4 6. The scope of the patent application _ is formed with a number of plated through-holes, each of which has a plated layer and a lightning failure of the substrate Correspondence between the circuit trace on the hole wall of the plated through hole and the corresponding conductive f layout surface. 6. Type of mounting of a semiconductor wafer package = connected plating layer. : Defect method, including the steps of providing an uncut lane wafer area, each wafer area has a circle, the wafer includes several pad mounting surfaces, and on each wafer, F: insulation for mounting pads The electrical connection of the circuit; the pad on the M domain is placed inside it with a pad to cover the crystal circle, the steel plate is formed with a sheet area of the steel plate in the opening of the crystal pad and It is attached to the Xindou to expose the areas of the wafers. Several through holes are formed on the wall of the holes and the opposite side of the temple. The body forms a space, and is formed between the conductive pads and the conductive pads. Between the mounting surfaces of the domains, a hole wall is formed between the hole and the corresponding wafer area to form a bump-shaped gas. The conductive metal glue is used as a material in a small workshop, and a conductive body is formed in the space. The brush means is applied to each conductor-shaped block; a steel handle block protruding from the wafer is formed in each of the bump-forming spaces to be heated and dried to # 'these conductors and bumps; and become rigid conductive The body and bump provide a cover for the wafer — the The substrate has a substrate provided with two substrates: a substrate area of a wafer region ’corresponding to the circuit layout surface of the at least one wafer F β Μ ′ and the pads of the Q domain are laid on the circuit track 第19頁 τ Ρ432647 六、申請專利範圍 表面上形成有數個焊點，該基板的該等焊點係與該電 路轨跡佈設表面上之對應的電路軌跡電氣連接； 把一用以覆蓋該基板的鋼板置於該基板之上，該 鋼板係形成有數個用於暴露該基板之該等焊的開孔， 在形成各開孔的孔壁與該基板之對應的烊點之間係形 成一導電體形成空間； 以導電金屬膠為材料利用印刷手段於各導電體形 成空間内形成一導電體； 在該基板上之鋼板被移除之後，藉著該等凸塊把 該晶圓與該基板分隔一預定距離’把該至少一個晶片 區域之焊墊的導電體與該基板之對應之焊點的導電體 炼接在一起；及 於該基板之與該電路軌跡佈設表面相對的另一表 面上設置有數個導電觸點’該等導電觸點係與該基板 之對應的電路轨跡電氣連接。 1 7.如申請專利範圍第1 6項所述之方法，更包含如下之步 驟： 於該基板與該至少一個晶片區域之間，灌注用以 進一步防止該基板從該晶圓脫離及確保該基板與該至 少一個晶片區域之間成真空狀態的膠質材料。 1 8 ·如申請專利範圍第1 7項所述之方法，其中，在該灌注 步驟中，該膠質材料是為環氧樹脂。 1 9 ·如申請專利範圍第1 6項所述之方法’其中，在形成導 電體和凸塊的步驟中，該等導電體是由導電金屬勝形Page 19 τ P432647 6. Several solder joints are formed on the surface of the scope of the patent application. The solder joints of the substrate are electrically connected to the corresponding circuit traces on the circuit trace layout surface; A steel plate is placed on the substrate, and the steel plate is formed with a plurality of openings for exposing the welding of the substrate. A conductive body is formed between the hole wall forming each opening and the corresponding spot of the substrate. Forming a space; using conductive metal paste as a material to form a conductive body in each conductive body forming space by printing means; after the steel plate on the substrate is removed, the wafer is separated from the substrate by the bumps Predetermined distance ': The conductors of the pads of the at least one wafer region and the conductors of the corresponding solder joints of the substrate are fused together; Conductive contacts' These conductive contacts are electrically connected to corresponding circuit traces of the substrate. 17. The method according to item 16 of the scope of patent application, further comprising the following steps: between the substrate and the at least one wafer region, infusion is used to further prevent the substrate from detaching from the wafer and ensure the substrate A colloidal material in a vacuum state with the at least one wafer region. 18 · The method according to item 17 of the scope of patent application, wherein in the pouring step, the gum material is epoxy resin. 1 9 · The method as described in item 16 of the scope of patent application, wherein in the step of forming the conductor and the bump, the conductor is formed by a conductive metal. >2132β47 六、申請專利範圍 成。 2 0,如申請專利範圍第丨9頊所述之方法’其中，在形成導 電體和凸塊的步驟中，該導電金屬膠是為摻雜有金、 銀、銅和鐵等導電金屬材料中之一種的導電金屬膠。 2 1 ·如申請專利範圍第1 6項所述之方法’其中’在形導電 體和凸塊的步驟中，該等凸塊疋由導電金屬膠形成β 22.如申請專利範圍第21項所述之方法，其中，在形導電 體和凸塊的步驟中，該導電金屬膠疋為摻雜有金、銀 、銅和鐵等導電金屬材料中之一種的導電金屬膠。 2 3.如申請專利範圍第1 6項所述之方法，其中，在形成導 電觸點的步驟中，該等導電觸點是為錫球。 2 4.如申請專利範圍第1 6項所述之方法’其中，在形成導 電體和凸塊的步驟中，該等導電體各具有一從該至少 一個晶片區域之對應之煤蟄延伸出來的延伸部及一形 成於該延伸部之自由端直與該基板之對應之焊點電氣 連接的擴大部。 2 5.如申請專利範圍第1 6項所述之方法’其中’在提供基 板的步驟中，該基板係形成有數個電鑛貫孔’於形成 各電鍍貫孔之孔壁上係電鍍有一層與該基板之電路轨 跡佈設表面上之對應之電路轨跡和對應之導電觸點電 氣連接的電鍵唐。 2 6 * —種半導體晶圓封裴體的封裝方法’包含如下之步驟 提供一未經切割的半導體晶圓，該晶圓包含數個> 2132β47 6. Scope of patent application. 2 0. The method described in the scope of application for patent No. 丨 9 ', wherein in the step of forming the conductor and the bump, the conductive metal paste is doped in a conductive metal material such as gold, silver, copper, and iron. One kind of conductive metal glue. 2 1 · The method described in item 16 of the scope of patent application 'wherein' in the step of forming the conductor and the bumps, the bumps 疋 are formed of conductive metal glue β 22. In the method described, in the step of forming the conductor and the bump, the conductive metal paste is a conductive metal paste doped with one of the conductive metal materials such as gold, silver, copper, and iron. 2 3. The method according to item 16 of the scope of patent application, wherein in the step of forming conductive contacts, the conductive contacts are solder balls. 2 4. The method according to item 16 of the scope of the patent application, wherein in the step of forming the conductors and the bumps, each of the conductors has an extending from a corresponding coal gangue of the at least one wafer region. The extension portion and an enlarged portion formed on the free end of the extension portion and electrically connected to corresponding solder joints of the substrate. 2 5. The method described in item 16 of the scope of the patent application, wherein, in the step of providing the substrate, the substrate is formed with a plurality of electrical ore through holes, and a layer is plated on the wall of the hole forming each of the plated through holes. A corresponding key on the circuit track layout surface of the substrate and a corresponding key electrically connected to the corresponding conductive contact. 2 6 * —A method for packaging a semiconductor wafer package ’includes the following steps: An uncut semiconductor wafer is provided, and the wafer includes several 第21頁 Γ 蹶4326 4 7 六、申請專利範圍 晶片區域，各晶片區域為 焊墊安裝表面，於各0曰^有—用以安裝焊墊之絕緣的 電路電氣連接； 0片區域上的焊塾係與其之内部 把一用以覆蓋該晶圖^ 圓之上，該鋼板係形成曰曰片區域的鋼板置於該晶 之焊塾的開孔，在形成=個用於暴露該等晶片區域 間係形成一導電體形成空間· a 以導電金屬膠為材料士丨^ 成空間内形成一導電體]用印刷手段於各導電體形 在移去該晶圓上的麵此^ > ,綱板之後，對該等導電體進行 提供至少-個覆ίίτΓ導電體； 声，爷至少個敖暾ί曰一個晶片區域的黏膠 域的安裝表面上，並且係形成有至少-個用 一個晶片區域之焊墊之導電體的開孔； 、+賂邊 提供一覆蓋該晶圓之至少一個曰 該基板具有-佈設有電路軌跡的電：佈：丄u板’ 對應於該至少一個晶片區域的焊墊於該^ ς跗士係 表面上形成有數個焊點，該基板的=:佈設 路軌跡佈設表面上之對應的電路軌跡與該電 把一用以覆蓋該基板的鋼板置於玆^ . 鋼板係形成有數個用於暴露該基板之^ |之上，該 在形成開孔的孔壁與該基板之對應的煙$ =的開孔， —導電體容置空間； 绊點之間係形成Page 21 Γ 蹶 4326 4 7 VI. Patent Application Wafer area, each wafer area is a pad mounting surface, and there is an electrical connection for the insulated circuit used to install the pad; soldering on the 0 area The steel plate and the inside thereof are used to cover a circle of the crystal pattern, and the steel plate is formed into an opening of the welding plate of the crystal plate. A conductive body forming space is formed in the system. A Conductive metal glue is used as a material. A conductive body is formed in the space.] Using printing methods, the surface of each conductive body on the wafer is removed. ^ ≫ After that, at least one conductive conductor is provided to these conductive bodies; at least one adhesive area on the mounting surface of the wafer area is formed, and at least one wafer area is formed. The openings of the conductive body of the pad; + The edge of the pad provides at least one covering the wafer. The substrate has-a circuit traced with electricity: cloth: 板 u board 'corresponding to the pad of the at least one wafer area In the ^ 跗 跗 series There are several solder joints formed on the surface. The corresponding circuit traces on the substrate's =: layout path traces and the surface are placed with a steel plate covering the substrate. The steel plate system is formed with several for exposing the Above the substrate, the hole wall forming the opening and the opening corresponding to the smoke $ = of the substrate, the conductor receiving space is formed between the trips; 第22頁Page 22 r ^4326 4 7 六、申請專利範圍 以導電金屬膠為材料利用印刷手段於各導電體形 成空間内形成一導電體； 在該基板上之鋼板被移除之後，將該黏膠層與該 基板的電路軌跡佈設表面黏接並把該一個晶片區域之 焊墊的導電體與該基板之對應之焊點的導電體熔接在 一起；及 於該基板之與該電路轨跡佈設表面相對的另一表 面上設置有數個導電觸點，該等導電觸點係與該基板 之對應的電路軌跡電氣連接。 2 7.如申請專利範圍第2 6項所述之方法，更包含如下之步 驟： 於該至少一個黏膠層的開孔内，灌注用以進一步 防止該基板從該晶圓脫離及確保開孔内成真空狀態的 膠質材料。 28.如申請專利範圍第26項所述之方法’其中，在形成導 電體的步驟中，該等導電體是由導電金屬膠形成。 2 9.如申請專利範圍第2 7項所述之方法，其中，在形成導 電體的步驟中，該導電金屬膠是為摻雜有金、銀、銅 和鐵等導電金屬材料中之一種的導電金屬膠。 3 0.如申請專利範圍第2 6項所述之方法’其中，在提供基 、 板的步驟中，該基板係形成有數個電鍍貫孔，於形成 各電鍍貫孔之孔壁上係電鍍有一層與該基板之電路軌 跡佈設表面上之對應之電路軌跡和對應之導電觸點電 氣連接的電鍍層。r ^ 4326 4 7 6. Scope of the application for patent Use conductive metal glue as a material to form a conductive body in each conductive body forming space by printing means; after the steel plate on the substrate is removed, the adhesive layer and the substrate The circuit trace layout surface is adhered and the conductors of the pads of the one wafer area are fused with the conductors of the corresponding solder joints of the substrate; and the other of the substrate is opposite to the circuit trace layout surface A plurality of conductive contacts are arranged on the surface, and the conductive contacts are electrically connected to corresponding circuit traces of the substrate. 2 7. The method according to item 26 of the scope of patent application, further comprising the following steps: in the opening of the at least one adhesive layer, injecting to further prevent the substrate from detaching from the wafer and ensuring the opening Gummy material in a vacuum state. 28. The method according to item 26 of the scope of the patent application, wherein in the step of forming the conductors, the conductors are formed of a conductive metal paste. 2 9. The method according to item 27 of the scope of patent application, wherein in the step of forming the conductor, the conductive metal paste is doped with one of the conductive metal materials such as gold, silver, copper, and iron. Conductive metal glue. 30. The method according to item 26 of the scope of the patent application, wherein in the step of providing the substrate and the plate, the substrate is formed with a plurality of plated through holes, and the wall of each hole forming the plated through holes is plated with A layer of electroplating layer electrically connected to the corresponding circuit track and the corresponding conductive contact on the circuit track layout surface of the substrate. 第23頁 JE4 32 6 4 〇、申請專利範圍 31 _ —種半導體晶圓封裝 * 提供一未經切割 晶片區域，各晶片區 焊墊安裝表面，於各 電路電氣連接； 利用打線機於各 體的封裝方法’包含如下之步驟 :半導體晶圓，該晶圓包含數個 ，具有—用以安裝焊墊之絕緣的 曰片區域上的焊墊係與其之内部 導電體形成空間内植入一導電體 層 提供 該至 域的安裝 —個晶片 提供 該基板具 對應於該 表面上形 路轨跡佈 把一 鋼板係形 在形成開 一導電體 以導 成空間内 在該 至少一個覆 少一個黏膠 表面上，並 區域之谭塾 一覆蓋該晶 有一佈設有 至少一個晶 成有數個焊 設表面上之 用以覆蓋該 成有數個用 孔的孔壁與 容置空間； 電金屬膠為 形成一導電 基板上之鋼 蓋該晶 層黏接 且係形 之導電 圓之至 電路轨 片區域 點，該 對應的 基板的 於暴露 該基板 圓之一 至該晶 成有至 體的開 少一個 跡的電 的焊墊 基板的 電路執 鋼板置 該基板 之對應 個晶片區 圓之該一 少一個用 孔； 晶片區域 路佈設表 於該電路 該等焊點 跡電氣連 於該基板 之該等焊 的焊點之 域的黏膠 個晶片區 於暴露該 的基板， 面並且係 執跡佈今 係與讀； 接；電 之上，診 的開孔f 材料利用印刷手段於各導電 體； 體形 板被移除之後，將該黏膠層與兮 r F4 326 4 7 六、申請專利範圍 基板的電路轨跡佈設表面黏接並把該一個晶片區域之 焊墊的導電體與該基板之對應之焊點的導電體熔接在 —起；及 於該基板之與該電路軌跡佈設表面相對的另一表 面上設置有數個導電觸點，該等導電觸點係與該基板 之對應的電路軌跡電氣連接。 3 2.如申請專利範圍第3 1項所述之方法，更包含如下之步 驟： 於該至少一個黏膠層的開孔内，灌注用以進一步 防止該基板從該晶圓脫離及確保開孔内成真空狀態的 膠質材料。 3 3.如申請專利範圍第3 1項所述之方法，其中，在植入導 電體的步驟中，該等導電體是為導電金球。 3 4.如申請專利範圍第3 1項所述之方法，其中，在形成導 電體的步驟中，該導電金屬膠是為摻雜有金、銀、銅 和鐵等導電金屬材料中之一種的導電金屬膠。 3 5 .如申請專利範圍第3 1項所述之方法，其中，在提供基 板的步驟中，該基板係形成有數個電鍍貫孔，於形成 各電鍍貫孔之孔壁上係電鍍有一層與該基板之電路軌 跡佈設表面上之對應之電路轨跡和對應之導電觸點電 氣連接的電鑛層。Page 23 JE4 32 6 4 〇 Application Patent Range 31 _ —Semiconductor wafer package * Provides an uncut wafer area, each wafer area has a pad mounting surface, and is electrically connected to each circuit; a wire bonding machine is used for each body. The packaging method includes the following steps: a semiconductor wafer including a plurality of wafers having a pad on an insulated region for mounting pads and an inner conductor forming space in which a pad is implanted; Provide the installation of this domain—a wafer provides the substrate with a track pattern on the surface, and a steel plate is formed on the surface to form an electrical conductor to guide the space on the at least one adhesive-covered surface, and In the area, Tan Ying covers the crystal and has a cloth with at least one crystal formed on several welding surfaces to cover the hole wall and accommodation space formed with several holes; the electric metal glue is a steel forming a conductive substrate Cover the point where the crystal layer is adhered and shaped to the circuit track area point, and the corresponding substrate is exposed to one of the substrate circles to the crystal formation. The circuit board of the electric pad substrate with one trace at least to the body is provided with the one and one hole for the corresponding wafer area circle of the substrate; the chip area route is arranged on the circuit and the solder traces are electrically connected to The adhesive wafer area of the solder joints of the substrate is exposed to the substrate, and the surface is connected with the reading; the connection; the electrical openings, the diagnosis of the opening f material using printing methods on After the body-shaped board is removed, the adhesive layer is bonded to the surface of the circuit trace layout of the patent-applied substrate and the conductive body of the pad of the one wafer area is bonded to The conductors of the corresponding solder joints of the substrate are welded together; and a plurality of conductive contacts are provided on the other surface of the substrate opposite to the surface on which the circuit track is arranged, and the conductive contacts correspond to the substrate Circuit traces for electrical connections. 3 2. The method according to item 31 of the scope of patent application, further comprising the following steps: in the opening of the at least one adhesive layer, injecting to further prevent the substrate from detaching from the wafer and ensuring the opening Gummy material in a vacuum state. 3 3. The method according to item 31 of the scope of patent application, wherein in the step of implanting the conductors, the conductors are conductive gold balls. 34. The method according to item 31 of the scope of patent application, wherein in the step of forming the conductor, the conductive metal paste is doped with one of the conductive metal materials such as gold, silver, copper, and iron. Conductive metal glue. 35. The method according to item 31 of the scope of patent application, wherein in the step of providing the substrate, the substrate is formed with a plurality of plated through holes, and a layer and The circuit traces of the substrate are provided with corresponding circuit traces on the surface and electric ore layers electrically connected to the corresponding conductive contacts. 第25頁Page 25
TW088123432A 1999-12-31 1999-12-31 Semiconductor wafer package and the packaging method thereof TW432647B (en)

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TW088123432A TW432647B (en) 1999-12-31 1999-12-31 Semiconductor wafer package and the packaging method thereof
DE10018638A DE10018638A1 (en) 1999-12-31 2000-04-14 Compact semiconductor element comprises a wafer having a chip region, a substrate arranged on the chip region, conducting bodies, a distancing device between the wafer and the substrate and component contacts
JP2000117937A JP2001194424A (en) 1999-12-31 2000-04-19 Package-type semiconductor integrated circuit and its manufacturing method

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JP3263859B2 (en) * 1992-04-21 2002-03-11 ソニー株式会社 Semiconductor device
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US5436503A (en) * 1992-11-18 1995-07-25 Matsushita Electronics Corporation Semiconductor device and method of manufacturing the same
JPH07231020A (en) * 1994-02-16 1995-08-29 Toshiba Corp Manufacture of semiconductor chip with area pad
US5400950A (en) * 1994-02-22 1995-03-28 Delco Electronics Corporation Method for controlling solder bump height for flip chip integrated circuit devices
DE19507547C2 (en) * 1995-03-03 1997-12-11 Siemens Ag Method of assembling chips
US5598036A (en) * 1995-06-15 1997-01-28 Industrial Technology Research Institute Ball grid array having reduced mechanical stress
KR100222299B1 (en) * 1996-12-16 1999-10-01 윤종용 Wafer level chip scale package and method of manufacturing the same
US5953814A (en) * 1998-02-27 1999-09-21 Delco Electronics Corp. Process for producing flip chip circuit board assembly exhibiting enhanced reliability
JPH11345905A (en) * 1998-06-02 1999-12-14 Mitsubishi Electric Corp Semiconductor device
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