TW362173B - Meta-hardened flip-flop - Google Patents

Meta-hardened flip-flop

Info

Publication number
TW362173B
TW362173B TW086108399A TW86108399A TW362173B TW 362173 B TW362173 B TW 362173B TW 086108399 A TW086108399 A TW 086108399A TW 86108399 A TW86108399 A TW 86108399A TW 362173 B TW362173 B TW 362173B
Authority
TW
Taiwan
Prior art keywords
signal
generating
data input
preferably includes
clock signal
Prior art date
Application number
TW086108399A
Other languages
English (en)
Inventor
Hoang P Nguyen
Richard T Schultz
Original Assignee
Lsi Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Logic Corp filed Critical Lsi Logic Corp
Application granted granted Critical
Publication of TW362173B publication Critical patent/TW362173B/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails

Landscapes

  • Logic Circuits (AREA)
TW086108399A 1996-06-28 1997-06-17 Meta-hardened flip-flop TW362173B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/671,862 US5999029A (en) 1996-06-28 1996-06-28 Meta-hardened flip-flop

Publications (1)

Publication Number Publication Date
TW362173B true TW362173B (en) 1999-06-21

Family

ID=24696167

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086108399A TW362173B (en) 1996-06-28 1997-06-17 Meta-hardened flip-flop

Country Status (5)

Country Link
US (1) US5999029A (zh)
EP (1) EP0908011A1 (zh)
AU (1) AU3100997A (zh)
TW (1) TW362173B (zh)
WO (1) WO1998000916A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6531905B1 (en) 2001-12-19 2003-03-11 Neoaxiom Corporation Flip-flop with metastability reduction
US6900665B2 (en) * 2003-06-10 2005-05-31 James Ma Transfer of digital data across asynchronous clock domains
US6906555B2 (en) * 2003-06-10 2005-06-14 James Ma Prevention of metastability in bistable circuits
US6927604B2 (en) * 2003-08-21 2005-08-09 International Business Machines Corporation Clock signal selector circuit with reduced probability of erroneous output due to metastability
US7474134B2 (en) * 2006-05-18 2009-01-06 International Business Machines Corporation Radiation hardened programmable phase frequency divider
US20090257263A1 (en) * 2008-04-15 2009-10-15 Vns Portfolio Llc Method and Apparatus for Computer Memory
US8405853B2 (en) * 2009-07-31 2013-03-26 Ricoh Company, Ltd. Dynamic DEVMODE support
US9647655B2 (en) * 2015-03-27 2017-05-09 Raytheon Company Current to frequency converter

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4093878A (en) * 1976-11-29 1978-06-06 Ncr Corporation De-glitchablenon-metastable flip-flop circuit
JPH01241913A (ja) * 1988-03-23 1989-09-26 Fujitsu Ltd レーシング防止回路
US5014226A (en) * 1988-09-29 1991-05-07 Lsi Logic Corporation Method and apparatus for predicting the metastable behavior of logic circuits
US4963772A (en) * 1989-02-07 1990-10-16 North American Philips Corp., Signetics Div. Metastable-immune flip-flop arrangement
US5036221A (en) * 1989-03-31 1991-07-30 Texas Instruments Incorporated Circuit for eliminating metastable events associated with a data signal asynchronous to a clock signal
JPH031608A (ja) * 1989-05-30 1991-01-08 Mitsubishi Electric Corp マスター・スレーブ型フリップフロップ回路
JP2874097B2 (ja) * 1989-10-24 1999-03-24 富士通株式会社 半導体メモリ装置
US4999528A (en) * 1989-11-14 1991-03-12 Keech Eugene E Metastable-proof flip-flop
US5225723A (en) * 1990-05-24 1993-07-06 Apple Computer, Inc. Circuitry for the timing data output enable pulses
US5045801A (en) * 1990-05-29 1991-09-03 The United States Of America As Represented By The Secretary Of The Air Force Metastable tolerant asynchronous interface
US5047658A (en) * 1990-06-01 1991-09-10 Ncr Corporation High frequency asynchronous data synchronizer
JP2611034B2 (ja) * 1990-07-10 1997-05-21 三菱電機株式会社 遅延回路
US5118974A (en) * 1990-07-19 1992-06-02 National Semiconductor Corporation Tristate circuits with fast and slow OE signals
US5140180A (en) * 1990-08-24 1992-08-18 Ncr Corporation High speed cmos flip-flop employing clocked tristate inverters
US5365122A (en) * 1990-11-09 1994-11-15 Vlsi Technology, Inc. Meta stable resistant signal detector
JPH04348609A (ja) * 1991-05-27 1992-12-03 Nec Kyushu Ltd ラッチ回路
JPH0529888A (ja) * 1991-07-22 1993-02-05 Kawasaki Steel Corp 半導体集積回路
DE4206082C1 (zh) * 1992-02-27 1993-04-08 Siemens Ag, 8000 Muenchen, De
JPH05335899A (ja) * 1992-05-28 1993-12-17 Fujitsu Ltd フリップフロップ回路
JPH065091A (ja) * 1992-06-23 1994-01-14 Mitsubishi Electric Corp 半導体装置
JPH06232704A (ja) * 1993-02-03 1994-08-19 Nippon Steel Corp フリップフロップ回路
US5391935A (en) * 1993-07-22 1995-02-21 International Business Machines Corporation Assertive latching flip-flop
US5398000A (en) * 1994-03-30 1995-03-14 Intel Corporation Simple and high speed BICMOS tristate buffer circuit
EP0691741B1 (en) * 1994-07-05 2004-10-06 Matsushita Electric Industrial Co., Ltd. Latch circuit
EP0713292A3 (en) * 1994-11-21 1997-10-01 Motorola Inc Feedback interlock circuit and its operating method
US5557225A (en) * 1994-12-30 1996-09-17 Intel Corporation Pulsed flip-flop circuit
US5453708A (en) * 1995-01-04 1995-09-26 Intel Corporation Clocking scheme for latching of a domino output
US5636165A (en) * 1995-04-14 1997-06-03 Martin Marietta Corporation Apparatus for and method of facilitating proper data transfer between two or more digital memory elements

Also Published As

Publication number Publication date
EP0908011A1 (en) 1999-04-14
US5999029A (en) 1999-12-07
AU3100997A (en) 1998-01-21
WO1998000916A1 (en) 1998-01-08

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Legal Events

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MK4A Expiration of patent term of an invention patent