US5453708A - Clocking scheme for latching of a domino output - Google Patents
Clocking scheme for latching of a domino output Download PDFInfo
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- US5453708A US5453708A US08/368,335 US36833595A US5453708A US 5453708 A US5453708 A US 5453708A US 36833595 A US36833595 A US 36833595A US 5453708 A US5453708 A US 5453708A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
- H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1738—Controllable logic circuits using cascode switch logic [CSL] or cascode emitter coupled logic [CECL]
Definitions
- the present invention relates to the field of semiconductor devices, and more particularly to transfer of data from domino circuits.
- a variety of latching circuits are known for transferring of data. Generally, these latching circuits receive a data input and generate an output under control of a clocking signal.
- One class of latching circuits is comprised of an input latch, an output latch and some form of circuitry disposed between the two latches for operating on the input data before it is sent as an output from the output latch. In faster circuits, the data transition from input to output is achieved within a single clock cycle.
- domino circuits One form of the above circuitry, in which the circuitry between the latches provides logic operations based on an input signal are known as domino circuits.
- Domino circuits are generally used to evaluate a logic operation based on a given input.
- the logic operation can be performed within one or more logic stages. Where multiple stages are present, an evaluation of one stage is rippled to a subsequent stage until a final evaluation is made in the final stage.
- the effect is for the logic to ripple (“domino") through the various stages, wherein each subsequent stage performs its evaluation based on the previous evaluation. After the completion of the evaluation in the final stage, an output is provided from the domino circuit through the output latch.
- any delaying elements or at least not introduce any additional delaying elements in the data path.
- unwanted conditions such as racing conditions
- a value of a data on a data line can be corrupted due to a presence of an unwanted signal on the data line.
- a desire for speed has corrupted valid data, or has the potential of corrupting data.
- any speed gained without the potential for corrupting data is a significant improvement.
- the present invention resides within this category of improvements, where data transfer speed is enhanced without compromising the validity of that data.
- the present invention provides for an improved latching of an output from a domino circuit by delaying a precharging of a domino node and wherein the delay is achieved in a clocking scheme without introducing the delay in the signal transmission path.
- a domino logic stage is precharged to a predetermined state prior to a first phase of a clocking cycle and an input data signal is made available to the domino stage.
- the input signal is evaluated by the logic of the domino stage(s).
- an output latch latches the domino output from the last domino stage as data output from the domino circuit.
- the domino node is precharged while an input latch couples in the next data signal to the stage for evaluation in the subsequent clocking cycle.
- precharging of the domino node during this precharge phase is delayed until the output latch is deactivated, thereby ensuring that the precharge is not latched out to corrupt the data being transmitted.
- the present invention utilizes gate delays by having the precharge activation signal transition through a plurality of gates so that these inherent gate delays delay the activation of the precharging of the domino node until the output latch is turned off. The delay is imposed in the clocking signal and not in the data path.
- Examples are shown to illustrate the application of domino circuits of the present invention.
- the precharging of a single stage circuit is shown in which the precharge phase is delayed until the output latch is completely shut off.
- two sequential domino stages are shown.
- the examples illustrate the clocking scheme of the present invention, in which precharging of the last domino stage is delayed until the output latch is completely shut off.
- the precharge delay is not introduced in the actual data path.
- FIG. 1 is a schematic diagram of a domino circuit having no delay in the data path, but in which a racing condition can occur if a domino node starts to precharge while data is still being transferred from an output latch.
- FIG. 2 is a schematic diagram to illustrate a domino stage in which transistors are configured serially to evaluate a number of data inputs.
- FIG. 3 is a schematic diagram to illustrate a domino stage in which transistors are configured in parallel to evaluate a number of data inputs.
- FIG. 4 is a schematic diagram to illustrate a domino stage in which transistors are configured both serially and in parallel to evaluate a number of data inputs.
- FIG. 5 is a schematic diagram of a latch circuit which is used as an input latch for the circuit shown in FIG. 1.
- FIG. 6 is a schematic diagram of a latch circuit which is used as an output latch for the circuit shown in FIG. 1.
- FIG. 7 is a timing diagram showing a number of clocking signals associated with the circuit of FIG. 1 and also showing a timing signal of the present invention for delaying the activation of the domino node.
- FIG. 8 is a schematic diagram of the domino circuit of FIG. 1 but with an inclusion of two inverters in the data path for providing delay needed to prevent the precharge from being coupled as an output.
- FIG. 9 is a schematic diagram of the domino circuit of FIG. 1 but with an inclusion of a single inverter in the data path for providing delay needed to prevent the precharge from being coupled as an output.
- FIG. 10 is a schematic diagram of a circuit of the present invention showing only a single domino stage, in which the precharge is delayed by the clocking scheme to ensure that the data output is no corrupted by the precharge, but where there is no delay in the data path.
- FIG. 11 is a schematic diagram of an example of a two stage domino circuit utilizing the precharge delaying scheme of the present invention.
- a clocking scheme for improved latching of an output from a domino circuit is described.
- numerous specific details are set forth, such as specific devices, signals, timing sequences, etc., in order to provide a thorough understanding of the present invention.
- the present invention may be practiced without these specific details.
- well known structures for operation and use of domino circuits have not been described in detail in order not to unnecessarily obscure the present invention.
- circuit 10 for latching a domino output is illustrated.
- the use and operation of circuits for providing a domino output are generally known and circuit 10 is one preferred implementation for providing such output.
- Domino circuits are generally used to "domino" a certain logic state from one stage to another.
- a domino node for each stage is precharged to a preset level (such as logic "1") and then the node responds to one or more input signals.
- the node will respond to the input signal(s) according to the logic configuration for the stage.
- the node response is then latched out and/or coupled to a next stage, wherein the domino output from the first stage now becomes an input or one of multiple inputs to the subsequent stage.
- the transition effect of the logic states through the sequence of stages is analogous to having a ripple (or "domino") effect.
- Circuit 10 is just one representation of such domino circuits.
- stage 15 In circuit 10 of FIG. 1, the portion of the circuitry pertaining to its domino stage 15 is shown enclosed within a dotted-line. Input to the domino stage 15 is shown as input 12, while output 14 represents the output from stage 15. The other input signal to stage 15 is a clocking signal 13.
- the particular circuit of stage 15 shown represents the simplest of domino stages for illustrative purpose. As noted in the figure, stage 15 has only one input data signal.
- domino stage 15 is comprised of three transistors 20-22, coupled in series between a supply source (VCC) and its return, which in this instance is ground.
- VCC supply source
- the two transistors 21-22 closest to ground are n-channel transistors, while transistor 20, which is coupled to VCC, is a p-channel transistor.
- the input 12 is coupled to the gate of transistor 21, while the gates of transistor 20 and transistor 22 are coupled together to receive the clocking signal 13.
- node 23 which is at the junction of the drains of transistors 20 and 21.
- Node 23 (which is referred to as the "domino node") is coupled as output 14.
- a second p-channel transistor 25 which is coupled between node 23 and VCC. Its gate is coupled to node 23 through inverter 26.
- the purpose of transistor 25 is to operate as a "pull-up" device to keep node 23 at VCC potential whenever node 23 has gone high (a higher voltage state, which is also a logic "1" state).
- the operation of transistor 25 is not critical to the understanding of the clocking scheme of the present invention.
- transistors 20 and 22 are coupled together, since it is desirable to control the activation of these transistors by the clocking signal 13, which is also denoted as signal "CLK1 .”
- CLK1 clocking signal 13
- transistor 20 conducts when CLK1 is low (a lower voltage state, which is also a logic "0" state) and transistor 22 conducts when CLK 1 is high.
- transistor 21 will be conducting, depending on the state of the CLK 1 signal.
- the activation of transistor 21 is controlled by the data input 12, but this input 12 is usable only when transistor 22 is on. If the data 12 is high, transistor 21 conducts and when data 12 is low, transistor 21 is shut off.
- the CLK 1 signal controls the operation of the domino stage 15 depending on which portion of the cycle it is in.
- transistor 20 Prior to a first phase (which is the second phase of the previous clock cycle), when CLK 1 is low, transistor 20 conducts to precharge node 23 to a logic "1" state. The purpose of the precharge is to establish node 23 to a preset state (also referred to as a "precharge” state). Also prior to the first phase, a valid input signal 12 is made available at the gate of transistor 21. Then, during the first phase (also referred to as an "evaluate” phase) when CLK1 is high, transistor 22 conducts and transistor 20 shuts off. The input signal 12 will determine if transistor 21 is to conduct.
- the domino stage 15 performs an evaluation based on the input 12 and the logic provided by transistors 20-22.
- FIGS. 2-4 other illustrative examples for domino logic are provided. It is to be appreciated that these illustrations are provided for exemplary purpose and are not intended to limit the types of circuitry which can be used for stage 15 or any other domino stage.
- FIG. 2 a series configuration is shown in which serial arrangement of transistors are disposed between the domino node and the n-channel clocking transistor 22.
- Transistors 27 provide for multiple inputs and in which all of the inputs must be high for the domino node 23 to be pulled low.
- input transistor 21 of FIG. 1 is replaced by a plurality of input transistors 27.
- FIG. 3 a parallel configuration is shown in which a number of input transistors 28 are coupled in parallel between the domino node 23 and the n-channel clocking transistor 22. Essentially, transistor 21 of FIG. 1 is replaced by a plurality of parallel input transistors 28. In this arrangement, conduction of any one of the input transistors 28 will pull the domino node low.
- FIG. 4 shows an arrangement in which both serial and parallel arrangements are used. It is essentially a matrix having "n" row and "m” column arrangement of input transistors 29. Thus, it is to be noted that the arrangements are endless and the particular arrangement selected will depend on the desired logic operation that is to be performed by a domino stage 15. Although the numbers are many, the various designs available are not critical to the understanding of the present invention, but are being presented in order to show the context in which the present invention is utilized.
- circuit 10 shows additional circuit components which are associated with the circuitry of stage 15.
- An input latch 11 is shown coupling data (d in ) as data input to stage 15.
- Latch 11 latches in the data when a clocking signal CLK# goes high (the # symbol is equivalent to the "bar" above the signal name, as shown in the drawings).
- An output latch 24 is shown latching the domino output from node 23. If stage 15 is coupled to other domino type stages, the last stage will usually be coupled to latch 24.
- Output latch 24 latches out the data when the CLK# signal goes low.
- a GCLKD# signal is shown representing a clocking signal, which timing is controlled by a master or system clock. GCLKD# signal is then used to generate clocking signals for controlling the precharge and evaluate phases of circuit 10.
- two inverters 31-32 and NAND gate 30 are used to provide the necessary timing.
- the GCLKD# signal is coupled to one input of NAND gate 30.
- the GCLKD# signal is also coupled through two inverters 31 and 32 to provide the CLK# clocking signal, which is coupled to a second input of NAND gate 30.
- the CLK# signal is coupled as well to the two latches 11 and 24 to provide the clocking of those latches.
- inverters 31 and 32 The purpose of inverters 31 and 32 is to buffer the GCLKD# signal for "fan-out” and to slightly delay the CLK# signal.
- the CLK# signal to the latches 11 and 24 operate to activate inverters from a tri-state position within those latches to allow data signals to be latched through the latches.
- the circuitry for the two latches are shown in FIGS. 5 and 6, but are being provided for exemplary purpose only, since the actual circuit of these latches 11 and 24 are not significant to the operation of the present invention, except for the clocking scheme described below.
- the CLK# signal is coupled to both of the latches 11 and 24, but that it requires a high state to latch data through latch 11 and a low state to latch data through latch 24. Therefore, the CLK# signal causes data d in to be latched in during one half-cycle of the CLK# signal and the domino output to be latched out during the other half-cycle of the CLK# signal.
- the inverted CLK# signal is denoted as CLK2.
- the CLK# signal is essentially the GCLKD# signal, but with a slight built in delay 40 due to the gate delays of inverters 31 and 32.
- the CLK 1 signal is provided by a logical NAND operation of GCLKD# and CLK# and is high whenever either GCLKD# or CLK# is low. There is a slight delay 43 due to the presence of NAND gate 30. Accordingly, the precharge phase occurs when CLK 1 is low. There may be a slight delay from the falling edge of CLK 1 until the start of the precharge phase. However, for all purposes, the precharge phase commences when CLK1 goes low.
- the precharge phase is denoted as the second phase of the clock cycle in the description, but the nomenclature (as to first phase or second phase) is strictly arbitrary. What is important is that there be one phase for evaluating the logic of the domino stage(s) and providing the output. During the other phase, the domino stage is reset by having the domino node 23 precharged and the next input signal made available to the input of the domino stage. Thus, *when CLK1 transitions high again, the next evaluate phase commences.
- the input signal d in drives the input transistor 21. If transistor 21 is turned on due to logic “1" at the input 12, then node 23 transitions from its precharged “1” state to a "0" state during the evaluate phase. If transistor 21 is not on due to logic "0" at input 12, then node 23 remains at the precharged "1” state. Since CLK2 is essentially the inverse of the CLK# signal, but with a slight gate delay 41, it is high at this time to latch the logic state of node 23 out through latch 24.
- this "turn-on" delay may be so short that it becomes difficult to completely turn off the output latch 24 prior to the start of the precharge sequence.
- FIG. 8 One approach to increasing the delay between the turn-off of latch 24 and start of the precharge is to provide a delay between the critical node 23 and output latch 24.
- FIG. 8 One solution is shown in FIG. 8. Referring to FIG. 8, the same circuit as FIG. 1 is shown, except now there are two additional inverters 27 and 28 placed in the path between node 23 and latch 24. The inverters add two additional gate delays in this critical path for the state of node 23 to transition through prior to the input of latch 24. Although the timing of the CLK1 and CLK2 signals have not changed, the inverters 27 and 28 add two additional gate delays between node 23 and the input of latch 24. The two additional gate delays, on top of the transistor 20 gate delay will ensure that the latch 24 is shut off before the precharge value can transition to the latch 24.
- FIG. 9 shows an alternative solution in the event a single gate delay may be sufficient to delay the transfer of the precharge state of node 23 to latch 24. In this instance, applying the same circuit of FIG. 1, only one inverter 27 is used.
- FIGS. 8 and 9 may resolve the precharge delay problem, but add in another problem. That is, the delays are in the actual data signal path and will introduce delays for the data to transition from node 23 to the output latch 24. It is desirable and in the instance of designing microprocessor circuitry, sometimes fatal to introduce undesirable delays in the data path.
- Circuit 35 is the same as circuit 10 of FIG. 1 but with the exceptions noted below. Although not shown, it is understood that a variety of domino circuits can be readily implemented for domino stage 15, as was described in reference to FIG. 1.
- Inverters 36 and 37 are now included to provide the necessary precharge transition delay, but without delaying the data transition. Inverters 36 and 37 introduce the delay at the front end of the precharge sequence and the circuit need not rely on the transition time between node 23 and output latch 24. Essentially, the delay is introduced through the clocking scheme in which the start of the precharge phase is delayed. However, the evaluate phase is not delayed.
- Inverters 36 and 37 are inserted between the output of inverter 32 and input of NAND gate 30. Since no delay is introduced in the path for the CLK# signal, the activations of latches 11 and 24 are not delayed. Furthermore, since the delay is not in the data path, data transfer during the evaluate phase is not delayed. Also, since the NAND gate 30 still has one input coupled directly to GCLKD#, the data transfer period still commences at the falling edge of the GCLKD# signal. However, as noted by the timing diagram of FIG. 7, the clocking signal at the output of the NAND gate 30 is now shown as clocking signal CLK1A. The falling edge is delayed by an additional delay 42 that corresponds to the delay introduced by inverters 36 and 37.
- the inverters essentially lengthens the high state of CLK 1A over the earlier signal CLK1.
- the precharge phase is shortened but the period is still sufficient to fully precharge node 23.
- significant time elapses from the time output latch 24 turns off until node 23 begins to precharge, preventing any possibility for the precharge to feed through to the output of latch 24.
- Circuit 48 is one example of circuitry utilizing two domino stages.
- the domino stage 15 from FIG. 1 forms the second stage, while a separate domino arrangement forms the earlier stage denoted as stage 55.
- transistors 50-52 function equivalently to transistors 20-22, respectively.
- Transistor 54 and inverter 49 function as a "pull-up" similar to transistor 25 and inverter 26.
- the input signal from input latch 11 is now coupled to the gate of transistor 51 and the gates of transistors 50 and 52 are coupled to the output of inverter 31 to obtain the clocking signal for stage 54.
- Domino node 53 of the first stage 55 is coupled as input to the next stage 15.
- the precharge of the first stage 54 is not a concern, since the "ripple" effect transitions all the way to the last domino node (which is node 23 in this instance). It is the timing of the precharge of the last stage 15 in relationship to the data transfer in the output latch 24, which is the concern noted earlier. As was described earlier, the built-in precharge delay of node 23 provides for the necessary delay to ensure that the output data will not be corrupted.
- clocking scheme of the present invention can be used in a variety of circuits and devices.
- the present invention is well suited for implementation in a microprocessor due to the concern for improving data processing and transition times.
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Cited By (81)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5517136A (en) * | 1995-03-03 | 1996-05-14 | Intel Corporation | Opportunistic time-borrowing domino logic |
US5541536A (en) * | 1995-03-01 | 1996-07-30 | Sun Microsystems, Inc. | Rubberband logic |
US5610548A (en) * | 1995-09-08 | 1997-03-11 | International Business Machines Corporation | Split drive clock buffer |
US5614845A (en) * | 1995-09-08 | 1997-03-25 | International Business Machines Corporation | Independent clock edge regulation |
US5623450A (en) * | 1995-09-08 | 1997-04-22 | International Business Machines Corporation | Conditional recharge for dynamic logic |
US5633605A (en) * | 1995-05-24 | 1997-05-27 | International Business Machines Corporation | Dynamic bus with singular central precharge |
US5642061A (en) * | 1995-04-17 | 1997-06-24 | Hitachi America, Ltd. | Short circuit current free dynamic logic clock timing |
US5656963A (en) * | 1995-09-08 | 1997-08-12 | International Business Machines Corporation | Clock distribution network for reducing clock skew |
US5661675A (en) * | 1995-03-31 | 1997-08-26 | Intel Corporation | Positive feedback circuit for fast domino logic |
US5668761A (en) * | 1995-09-08 | 1997-09-16 | International Business Machines Corporation | Fast read domino SRAM |
US5675273A (en) * | 1995-09-08 | 1997-10-07 | International Business Machines Corporation | Clock regulator with precision midcycle edge timing |
US5729501A (en) * | 1995-09-08 | 1998-03-17 | International Business Machines Corporation | High Speed SRAM with or-gate sense |
US5774005A (en) * | 1995-09-11 | 1998-06-30 | Advanced Micro Devices, Inc. | Latching methodology |
WO1998029949A1 (en) * | 1996-12-27 | 1998-07-09 | Intel Corporation | Single-phase domino time borrowing logic with clocks at first and last stages and latch at last stage |
US5796282A (en) * | 1996-08-12 | 1998-08-18 | Intel Corporation | Latching mechanism for pulsed domino logic with inherent race margin and time borrowing |
US5815687A (en) * | 1996-09-19 | 1998-09-29 | International Business Machines Corporation | Apparatus and method for simulating domino logic circuits using a special machine cycle to validate pre-charge |
US5821775A (en) * | 1996-12-27 | 1998-10-13 | Intel Corporation | Method and apparatus to interface monotonic and non-monotonic domino logic |
US5828257A (en) * | 1995-09-08 | 1998-10-27 | International Business Machines Corporation | Precision time interval division with digital phase delay lines |
EP0880231A1 (en) * | 1997-05-19 | 1998-11-25 | Texas Instruments Incorporated | Domino logic circuits |
US5859547A (en) * | 1996-12-20 | 1999-01-12 | Translogic Technology, Inc. | Dynamic logic circuit |
US5880608A (en) * | 1996-12-27 | 1999-03-09 | Intel Corporation | Pulsed domino latches |
US5883529A (en) * | 1996-04-19 | 1999-03-16 | Sony Corporation | Function clock generation circuit and D-type flip-flop equipped with enable function and memory circuit using same |
US5886540A (en) * | 1996-05-31 | 1999-03-23 | Hewlett-Packard Company | Evaluation phase expansion for dynamic logic circuits |
US5896046A (en) * | 1997-01-27 | 1999-04-20 | International Business Machines Corporation | Latch structure for ripple domino logic |
US5920218A (en) * | 1996-09-19 | 1999-07-06 | Sun Microsystems, Inc | Single-phase edge-triggered dual-rail dynamic flip-flop |
US5933038A (en) * | 1997-02-25 | 1999-08-03 | Sun Microsystems, Inc. | Flip-flop with logic function incorporated therein with minimal time penalty |
US5999029A (en) * | 1996-06-28 | 1999-12-07 | Lsi Logic Corporation | Meta-hardened flip-flop |
US6026473A (en) * | 1996-12-23 | 2000-02-15 | Intel Corporation | Method and apparatus for storing data in a sequentially written memory using an interleaving mechanism |
US6037804A (en) * | 1998-03-27 | 2000-03-14 | International Business Machines Corporation | Reduced power dynamic logic circuit that inhibits reevaluation of stable inputs |
US6043696A (en) * | 1997-05-06 | 2000-03-28 | Klass; Edgardo F. | Method for implementing a single phase edge-triggered dual-rail dynamic flip-flop |
US6046606A (en) * | 1998-01-21 | 2000-04-04 | International Business Machines Corporation | Soft error protected dynamic circuit |
EP1028434A1 (en) * | 1999-02-11 | 2000-08-16 | Infineon Technologies North America Corp. | Dynamic logic circuit |
US6140855A (en) * | 1999-03-30 | 2000-10-31 | International Business Machines Corporation | Dynamic-latch-receiver with self-reset pointer |
US6154045A (en) * | 1998-12-22 | 2000-11-28 | Intel Corporation | Method and apparatus for reducing signal transmission delay using skewed gates |
US6184718B1 (en) | 1996-12-20 | 2001-02-06 | Translogic Technology, Inc. | Dynamic logic circuit |
US6201415B1 (en) | 1999-08-05 | 2001-03-13 | Intel Corporation | Latched time borrowing domino circuit |
US6262615B1 (en) | 1999-02-25 | 2001-07-17 | Infineon Technologies Ag | Dynamic logic circuit |
US6265897B1 (en) * | 1999-12-17 | 2001-07-24 | Hewlett-Packard Company | Contention based logic gate driving a latch and driven by pulsed clock |
US6265899B1 (en) | 1999-06-04 | 2001-07-24 | S3 Incorporated | Single rail domino logic for four-phase clocking scheme |
US6271684B1 (en) | 1999-04-08 | 2001-08-07 | Intel Corporation | Method and apparatus for stalling OTB domino circuits |
US6275071B1 (en) | 1999-12-29 | 2001-08-14 | Intel Corporation | Domino logic circuit and method |
US6281710B1 (en) * | 1999-12-17 | 2001-08-28 | Hewlett-Packard Company | Selective latch for a domino logic gate |
US6300801B1 (en) * | 1998-09-28 | 2001-10-09 | Hyundai Electronics Industries Co., Ltd. | Or gate circuit and state machine using the same |
US6316960B2 (en) | 1999-04-06 | 2001-11-13 | Intel Corporation | Domino logic circuit and method |
US6323698B1 (en) | 1999-12-30 | 2001-11-27 | Intel Corporation | Apparatus, method and system for providing LVS enables together with LVS data |
US6323688B1 (en) * | 1999-03-08 | 2001-11-27 | Elbrus International Limited | Efficient half-cycle clocking scheme for self-reset circuit |
US6329857B1 (en) | 1999-12-30 | 2001-12-11 | Intel Corporation | Apparatus, method and system for a logic arrangement having mutually exclusive outputs controlled by buffering cross-coupled devices |
US6339353B1 (en) * | 1999-09-20 | 2002-01-15 | Fujitsu Limited | Input circuit of a memory having a lower current dissipation |
US6346828B1 (en) | 2000-06-30 | 2002-02-12 | Intel Corporation | Method and apparatus for pulsed clock tri-state control |
US6392466B1 (en) | 1999-12-30 | 2002-05-21 | Intel Corporation | Apparatus, method and system for a controllable pulse clock delay arrangement to control functional race margins in a logic data path |
US6404234B1 (en) | 2001-05-09 | 2002-06-11 | Intel Corporation | Variable virtual ground domino logic with leakage control |
US6448818B1 (en) | 1999-12-30 | 2002-09-10 | Intel Corporation | Apparatus, method and system for a ratioed NOR logic arrangement |
US6486706B2 (en) | 2000-12-06 | 2002-11-26 | Intel Corporation | Domino logic with low-threshold NMOS pull-up |
US6492837B1 (en) | 2000-03-17 | 2002-12-10 | Intel Corporation | Domino logic with output predischarge |
US6496038B1 (en) * | 2000-06-30 | 2002-12-17 | Intel Corporation | Pulsed circuit topology including a pulsed, domino flip-flop |
US6518793B2 (en) * | 2000-03-31 | 2003-02-11 | International Business Machines Corporation | Embedding of dynamic circuits in a static environment |
US6529045B2 (en) | 1999-09-28 | 2003-03-04 | Intel Corporation | NMOS precharge domino logic |
US6529861B1 (en) | 1999-07-02 | 2003-03-04 | Intel Corporation | Power consumption reduction for domino circuits |
US6531897B1 (en) | 2000-06-30 | 2003-03-11 | Intel Corporation | Global clock self-timed circuit with self-terminating precharge for high frequency applications |
US6542006B1 (en) | 2000-06-30 | 2003-04-01 | Intel Corporation | Reset first latching mechanism for pulsed circuit topologies |
US6556962B1 (en) | 1999-07-02 | 2003-04-29 | Intel Corporation | Method for reducing network costs and its application to domino circuits |
US6567337B1 (en) | 2000-06-30 | 2003-05-20 | Intel Corporation | Pulsed circuit topology to perform a memory array write operation |
US20030112678A1 (en) * | 2001-12-18 | 2003-06-19 | Hsu Steven K. | Register files and caches with digital sub-threshold leakage current calibration |
US20030237010A1 (en) * | 2002-06-25 | 2003-12-25 | Micron Technology, Inc. | Method and unit for buffer control |
US6677783B2 (en) * | 2001-12-31 | 2004-01-13 | Intel Corporation | High-speed, state-preserving, race-reducing, wide-pulsed-clock domino design style |
US6737888B1 (en) * | 1999-11-08 | 2004-05-18 | International Business Machines Corporation | Method for skipping a latch in timing-sensitive dynamic circuits of a multi-clocked system with unspecific underlap requirement |
US6801057B2 (en) * | 2000-08-18 | 2004-10-05 | Texas Instruments Incorporated | Silicon-on-insulator dynamic logic |
US20040257115A1 (en) * | 2003-04-28 | 2004-12-23 | Via Technologies, Inc. | N-domino output latch with accelerated evaluate path |
US6842046B2 (en) | 2002-01-31 | 2005-01-11 | Fujitsu Limited | Low-to-high voltage conversion method and system |
US6937079B1 (en) | 2003-07-28 | 2005-08-30 | University Of Louisiana At Lafayette | Single-transistor-clocked flip-flop |
US20050189967A1 (en) * | 1999-12-30 | 2005-09-01 | Eitan Rosen | Generalized pre-charge clock circuit for pulsed domino gates |
US20050248368A1 (en) * | 2003-04-28 | 2005-11-10 | Via Technologies, Inc. | P-domino output latch with accelerated evaluate path |
US20060220678A1 (en) * | 2005-03-31 | 2006-10-05 | Transmeta Corporation | Method and system for elastic signal pipelining |
US20070008012A1 (en) * | 2005-06-30 | 2007-01-11 | Masleid Robert P | Scannable dynamic circuit latch |
US20070013425A1 (en) * | 2005-06-30 | 2007-01-18 | Burr James B | Lower minimum retention voltage storage elements |
US7256619B1 (en) * | 2005-04-04 | 2007-08-14 | Sun Microsystems, Inc. | Apparatus to shift to pre-charge mode a dynamic circuit driven by one-shot clock signal during power off mode |
US7495466B1 (en) | 2006-06-30 | 2009-02-24 | Transmeta Corporation | Triple latch flip flop system and method |
US7667916B1 (en) | 2004-04-26 | 2010-02-23 | Marvell International Ltd. | Signal conversion system and method |
US20100103747A1 (en) * | 2008-10-24 | 2010-04-29 | Arm Limited | Memory device and method of operating such a memory device |
US7737749B1 (en) * | 2005-07-06 | 2010-06-15 | Robert Paul Masleid | Elastic pipeline latch with a safe mode |
WO2022191984A3 (en) * | 2021-03-11 | 2022-10-20 | Qualcomm Incorporated | Analog-to-digital converter, phase sampler, time-to-digital converter, and flip-flop |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4568842A (en) * | 1983-01-24 | 1986-02-04 | Tokyo Shibaura Denki Kabushiki Kaisha | D-Latch circuit using CMOS transistors |
US4841174A (en) * | 1985-10-21 | 1989-06-20 | Western Digital Corporation | CMOS circuit with racefree single clock dynamic logic |
US4893034A (en) * | 1987-02-19 | 1990-01-09 | Kabushiki Kaisha Toshiba | Stop/restart latch |
US4929850A (en) * | 1987-09-17 | 1990-05-29 | Texas Instruments Incorporated | Metastable resistant flip-flop |
US5189319A (en) * | 1991-10-10 | 1993-02-23 | Intel Corporation | Power reducing buffer/latch circuit |
US5208489A (en) * | 1986-09-03 | 1993-05-04 | Texas Instruments Incorporated | Multiple compound domino logic circuit |
-
1995
- 1995-01-04 US US08/368,335 patent/US5453708A/en not_active Expired - Lifetime
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4568842A (en) * | 1983-01-24 | 1986-02-04 | Tokyo Shibaura Denki Kabushiki Kaisha | D-Latch circuit using CMOS transistors |
US4841174A (en) * | 1985-10-21 | 1989-06-20 | Western Digital Corporation | CMOS circuit with racefree single clock dynamic logic |
US5208489A (en) * | 1986-09-03 | 1993-05-04 | Texas Instruments Incorporated | Multiple compound domino logic circuit |
US4893034A (en) * | 1987-02-19 | 1990-01-09 | Kabushiki Kaisha Toshiba | Stop/restart latch |
US4929850A (en) * | 1987-09-17 | 1990-05-29 | Texas Instruments Incorporated | Metastable resistant flip-flop |
US5189319A (en) * | 1991-10-10 | 1993-02-23 | Intel Corporation | Power reducing buffer/latch circuit |
Non-Patent Citations (2)
Title |
---|
"The Metaflow Architecture", IEEE Micro., by Val Popescu, Merle Schultz, John Spracklen, Gary Gibson, Bruce Lightner and David Isaman, 1991. |
The Metaflow Architecture , IEEE Micro., by Val Popescu, Merle Schultz, John Spracklen, Gary Gibson, Bruce Lightner and David Isaman, 1991. * |
Cited By (100)
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---|---|---|---|---|
US5541536A (en) * | 1995-03-01 | 1996-07-30 | Sun Microsystems, Inc. | Rubberband logic |
US5517136A (en) * | 1995-03-03 | 1996-05-14 | Intel Corporation | Opportunistic time-borrowing domino logic |
US5661675A (en) * | 1995-03-31 | 1997-08-26 | Intel Corporation | Positive feedback circuit for fast domino logic |
US5642061A (en) * | 1995-04-17 | 1997-06-24 | Hitachi America, Ltd. | Short circuit current free dynamic logic clock timing |
US5633605A (en) * | 1995-05-24 | 1997-05-27 | International Business Machines Corporation | Dynamic bus with singular central precharge |
US5675273A (en) * | 1995-09-08 | 1997-10-07 | International Business Machines Corporation | Clock regulator with precision midcycle edge timing |
US5656963A (en) * | 1995-09-08 | 1997-08-12 | International Business Machines Corporation | Clock distribution network for reducing clock skew |
US5614845A (en) * | 1995-09-08 | 1997-03-25 | International Business Machines Corporation | Independent clock edge regulation |
US5668761A (en) * | 1995-09-08 | 1997-09-16 | International Business Machines Corporation | Fast read domino SRAM |
US5623450A (en) * | 1995-09-08 | 1997-04-22 | International Business Machines Corporation | Conditional recharge for dynamic logic |
US5729501A (en) * | 1995-09-08 | 1998-03-17 | International Business Machines Corporation | High Speed SRAM with or-gate sense |
US5610548A (en) * | 1995-09-08 | 1997-03-11 | International Business Machines Corporation | Split drive clock buffer |
US5828257A (en) * | 1995-09-08 | 1998-10-27 | International Business Machines Corporation | Precision time interval division with digital phase delay lines |
US5774005A (en) * | 1995-09-11 | 1998-06-30 | Advanced Micro Devices, Inc. | Latching methodology |
US5883529A (en) * | 1996-04-19 | 1999-03-16 | Sony Corporation | Function clock generation circuit and D-type flip-flop equipped with enable function and memory circuit using same |
US5886540A (en) * | 1996-05-31 | 1999-03-23 | Hewlett-Packard Company | Evaluation phase expansion for dynamic logic circuits |
US5999029A (en) * | 1996-06-28 | 1999-12-07 | Lsi Logic Corporation | Meta-hardened flip-flop |
US5796282A (en) * | 1996-08-12 | 1998-08-18 | Intel Corporation | Latching mechanism for pulsed domino logic with inherent race margin and time borrowing |
US5920218A (en) * | 1996-09-19 | 1999-07-06 | Sun Microsystems, Inc | Single-phase edge-triggered dual-rail dynamic flip-flop |
US6121807A (en) * | 1996-09-19 | 2000-09-19 | Sun Microsystems, Inc. | Single phase edge-triggered dual-rail dynamic flip-flop |
US5815687A (en) * | 1996-09-19 | 1998-09-29 | International Business Machines Corporation | Apparatus and method for simulating domino logic circuits using a special machine cycle to validate pre-charge |
US5859547A (en) * | 1996-12-20 | 1999-01-12 | Translogic Technology, Inc. | Dynamic logic circuit |
US6184718B1 (en) | 1996-12-20 | 2001-02-06 | Translogic Technology, Inc. | Dynamic logic circuit |
US6026473A (en) * | 1996-12-23 | 2000-02-15 | Intel Corporation | Method and apparatus for storing data in a sequentially written memory using an interleaving mechanism |
US5880608A (en) * | 1996-12-27 | 1999-03-09 | Intel Corporation | Pulsed domino latches |
WO1998029949A1 (en) * | 1996-12-27 | 1998-07-09 | Intel Corporation | Single-phase domino time borrowing logic with clocks at first and last stages and latch at last stage |
US5821775A (en) * | 1996-12-27 | 1998-10-13 | Intel Corporation | Method and apparatus to interface monotonic and non-monotonic domino logic |
US5896046A (en) * | 1997-01-27 | 1999-04-20 | International Business Machines Corporation | Latch structure for ripple domino logic |
US5933038A (en) * | 1997-02-25 | 1999-08-03 | Sun Microsystems, Inc. | Flip-flop with logic function incorporated therein with minimal time penalty |
US6043696A (en) * | 1997-05-06 | 2000-03-28 | Klass; Edgardo F. | Method for implementing a single phase edge-triggered dual-rail dynamic flip-flop |
US6040716A (en) * | 1997-05-19 | 2000-03-21 | Texas Instruments Incorporated | Domino logic circuits, systems, and methods with precharge control based on completion of evaluation by the subsequent domino logic stage |
EP0880231A1 (en) * | 1997-05-19 | 1998-11-25 | Texas Instruments Incorporated | Domino logic circuits |
US6046606A (en) * | 1998-01-21 | 2000-04-04 | International Business Machines Corporation | Soft error protected dynamic circuit |
US6037804A (en) * | 1998-03-27 | 2000-03-14 | International Business Machines Corporation | Reduced power dynamic logic circuit that inhibits reevaluation of stable inputs |
US6300801B1 (en) * | 1998-09-28 | 2001-10-09 | Hyundai Electronics Industries Co., Ltd. | Or gate circuit and state machine using the same |
US6154045A (en) * | 1998-12-22 | 2000-11-28 | Intel Corporation | Method and apparatus for reducing signal transmission delay using skewed gates |
EP1028434A1 (en) * | 1999-02-11 | 2000-08-16 | Infineon Technologies North America Corp. | Dynamic logic circuit |
US6262615B1 (en) | 1999-02-25 | 2001-07-17 | Infineon Technologies Ag | Dynamic logic circuit |
US6323688B1 (en) * | 1999-03-08 | 2001-11-27 | Elbrus International Limited | Efficient half-cycle clocking scheme for self-reset circuit |
US6140855A (en) * | 1999-03-30 | 2000-10-31 | International Business Machines Corporation | Dynamic-latch-receiver with self-reset pointer |
US6316960B2 (en) | 1999-04-06 | 2001-11-13 | Intel Corporation | Domino logic circuit and method |
US6271684B1 (en) | 1999-04-08 | 2001-08-07 | Intel Corporation | Method and apparatus for stalling OTB domino circuits |
US6265899B1 (en) | 1999-06-04 | 2001-07-24 | S3 Incorporated | Single rail domino logic for four-phase clocking scheme |
US6556962B1 (en) | 1999-07-02 | 2003-04-29 | Intel Corporation | Method for reducing network costs and its application to domino circuits |
US6529861B1 (en) | 1999-07-02 | 2003-03-04 | Intel Corporation | Power consumption reduction for domino circuits |
US6201415B1 (en) | 1999-08-05 | 2001-03-13 | Intel Corporation | Latched time borrowing domino circuit |
US6339353B1 (en) * | 1999-09-20 | 2002-01-15 | Fujitsu Limited | Input circuit of a memory having a lower current dissipation |
US6529045B2 (en) | 1999-09-28 | 2003-03-04 | Intel Corporation | NMOS precharge domino logic |
US6737888B1 (en) * | 1999-11-08 | 2004-05-18 | International Business Machines Corporation | Method for skipping a latch in timing-sensitive dynamic circuits of a multi-clocked system with unspecific underlap requirement |
US6281710B1 (en) * | 1999-12-17 | 2001-08-28 | Hewlett-Packard Company | Selective latch for a domino logic gate |
US6265897B1 (en) * | 1999-12-17 | 2001-07-24 | Hewlett-Packard Company | Contention based logic gate driving a latch and driven by pulsed clock |
US6275071B1 (en) | 1999-12-29 | 2001-08-14 | Intel Corporation | Domino logic circuit and method |
US6392466B1 (en) | 1999-12-30 | 2002-05-21 | Intel Corporation | Apparatus, method and system for a controllable pulse clock delay arrangement to control functional race margins in a logic data path |
US6329857B1 (en) | 1999-12-30 | 2001-12-11 | Intel Corporation | Apparatus, method and system for a logic arrangement having mutually exclusive outputs controlled by buffering cross-coupled devices |
US6448818B1 (en) | 1999-12-30 | 2002-09-10 | Intel Corporation | Apparatus, method and system for a ratioed NOR logic arrangement |
US6323698B1 (en) | 1999-12-30 | 2001-11-27 | Intel Corporation | Apparatus, method and system for providing LVS enables together with LVS data |
US20050189967A1 (en) * | 1999-12-30 | 2005-09-01 | Eitan Rosen | Generalized pre-charge clock circuit for pulsed domino gates |
US6968475B2 (en) * | 1999-12-30 | 2005-11-22 | Intel Corporation | Generalized pre-charge clock circuit for pulsed domino gates |
US6492837B1 (en) | 2000-03-17 | 2002-12-10 | Intel Corporation | Domino logic with output predischarge |
US6653866B2 (en) | 2000-03-17 | 2003-11-25 | Intel Corporation | Domino logic with output predischarge |
US6518793B2 (en) * | 2000-03-31 | 2003-02-11 | International Business Machines Corporation | Embedding of dynamic circuits in a static environment |
US6496038B1 (en) * | 2000-06-30 | 2002-12-17 | Intel Corporation | Pulsed circuit topology including a pulsed, domino flip-flop |
US6542006B1 (en) | 2000-06-30 | 2003-04-01 | Intel Corporation | Reset first latching mechanism for pulsed circuit topologies |
US6567337B1 (en) | 2000-06-30 | 2003-05-20 | Intel Corporation | Pulsed circuit topology to perform a memory array write operation |
US6531897B1 (en) | 2000-06-30 | 2003-03-11 | Intel Corporation | Global clock self-timed circuit with self-terminating precharge for high frequency applications |
US6346828B1 (en) | 2000-06-30 | 2002-02-12 | Intel Corporation | Method and apparatus for pulsed clock tri-state control |
US6801057B2 (en) * | 2000-08-18 | 2004-10-05 | Texas Instruments Incorporated | Silicon-on-insulator dynamic logic |
US6486706B2 (en) | 2000-12-06 | 2002-11-26 | Intel Corporation | Domino logic with low-threshold NMOS pull-up |
US6404234B1 (en) | 2001-05-09 | 2002-06-11 | Intel Corporation | Variable virtual ground domino logic with leakage control |
US6690604B2 (en) * | 2001-12-18 | 2004-02-10 | Intel Corporation | Register files and caches with digital sub-threshold leakage current calibration |
US20030112678A1 (en) * | 2001-12-18 | 2003-06-19 | Hsu Steven K. | Register files and caches with digital sub-threshold leakage current calibration |
US6677783B2 (en) * | 2001-12-31 | 2004-01-13 | Intel Corporation | High-speed, state-preserving, race-reducing, wide-pulsed-clock domino design style |
US6842046B2 (en) | 2002-01-31 | 2005-01-11 | Fujitsu Limited | Low-to-high voltage conversion method and system |
US7519850B2 (en) | 2002-06-25 | 2009-04-14 | Micron Technology, Inc. | Method and unit for buffer control |
US20030237010A1 (en) * | 2002-06-25 | 2003-12-25 | Micron Technology, Inc. | Method and unit for buffer control |
US7155630B2 (en) | 2002-06-25 | 2006-12-26 | Micron Technology, Inc. | Method and unit for selectively enabling an input buffer based on an indication of a clock transition |
US20060244491A1 (en) * | 2002-06-25 | 2006-11-02 | Micron Technology, Inc. | Method and unit for buffer control |
US7064584B2 (en) | 2003-04-28 | 2006-06-20 | Via Technologies, Inc. | P-domino output latch with accelerated evaluate path |
US20040257115A1 (en) * | 2003-04-28 | 2004-12-23 | Via Technologies, Inc. | N-domino output latch with accelerated evaluate path |
US20050248368A1 (en) * | 2003-04-28 | 2005-11-10 | Via Technologies, Inc. | P-domino output latch with accelerated evaluate path |
US7034578B2 (en) | 2003-04-28 | 2006-04-25 | Via Technologies, Inc. | N-domino output latch with accelerated evaluate path |
US6937079B1 (en) | 2003-07-28 | 2005-08-30 | University Of Louisiana At Lafayette | Single-transistor-clocked flip-flop |
US7667916B1 (en) | 2004-04-26 | 2010-02-23 | Marvell International Ltd. | Signal conversion system and method |
US7929241B1 (en) | 2004-04-26 | 2011-04-19 | Marvell International Ltd. | Signal conversion system and method |
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US20060220678A1 (en) * | 2005-03-31 | 2006-10-05 | Transmeta Corporation | Method and system for elastic signal pipelining |
US7724027B2 (en) | 2005-03-31 | 2010-05-25 | Rozas Guillermo J | Method and system for elastic signal pipelining |
US7256619B1 (en) * | 2005-04-04 | 2007-08-14 | Sun Microsystems, Inc. | Apparatus to shift to pre-charge mode a dynamic circuit driven by one-shot clock signal during power off mode |
US20070008012A1 (en) * | 2005-06-30 | 2007-01-11 | Masleid Robert P | Scannable dynamic circuit latch |
US7663408B2 (en) | 2005-06-30 | 2010-02-16 | Robert Paul Masleid | Scannable dynamic circuit latch |
US20070013425A1 (en) * | 2005-06-30 | 2007-01-18 | Burr James B | Lower minimum retention voltage storage elements |
US7737749B1 (en) * | 2005-07-06 | 2010-06-15 | Robert Paul Masleid | Elastic pipeline latch with a safe mode |
US20090212815A1 (en) * | 2006-06-30 | 2009-08-27 | Scott Pitkethly | Triple latch flip flop system and method |
US7495466B1 (en) | 2006-06-30 | 2009-02-24 | Transmeta Corporation | Triple latch flip flop system and method |
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US11569801B2 (en) | 2021-03-11 | 2023-01-31 | Qualcomm Incorporated | Analog-to-digital converter, phase sampler, time-to-digital converter, and flip-flop |
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