TW291586B - - Google Patents

Info

Publication number
TW291586B
TW291586B TW084109295A TW84109295A TW291586B TW 291586 B TW291586 B TW 291586B TW 084109295 A TW084109295 A TW 084109295A TW 84109295 A TW84109295 A TW 84109295A TW 291586 B TW291586 B TW 291586B
Authority
TW
Taiwan
Application number
TW084109295A
Other languages
Chinese (zh)
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of TW291586B publication Critical patent/TW291586B/zh

Links

Classifications

    • H10W20/076—
    • H10W20/077—
    • H10W20/098—
    • H10W20/43—
    • H10W20/48—
    • H10W20/495—
TW084109295A 1994-05-27 1995-09-06 TW291586B (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US25014294A 1994-05-27 1994-05-27

Publications (1)

Publication Number Publication Date
TW291586B true TW291586B (enExample) 1996-11-21

Family

ID=22946465

Family Applications (1)

Application Number Title Priority Date Filing Date
TW084109295A TW291586B (enExample) 1994-05-27 1995-09-06

Country Status (6)

Country Link
US (3) US5751066A (enExample)
EP (1) EP0689246B1 (enExample)
JP (1) JPH0864598A (enExample)
KR (1) KR950034755A (enExample)
DE (1) DE69531571T2 (enExample)
TW (1) TW291586B (enExample)

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0701277B1 (en) * 1994-05-27 2008-02-27 Texas Instruments Incorporated Interconnection method using a porous insulator for line to line capacitance reduction
JPH0855913A (ja) * 1994-06-07 1996-02-27 Texas Instr Inc <Ti> サブミクロン相互接続の選択的空隙充填方法
TWI228625B (en) * 1995-11-17 2005-03-01 Semiconductor Energy Lab Display device
JP3159093B2 (ja) 1996-12-25 2001-04-23 日本電気株式会社 半導体装置およびその製造方法
JP2910713B2 (ja) * 1996-12-25 1999-06-23 日本電気株式会社 半導体装置の製造方法
US5960316A (en) * 1997-03-31 1999-09-28 Intel Corporation Method to fabricate unlanded vias with a low dielectric constant material as an intraline dielectric
US6010957A (en) * 1997-06-25 2000-01-04 Advanced Micro Devices Semiconductor device having tapered conductive lines and fabrication thereof
JPH1140665A (ja) * 1997-07-18 1999-02-12 Nec Corp 半導体集積回路およびその製造方法
US6048803A (en) * 1997-08-19 2000-04-11 Advanced Microdevices, Inc. Method of fabricating a semiconductor device having fluorine bearing oxide between conductive lines
US5977635A (en) * 1997-09-29 1999-11-02 Siemens Aktiengesellschaft Multi-level conductive structure including low capacitance material
US6117763A (en) * 1997-09-29 2000-09-12 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor device with a low permittivity dielectric layer and contamination due to exposure to water
TW337608B (en) * 1997-10-29 1998-08-01 United Microelectronics Corp Process for producing unlanded via
US5990558A (en) * 1997-12-18 1999-11-23 Advanced Micro Devices, Inc. Reduced cracking in gap filling dielectrics
US5994221A (en) * 1998-01-30 1999-11-30 Lucent Technologies Inc. Method of fabricating aluminum-indium (or thallium) vias for ULSI metallization and interconnects
US6614097B1 (en) 1998-09-30 2003-09-02 Lsi Logic Corporation Method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device
US6037668A (en) * 1998-11-13 2000-03-14 Motorola, Inc. Integrated circuit having a support structure
US6777320B1 (en) * 1998-11-13 2004-08-17 Intel Corporation In-plane on-chip decoupling capacitors and method for making same
US6090724A (en) * 1998-12-15 2000-07-18 Lsi Logic Corporation Method for composing a thermally conductive thin film having a low dielectric property
US6181011B1 (en) * 1998-12-29 2001-01-30 Kawasaki Steel Corporation Method of controlling critical dimension of features in integrated circuits (ICS), ICS formed by the method, and systems utilizing same
US6071805A (en) * 1999-01-25 2000-06-06 Chartered Semiconductor Manufacturing, Ltd. Air gap formation for high speed IC processing
US6469390B2 (en) 1999-01-26 2002-10-22 Agere Systems Guardian Corp. Device comprising thermally stable, low dielectric constant material
US6486051B1 (en) * 1999-03-17 2002-11-26 Intel Corporation Method for relieving bond stress in an under-bond-pad resistor
FR2803093B1 (fr) * 1999-12-24 2002-11-29 St Microelectronics Sa Procede de realisation d'interconnexions metalliques isolees dans des circuits integres
FR2803092B1 (fr) * 1999-12-24 2002-11-29 St Microelectronics Sa Procede de realisation d'interconnexions metalliques isolees dans des circuits integres
US6313538B1 (en) * 2000-01-21 2001-11-06 Advanced Micro Devices, Inc. Semiconductor device with partial passivation layer
US6303456B1 (en) 2000-02-25 2001-10-16 International Business Machines Corporation Method for making a finger capacitor with tuneable dielectric constant
US6166420A (en) * 2000-03-16 2000-12-26 International Business Machines Corporation Method and structure of high and low K buried oxide for SoI technology
US6335261B1 (en) 2000-05-31 2002-01-01 International Business Machines Corporation Directional CVD process with optimized etchback
DE10059935A1 (de) * 2000-11-28 2002-06-06 Infineon Technologies Ag Dicht gepackte Halbleiterstruktur und Verfahren zum Herstellen einer solchen
US6358845B1 (en) * 2001-03-16 2002-03-19 Taiwan Semiconductor Manufacturing Company Method for forming inter metal dielectric
JP3834589B2 (ja) * 2001-06-27 2006-10-18 株式会社ルネサステクノロジ 半導体装置の製造方法
US7067440B1 (en) 2001-08-24 2006-06-27 Novellus Systems, Inc. Gap fill for high aspect ratio structures
US6794290B1 (en) 2001-12-03 2004-09-21 Novellus Systems, Inc. Method of chemical modification of structure topography
US7042092B1 (en) * 2001-12-05 2006-05-09 National Semiconductor Corporation Multilevel metal interconnect and method of forming the interconnect with capacitive structures that adjust the capacitance of the interconnect
JP3775354B2 (ja) * 2002-06-20 2006-05-17 松下電器産業株式会社 半導体装置およびその製造方法
US7122485B1 (en) 2002-12-09 2006-10-17 Novellus Systems, Inc. Deposition profile modification through process chemistry
JP3802002B2 (ja) * 2003-03-27 2006-07-26 三星電子株式会社 半導体装置の製造方法
US20040248400A1 (en) * 2003-06-09 2004-12-09 Kim Sun-Oo Composite low-k dielectric structure
US7078312B1 (en) 2003-09-02 2006-07-18 Novellus Systems, Inc. Method for controlling etch process repeatability
US7163896B1 (en) 2003-12-10 2007-01-16 Novellus Systems, Inc. Biased H2 etch process in deposition-etch-deposition gap fill
US7344996B1 (en) 2005-06-22 2008-03-18 Novellus Systems, Inc. Helium-based etch process in deposition-etch-deposition gap fill
US7476621B1 (en) 2003-12-10 2009-01-13 Novellus Systems, Inc. Halogen-free noble gas assisted H2 plasma etch process in deposition-etch-deposition gap fill
US7217658B1 (en) 2004-09-07 2007-05-15 Novellus Systems, Inc. Process modulation to prevent structure erosion during gap fill
US7176039B1 (en) 2004-09-21 2007-02-13 Novellus Systems, Inc. Dynamic modification of gap fill process characteristics
US7381451B1 (en) 2004-11-17 2008-06-03 Novellus Systems, Inc. Strain engineering—HDP thin film with tensile stress for FEOL and other applications
US7211525B1 (en) 2005-03-16 2007-05-01 Novellus Systems, Inc. Hydrogen treatment enhanced gap fill
US7880268B2 (en) * 2006-05-12 2011-02-01 Stmicroelectronics S.A. MIM capacitor
US7482245B1 (en) 2006-06-20 2009-01-27 Novellus Systems, Inc. Stress profile modulation in STI gap fill
CN101971360A (zh) * 2008-02-08 2011-02-09 清洁电池国际股份有限公司 用于发电的基于纳米棒的复合结构
US8133797B2 (en) * 2008-05-16 2012-03-13 Novellus Systems, Inc. Protective layer to enable damage free gap fill
US20110089402A1 (en) * 2009-04-10 2011-04-21 Pengfei Qi Composite Nanorod-Based Structures for Generating Electricity
JP5696679B2 (ja) * 2012-03-23 2015-04-08 富士通株式会社 半導体装置
US9449871B1 (en) * 2015-11-18 2016-09-20 International Business Machines Corporation Hybrid airgap structure with oxide liner

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4442137A (en) * 1982-03-18 1984-04-10 International Business Machines Corporation Maskless coating of metallurgical features of a dielectric substrate
US4584079A (en) * 1983-10-11 1986-04-22 Honeywell Inc. Step shape tailoring by phase angle variation RF bias sputtering
DE3637513A1 (de) * 1986-11-04 1988-05-11 Semikron Elektronik Gmbh Verfahren zum herstellen feinstrukturierter kontaktelektroden von leistungs-halbleiterbauelementen
JPS63179548A (ja) * 1987-01-21 1988-07-23 Mitsubishi Electric Corp 半導体集積回路装置の配線構造
SE8704588D0 (sv) * 1987-06-17 1987-11-20 Bioboat Ab Contamination removal process
JPH01235254A (ja) * 1988-03-15 1989-09-20 Nec Corp 半導体装置及びその製造方法
US4986878A (en) * 1988-07-19 1991-01-22 Cypress Semiconductor Corp. Process for improved planarization of the passivation layers for semiconductor devices
JPH0289346A (ja) * 1988-09-27 1990-03-29 Toshiba Corp 半導体装置及びその製造方法
JPH0793354B2 (ja) * 1988-11-28 1995-10-09 株式会社東芝 半導体装置の製造方法
US4987101A (en) * 1988-12-16 1991-01-22 International Business Machines Corporation Method for providing improved insulation in VLSI and ULSI circuits
JPH0316223A (ja) * 1989-06-14 1991-01-24 Matsushita Electron Corp 半導体装置の製造方法
US5013691A (en) * 1989-07-31 1991-05-07 At&T Bell Laboratories Anisotropic deposition of silicon dioxide
US5166101A (en) * 1989-09-28 1992-11-24 Applied Materials, Inc. Method for forming a boron phosphorus silicate glass composite layer on a semiconductor wafer
JPH04174541A (ja) * 1990-03-28 1992-06-22 Nec Corp 半導体集積回路及びその製造方法
KR950002948B1 (ko) * 1991-10-10 1995-03-28 삼성전자 주식회사 반도체 장치의 금속층간 절연막 형성방법
JP2825112B2 (ja) * 1992-04-22 1998-11-18 日本電気株式会社 半導体装置
US5441915A (en) * 1992-09-01 1995-08-15 Taiwan Semiconductor Manufacturing Company Ltd. Process of fabrication planarized metallurgy structure for a semiconductor device
US5272117A (en) * 1992-12-07 1993-12-21 Motorola, Inc. Method for planarizing a layer of material
US5278103A (en) * 1993-02-26 1994-01-11 Lsi Logic Corporation Method for the controlled formation of voids in doped glass dielectric films
US5356513A (en) * 1993-04-22 1994-10-18 International Business Machines Corporation Polishstop planarization method and structure
JP2973799B2 (ja) * 1993-04-23 1999-11-08 富士電機株式会社 パワートランジスタモジュール
US5324683A (en) * 1993-06-02 1994-06-28 Motorola, Inc. Method of forming a semiconductor structure having an air region

Also Published As

Publication number Publication date
DE69531571D1 (de) 2003-10-02
US5751066A (en) 1998-05-12
KR950034755A (enExample) 1995-12-28
US5728628A (en) 1998-03-17
DE69531571T2 (de) 2004-04-08
EP0689246A1 (en) 1995-12-27
EP0689246B1 (en) 2003-08-27
JPH0864598A (ja) 1996-03-08
US5789818A (en) 1998-08-04

Similar Documents

Publication Publication Date Title
TW291586B (enExample)
BR9508234A (enExample)
BRPI9507160A (enExample)
TW268975B (enExample)
EP0666470A3 (enExample)
FR2725040B1 (enExample)
TW272160B (enExample)
TW275120B (enExample)
EP0667627A3 (enExample)
FR2728175B3 (enExample)
AR255595A1 (enExample)
FR2728825B1 (enExample)
IN190173B (enExample)
IN189499B (enExample)
IN179286B (enExample)
IN184117B (enExample)
IN178618B (enExample)
IN182195B (enExample)
CN3022750S (enExample)
EP0664137A3 (enExample)
CN3025747S (enExample)
CN3024054S (enExample)
CN3023738S (enExample)
CN3023289S (enExample)
EP0709830A3 (enExample)

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees