DE69531571D1 - Verbesserungen in Bezug auf Halbleitervorrichtungen - Google Patents

Verbesserungen in Bezug auf Halbleitervorrichtungen

Info

Publication number
DE69531571D1
DE69531571D1 DE69531571T DE69531571T DE69531571D1 DE 69531571 D1 DE69531571 D1 DE 69531571D1 DE 69531571 T DE69531571 T DE 69531571T DE 69531571 T DE69531571 T DE 69531571T DE 69531571 D1 DE69531571 D1 DE 69531571D1
Authority
DE
Germany
Prior art keywords
semiconductor devices
semiconductor
devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69531571T
Other languages
English (en)
Other versions
DE69531571T2 (de
Inventor
Robert H Havemann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69531571D1 publication Critical patent/DE69531571D1/de
Publication of DE69531571T2 publication Critical patent/DE69531571T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
DE69531571T 1994-05-27 1995-05-26 Verbesserungen in Bezug auf Halbleitervorrichtungen Expired - Lifetime DE69531571T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US25014294A 1994-05-27 1994-05-27
US250142 1994-05-27

Publications (2)

Publication Number Publication Date
DE69531571D1 true DE69531571D1 (de) 2003-10-02
DE69531571T2 DE69531571T2 (de) 2004-04-08

Family

ID=22946465

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69531571T Expired - Lifetime DE69531571T2 (de) 1994-05-27 1995-05-26 Verbesserungen in Bezug auf Halbleitervorrichtungen

Country Status (6)

Country Link
US (3) US5751066A (de)
EP (1) EP0689246B1 (de)
JP (1) JPH0864598A (de)
KR (1) KR950034755A (de)
DE (1) DE69531571T2 (de)
TW (1) TW291586B (de)

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US5990558A (en) * 1997-12-18 1999-11-23 Advanced Micro Devices, Inc. Reduced cracking in gap filling dielectrics
US5994221A (en) * 1998-01-30 1999-11-30 Lucent Technologies Inc. Method of fabricating aluminum-indium (or thallium) vias for ULSI metallization and interconnects
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US6777320B1 (en) * 1998-11-13 2004-08-17 Intel Corporation In-plane on-chip decoupling capacitors and method for making same
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US6469390B2 (en) 1999-01-26 2002-10-22 Agere Systems Guardian Corp. Device comprising thermally stable, low dielectric constant material
US6486051B1 (en) * 1999-03-17 2002-11-26 Intel Corporation Method for relieving bond stress in an under-bond-pad resistor
FR2803092B1 (fr) * 1999-12-24 2002-11-29 St Microelectronics Sa Procede de realisation d'interconnexions metalliques isolees dans des circuits integres
FR2803093B1 (fr) * 1999-12-24 2002-11-29 St Microelectronics Sa Procede de realisation d'interconnexions metalliques isolees dans des circuits integres
US6313538B1 (en) * 2000-01-21 2001-11-06 Advanced Micro Devices, Inc. Semiconductor device with partial passivation layer
US6303456B1 (en) 2000-02-25 2001-10-16 International Business Machines Corporation Method for making a finger capacitor with tuneable dielectric constant
US6166420A (en) * 2000-03-16 2000-12-26 International Business Machines Corporation Method and structure of high and low K buried oxide for SoI technology
US6335261B1 (en) 2000-05-31 2002-01-01 International Business Machines Corporation Directional CVD process with optimized etchback
DE10059935A1 (de) * 2000-11-28 2002-06-06 Infineon Technologies Ag Dicht gepackte Halbleiterstruktur und Verfahren zum Herstellen einer solchen
US6358845B1 (en) * 2001-03-16 2002-03-19 Taiwan Semiconductor Manufacturing Company Method for forming inter metal dielectric
JP3834589B2 (ja) * 2001-06-27 2006-10-18 株式会社ルネサステクノロジ 半導体装置の製造方法
US7067440B1 (en) 2001-08-24 2006-06-27 Novellus Systems, Inc. Gap fill for high aspect ratio structures
US6794290B1 (en) 2001-12-03 2004-09-21 Novellus Systems, Inc. Method of chemical modification of structure topography
US7042092B1 (en) * 2001-12-05 2006-05-09 National Semiconductor Corporation Multilevel metal interconnect and method of forming the interconnect with capacitive structures that adjust the capacitance of the interconnect
JP3775354B2 (ja) * 2002-06-20 2006-05-17 松下電器産業株式会社 半導体装置およびその製造方法
US7122485B1 (en) 2002-12-09 2006-10-17 Novellus Systems, Inc. Deposition profile modification through process chemistry
JP3802002B2 (ja) * 2003-03-27 2006-07-26 三星電子株式会社 半導体装置の製造方法
US20040248400A1 (en) * 2003-06-09 2004-12-09 Kim Sun-Oo Composite low-k dielectric structure
US7078312B1 (en) 2003-09-02 2006-07-18 Novellus Systems, Inc. Method for controlling etch process repeatability
US7344996B1 (en) 2005-06-22 2008-03-18 Novellus Systems, Inc. Helium-based etch process in deposition-etch-deposition gap fill
US7163896B1 (en) 2003-12-10 2007-01-16 Novellus Systems, Inc. Biased H2 etch process in deposition-etch-deposition gap fill
US7476621B1 (en) 2003-12-10 2009-01-13 Novellus Systems, Inc. Halogen-free noble gas assisted H2 plasma etch process in deposition-etch-deposition gap fill
US7217658B1 (en) 2004-09-07 2007-05-15 Novellus Systems, Inc. Process modulation to prevent structure erosion during gap fill
US7176039B1 (en) 2004-09-21 2007-02-13 Novellus Systems, Inc. Dynamic modification of gap fill process characteristics
US7381451B1 (en) 2004-11-17 2008-06-03 Novellus Systems, Inc. Strain engineering—HDP thin film with tensile stress for FEOL and other applications
US7211525B1 (en) 2005-03-16 2007-05-01 Novellus Systems, Inc. Hydrogen treatment enhanced gap fill
US7880268B2 (en) * 2006-05-12 2011-02-01 Stmicroelectronics S.A. MIM capacitor
US7482245B1 (en) 2006-06-20 2009-01-27 Novellus Systems, Inc. Stress profile modulation in STI gap fill
WO2009100458A2 (en) * 2008-02-08 2009-08-13 Clean Cell International Inc. Composite nanorod-based structures for generating electricity
US8133797B2 (en) * 2008-05-16 2012-03-13 Novellus Systems, Inc. Protective layer to enable damage free gap fill
US20110089402A1 (en) * 2009-04-10 2011-04-21 Pengfei Qi Composite Nanorod-Based Structures for Generating Electricity
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US9449871B1 (en) * 2015-11-18 2016-09-20 International Business Machines Corporation Hybrid airgap structure with oxide liner

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Also Published As

Publication number Publication date
DE69531571T2 (de) 2004-04-08
US5728628A (en) 1998-03-17
EP0689246A1 (de) 1995-12-27
US5789818A (en) 1998-08-04
TW291586B (de) 1996-11-21
EP0689246B1 (de) 2003-08-27
KR950034755A (de) 1995-12-28
US5751066A (en) 1998-05-12
JPH0864598A (ja) 1996-03-08

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