TW205112B - - Google Patents

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Publication number
TW205112B
TW205112B TW081107561A TW81107561A TW205112B TW 205112 B TW205112 B TW 205112B TW 081107561 A TW081107561 A TW 081107561A TW 81107561 A TW81107561 A TW 81107561A TW 205112 B TW205112 B TW 205112B
Authority
TW
Taiwan
Prior art keywords
film
field
area
insulating film
semiconductor substrate
Prior art date
Application number
TW081107561A
Other languages
English (en)
Chinese (zh)
Original Assignee
Hitachi Seisakusyo Kk
Hitachi Cho Lsi Eng Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Seisakusyo Kk, Hitachi Cho Lsi Eng Co Ltd filed Critical Hitachi Seisakusyo Kk
Application granted granted Critical
Publication of TW205112B publication Critical patent/TW205112B/zh

Links

Classifications

    • H10P14/60—
    • H10W10/17—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10W10/0148—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell

Landscapes

  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
TW081107561A 1991-10-01 1992-09-24 TW205112B (Direct)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25347291 1991-10-01

Publications (1)

Publication Number Publication Date
TW205112B true TW205112B (Direct) 1993-05-01

Family

ID=17251862

Family Applications (1)

Application Number Title Priority Date Filing Date
TW081107561A TW205112B (Direct) 1991-10-01 1992-09-24

Country Status (5)

Country Link
US (1) US5455438A (Direct)
EP (1) EP0560985A1 (Direct)
KR (1) KR100253696B1 (Direct)
TW (1) TW205112B (Direct)
WO (1) WO1993007641A1 (Direct)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08111462A (ja) * 1994-10-12 1996-04-30 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法
US5815433A (en) * 1994-12-27 1998-09-29 Nkk Corporation Mask ROM device with gate insulation film based in pad oxide film and/or nitride film
JPH08316223A (ja) * 1995-05-16 1996-11-29 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5576573A (en) * 1995-05-31 1996-11-19 United Microelectronics Corporation Stacked CVD oxide architecture multi-state memory cell for mask read-only memories
US5680345A (en) * 1995-06-06 1997-10-21 Advanced Micro Devices, Inc. Nonvolatile memory cell with vertical gate overlap and zero birds beaks
KR100214068B1 (ko) * 1995-11-21 1999-08-02 김영환 반도체 장치의 소자분리막 형성방법
KR100214469B1 (ko) * 1995-12-29 1999-08-02 구본준 반도체소자의 격리막 형성방법
KR100232197B1 (ko) * 1996-12-26 1999-12-01 김영환 반도체 소자의 제조 방법
KR19980057003A (ko) * 1996-12-30 1998-09-25 김영환 반도체 메모리 디바이스 및 그 제조방법
JPH10233392A (ja) * 1997-02-20 1998-09-02 Mitsubishi Electric Corp 半導体装置の製造方法
US5858830A (en) * 1997-06-12 1999-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making dual isolation regions for logic and embedded memory devices
KR19990008496A (ko) * 1997-07-01 1999-02-05 윤종용 복합 반도체 장치의 비대칭 게이트 산화막 제조 방법
JP3583583B2 (ja) * 1997-07-08 2004-11-04 株式会社東芝 半導体装置及びその製造方法
JPH11145397A (ja) * 1997-11-11 1999-05-28 Mitsubishi Electric Corp 半導体集積回路装置
US6440819B1 (en) 1998-03-03 2002-08-27 Advanced Micro Devices, Inc. Method for differential trenching in conjunction with differential fieldox growth
JP4030198B2 (ja) * 1998-08-11 2008-01-09 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6674134B2 (en) * 1998-10-15 2004-01-06 International Business Machines Corporation Structure and method for dual gate oxidation for CMOS technology
JP3733252B2 (ja) * 1998-11-02 2006-01-11 セイコーエプソン株式会社 半導体記憶装置及びその製造方法
JP2001068564A (ja) * 1999-08-30 2001-03-16 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2001203347A (ja) 2000-01-18 2001-07-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP4592193B2 (ja) * 2001-02-06 2010-12-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4738840B2 (ja) * 2004-03-16 2011-08-03 キヤノン株式会社 電子写真感光体
KR100591184B1 (ko) * 2004-12-30 2006-06-19 동부일렉트로닉스 주식회사 듀얼 버즈 비크 로코스 소자 분리 형성 방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6379371A (ja) * 1986-09-24 1988-04-09 Hitachi Vlsi Eng Corp 半導体集積回路装置の製造方法
JPS63140567A (ja) * 1986-12-01 1988-06-13 Mitsubishi Electric Corp 半導体記憶装置
US5196910A (en) * 1987-04-24 1993-03-23 Hitachi, Ltd. Semiconductor memory device with recessed array region
JPS6411343A (en) * 1987-07-03 1989-01-13 Matsushita Electric Industrial Co Ltd Manufacture of semiconductor device
JPH0237158A (ja) * 1988-07-27 1990-02-07 Walbro Far East Inc ダイヤフラム型気化器
JPH02303049A (ja) * 1989-05-17 1990-12-17 Toshiba Corp 半導体装置およびその製造方法
JPH0346345A (ja) * 1989-07-14 1991-02-27 Nec Kyushu Ltd 半導体装置
JP2512216B2 (ja) * 1989-08-01 1996-07-03 松下電器産業株式会社 半導体装置の製造方法
JP2689004B2 (ja) * 1989-12-15 1997-12-10 三菱電機株式会社 半導体装置
US5057449A (en) * 1990-03-26 1991-10-15 Micron Technology, Inc. Process for creating two thicknesses of gate oxide within a dynamic random access memory
JPH1011343A (ja) * 1996-06-19 1998-01-16 Canon Inc 情報処理装置及び方法

Also Published As

Publication number Publication date
EP0560985A1 (en) 1993-09-22
KR100253696B1 (ko) 2000-04-15
EP0560985A4 (Direct) 1994-02-02
KR930702784A (ko) 1993-09-09
US5455438A (en) 1995-10-03
WO1993007641A1 (fr) 1993-04-15

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