TW202318452A - 陶瓷電子零件及其製造方法 - Google Patents
陶瓷電子零件及其製造方法 Download PDFInfo
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- TW202318452A TW202318452A TW111136144A TW111136144A TW202318452A TW 202318452 A TW202318452 A TW 202318452A TW 111136144 A TW111136144 A TW 111136144A TW 111136144 A TW111136144 A TW 111136144A TW 202318452 A TW202318452 A TW 202318452A
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Abstract
本發明提供一種可抑制內部電極層之連續率下降之陶瓷電子零件及其製造方法。
本發明之陶瓷電子零件之特徵在於，具備由介電層與以Ni為主相之內部電極層交替地積層而成之積層晶片，至少任一上述介電層於與相鄰之上述內部電極層之界面處具備包含Si之二次相，與具備上述二次相之上述介電層相鄰之上述內部電極層於上述界面中與上述二次相接觸之部位，具備包含Au、Pt、Cu、Fe、Cr、Zn及In中之任1種以上之添加元素之層。
Description
本發明係關於一種陶瓷電子零件及其製造方法。
積層陶瓷電容器係藉由以下方式製作，即，將以Ni粉末為主原料之金屬漿料印刷至以鈦酸鋇等介電材料為主原料之介電坯片上，並經積層、壓接、切割、脫黏、焙燒、外部電極塗佈等而製作。為了市場要求之積層陶瓷電容器之小型大容量化，與介電層之薄層化同樣地要求內部電極層之薄層化及高積層化。
於作為陶瓷之介電層與作為金屬之內部電極層之同時焙燒中，為了抑制如裂痕等內部缺陷，通常於介電層中，除導入作為主相之介電材料以外，亦導入包含作為燒結助劑之Si等之液相成分之二次相，以設計精細結構及電特性(例如參照專利文獻1)。
[先前技術文獻]
[專利文獻]
[專利文獻1]日本專利特開2014-123698號公報
[發明所欲解決之問題]
然而，內部電極層中與二次相接觸之部位容易因由液相燒結所導致之燒結促進效果而產生不連續化。
本發明係鑒於上述問題而成者，目的在於提供一種可抑制內部電極層之連續率下降之陶瓷電子零件及其製造方法。
[解決問題之技術手段]
本發明之陶瓷電子零件之特徵在於，具備由介電層與以Ni為主相之內部電極層交替地積層而成之積層晶片，至少任一上述介電層於與相鄰之上述內部電極層之界面處具備包含Si之二次相，與具備上述二次相之上述介電層相鄰之上述內部電極層於上述界面中與上述二次相接觸之部位，具備包含Au、Pt、Cu、Fe、Cr、Zn及In中之任1種以上之添加元素之層。
於上述陶瓷電子零件中，於與具備上述二次相之上述介電層相鄰之上述內部電極層中，上述添加元素之總量相對於Ni可為0.01 at%以上5 at%以下。
於上述陶瓷電子零件中，包含上述添加元素之層可為上述添加元素之單金屬、合金或氧化物。
於上述陶瓷電子零件中，上述介電層與上述內部電極層之積層方向上之(上述二次相之厚度/包含上述添加元素之層之厚度)可為0.1以上3以下。
於上述陶瓷電子零件中，上述介電層之厚度可為0.5 μm以下。
於上述陶瓷電子零件中，於在上述介電層與上述內部電極層之積層方向上進行STEM-EDS(scanning transmission electron microscopy-energy dispersive X-ray spectroscopy，掃描穿透式電子顯微鏡-能量分散型X射線分析)線分析之情形時，可於上述二次相中出現Si濃度之峰，並且於包含上述添加元素之層中出現上述添加元素之濃度之峰。
於上述陶瓷電子零件中，與具備上述二次相之上述介電層相鄰之上述內部電極層之厚度可為0.05 μm以上0.4 μm以下。
於上述陶瓷電子零件中，上述介電層可包含鈦酸鋇。
本發明之陶瓷電子零件之製造方法之特徵在於，包括如下步驟：藉由於含有包含SiO
2之燒結助劑之介電坯片上形成包含Au、Pt、Cu、Fe、Cr、Zn及In中之任1種以上之添加元素之Ni漿料之內部電極圖案而形成積層單元之步驟；藉由將複數個上述積層單元積層而形成積層體之步驟；及對上述積層體進行焙燒之步驟；調整上述焙燒步驟之條件，以使對上述介電坯片進行焙燒而獲得之介電層中之至少任一個於與對上述內部電極圖案進行焙燒而獲得之相鄰之內部電極層之界面處形成包含Si之二次相，並於上述相鄰之內部電極層中與上述二次相接觸之部位形成包含上述添加元素之層。
[發明之效果]
根據本發明，可提供一種可抑制內部電極層之連續率下降之陶瓷電子零件及其製造方法。
以下參照圖式說明實施方式。
(第1實施方式)
圖1係第1實施方式之積層陶瓷電容器100之部分剖視立體圖。圖2係圖1之A-A線剖視圖。圖3係圖1之B-B線剖視圖。如圖1～圖3所例示，積層陶瓷電容器100具備具有大致長方體形狀之積層晶片10、及設於積層晶片10之任一對向之兩端面之外部電極20a、20b。再者，積層晶片10之除該兩端面以外之四面中，將除積層方向之上表面及下表面以外之兩面稱為側面。外部電極20a、20b沿積層晶片10之積層方向之上表面、下表面及兩側面延伸。然而，外部電極20a、20b相互隔開。
積層晶片10具有包含作為介電體發揮功能之陶瓷材料之介電層11與以Ni為主相之內部電極層12交替地積層之構成。各內部電極層12之端緣交替地露出於積層晶片10之設有外部電極20a之端面及設有外部電極20b之端面。藉此，各內部電極層12與外部電極20a及外部電極20b交替地導通。其結果為，積層陶瓷電容器100具有複數個介電層11經由內部電極層12而積層之構成。又，於介電層11與內部電極層12之積層體中，於積層方向之最外層配置有內部電極層12，該積層體之上表面及下表面被覆蓋層13覆蓋。覆蓋層13以陶瓷材料為主成分。例如，覆蓋層13之材料之陶瓷材料之主成分可與介電層11相同。
積層陶瓷電容器100之尺寸例如為長0.25 mm、寬0.125 mm、高0.125 mm或長0.4 mm、寬0.2 mm、高0.2 mm或長0.6 mm、寬0.3 mm、高0.3 mm或長0.6 mm、寬0.3 mm、高0.110 mm或長1.0 mm、寬0.5 mm、高0.5 mm或長1.0 mm、寬0.5 mm、高0.1 mm或長3.2 mm、寬1.6 mm、高1.6 mm或長4.5 mm、寬3.2 mm、高2.5 mm，但不限於該等尺寸。
介電層11例如以具有通式ABO
3所表示之鈣鈦礦結構之陶瓷材料為主相。再者，該鈣鈦礦結構包含不符合化學計量組成之ABO
3-α。例如，作為該陶瓷材料，可選擇BaTiO
3(鈦酸鋇)、CaZrO
3(鋯酸鈣)、CaTiO
3(鈦酸鈣)、SrTiO
3(鈦酸鍶)、MgTiO
3(鈦酸鎂)、形成鈣鈦礦結構之Ba
1-x-yCa
xSr
yTi
1-zZr
zO
3(0≦x≦1、0≦y≦1、0≦z≦1)等中之至少1種使用。Ba
1-x-yCa
xSr
yTi
1-zZr
zO
3為鈦酸鋇鍶、鈦酸鋇鈣、鋯酸鋇、鋯鈦酸鋇、鋯鈦酸鋇鈣及鋯鈦酸鋇鈣等。
如圖2所例示，連接於外部電極20a之內部電極層12與連接於外部電極20b之內部電極層12對向之區域為積層陶瓷電容器100中產生電容之區域。對此，將該產生電容之區域稱為容量區域14。即，容量區域14為連接於不同外部電極之相鄰之內部電極層12彼此對向之區域。
將連接於外部電極20a之內部電極層12彼此不經由連接於外部電極20b之內部電極層12而對向之區域稱為端邊緣15。又，連接於外部電極20b之內部電極層12彼此不經由連接於外部電極20a之內部電極層12而對向之區域亦為端邊緣15。即，端邊緣15為連接於相同外部電極之內部電極層12不經由連接於不同外部電極之內部電極層12而對向之區域。端邊緣15為不產生電容之區域。
如圖3所例示，於積層晶片10中，將自積層晶片10之兩側面至內部電極層12為止之區域稱為側邊緣16。即，側邊緣16為以覆蓋上述積層結構中積層之複數個內部電極層12沿兩側面側延伸之端部之方式而設置之區域。側邊緣16亦為不產生電容之區域。
介電層11與內部電極層12之積層結構可藉由以下方式而獲得，即，對將於介電坯片上印刷有以Ni粉末為主原料之金屬漿料之積層單元積層複數個而成者進行焙燒。因此，作為陶瓷之介電層11與作為金屬之內部電極層12會被同時焙燒。為了抑制同時焙燒過程中容易產生之裂痕等內部缺陷，向介電坯片中添加包含Si之燒結助劑。燒結助劑於焙燒時成為液相，產生液相燒結，促進介電層11之主成分陶瓷之燒結。該液相於焙燒後成為二次相。
圖4係例示形成於介電層11之主相17及二次相18之圖。如圖4所例示，介電層11形成有主相17及二次相18。主相17為介電層11之主成分陶瓷之晶粒。二次相18形成於主相17之晶界、或介電層11與內部電極層12之界面。二次相18意指藉由對燒結助劑進行焙燒而生成於介電層11之相，例如以SiO
2或SiO
2及B
2O
3中之至少任一者為主成分。內部電極層12中與二次相18接觸之部位容易因由液相燒結所導致之燒結促進效果而產生不連續化，有引起連續率下降之虞。
圖5係表示連續率之圖。如圖5所例示，於某一內部電極層12中之長度L0之觀察區域中，可測定其金屬部分之長度L1、L2、……、Ln並相加，將金屬部分之比率ΣLn/L0定義為該層之連續率。
本實施方式之積層陶瓷電容器100具有抑制內部電極層12之連續率下降之結構。首先，如圖6所例示，至少任一介電層11於介電層11與內部電極層12之界面處具備二次相18。
內部電極層12於介電層11與內部電極層12之界面中與二次相18接觸之部位，具備包含Au、Pt、Cu、Fe、Cr、Zn及In中之任1種以上之添加元素之層19。層19係指出現於內部電極層12之表層之薄層，於沿積層方向進行STEM-EDS線分析之情形時，係指上述添加元素之濃度出現峰之層。層19可為Au、Pt、Cu、Fe、Cr、Zn及In中之任1種以上之添加元素之單金屬，可為合金，亦可為氧化物。藉由設置層19，界面處會產生釘紮效應，因此可抑制焙燒時與作為液相而存在之二次相18之接觸界面處之燒結促進效果，並可抑制內部電極層12之球化及不連續化，從而可抑制內部電極層12之連續率下降。再者，層19可覆蓋介電層11與內部電極層12之界面整體，亦可覆蓋該界面之至少一部分。
例如，由於Au、Pt及Cu相較於Ni之離子化能更高，因此包含Au、Pt及Cu中之至少任一者之層19會抑制伴隨燒結之原子擴散，亦會於與二次相18之接觸界面處抑制燒結促進效果。由於Fe、Cr、Zn及In會形成相較於Ni更穩定之氧化物或複合氧化物，因此包含Fe、Cr、Zn及In中之至少任一者之層19會阻礙金屬Ni溶解於二次相18中之反應，從而抑制燒結促進效果。
於內部電極層12中，若Au、Pt、Cu、Fe、Cr、Zn及In之總量較少，則有於與二次相18之接觸界面處無法充分抑制燒結促進效果之虞。因此，於內部電極層12中，較佳為對Au、Pt、Cu、Fe、Cr、Zn及In之總量設定下限。例如，於內部電極層12中，於將Ni設為100 at%之情形時，Au、Pt、Cu、Fe、Cr、Zn及In之總量較佳為0.01 at%以上，更佳為0.05 at%以上，更佳為0.1 at%以上。再者，Au、Pt、Cu、Fe、Cr、Zn及In中之未添加之金屬不算入總量。因此，於向內部電極層12中僅添加Au之情形時，Au、Pt、Cu、Fe、Cr、Zn及In之總量為Au之量。
另一方面，於內部電極層12中，若Au、Pt、Cu、Fe、Cr、Zn及In之總量較多，則有產生該等元素擴散至介電層11、內部電極層12氧化、無法忽視內部電極層12之燒結性之影響等不良情況之虞。因此，於內部電極層12中，較佳為對Au、Pt、Cu、Fe、Cr、Zn及In之總量設定上限。例如，於內部電極層12中，於將Ni設為100 at%之情形時，Au、Pt、Cu、Fe、Cr、Zn及In之總量較佳為5 at%以下，更佳為3 at%以下，更佳為1 at%以下。
每一層之介電層11之厚度為0.05 μm以上5 μm以下、或0.1 μm以上3 μm以下、或0.2 μm以上1 μm以下、或0.6 μm以下。此處，若介電層11較薄，則燒結時由介電層11產生之約束力下降，因此內部電極層12中容易發生球化。因此，於介電層11較薄之構成中，可顯著獲得本實施方式之抑制內部電極層12之連續率下降之效果。例如，於介電層11為0.5 μm以下之情形時，可顯著獲得本實施方式之效果。再者，介電層11之厚度可藉由以下方式測定，即，使用SEM(掃描型電子顯微鏡)觀察積層陶瓷電容器100之剖面，對不同之10層之介電層11分別測定各10個點之厚度，並導出所有測定點之平均值。
於內部電極層12較薄之構成中，可顯著獲得本實施方式之抑制內部電極層12之連續率下降之效果。例如，於每一層之內部電極層12之厚度為0.4 μm以下、0.6 μm以下或0.8 μm以下之情形時，可顯著獲得本實施方式之效果。另一方面，若內部電極層12過薄，則層19之厚度相對於內部電極層12之厚度之比率變高，有ESR(等效串聯電阻)增加、內部電極層12氧化、無法忽視內部電極層12之燒結性之影響之虞。因此，每一層之內部電極層12之厚度較佳為0.05 μm以上，更佳為0.1 μm以上，進而較佳為0.15 μm以上。再者，內部電極層12之厚度可藉由以下方式測定，即，使用SEM觀察積層陶瓷電容器100之剖面，對不同之10層之內部電極層12分別測定各10個點之厚度，並導出所有測定點之平均值。
若介電層11與內部電極層12之積層方向上之厚度比(二次相18之厚度/層19之厚度)較大，則有系統中之液相量會相對增加，導致難以維持界面處之釘紮作用之虞。因此，較佳為對該厚度比設置上限。例如，該厚度比較佳為3以下，更佳為2以下，進而較佳為1.5以下。另一方面，若該厚度比較小，則有介電層無法吸收伴隨更低溫下發生之內部電極層之燒結之收縮應力，從而產生裂痕之虞。因此，較佳為對該厚度比設置下限。例如，該厚度比較佳為0.1以上，更佳為0.3以上，進而較佳為0.5以上。
繼而說明積層陶瓷電容器100之製造方法。圖7係例示積層陶瓷電容器100之製造方法之流程之圖。
(原料粉末製作步驟)
首先，準備用以形成介電層11之介電材料。介電層11所包含之A位元素及B位元素通常以ABO
3之粒子之燒結體形態包含於介電層11中。例如，BaTiO
3係具有鈣鈦礦結構之正方晶化合物，其表現出高介電常數。該BaTiO
3一般可藉由使二氧化鈦等鈦原料與碳酸鋇等鋇原料反應而合成鈦酸鋇來獲得。作為介電層11之主成分陶瓷之合成方法，已知有先前多種方法，例如已知有固相法、溶膠-凝膠法、水熱法等。於本實施方式中，可採用該等任意一種方法。
向所獲得之陶瓷粉末中視目的添加特定之添加化合物。作為添加化合物，可例舉：鎂(Mg)、錳(Mn)、釩(V)、Cr、稀土類元素(Y、釤(Sm)、銪(Eu)、釓(Gd)、鋱(Tb)、鏑(Dy)、鈥(Ho)、鉺(Er)、銩(Tm)及鐿(Yb))之氧化物；包含Co(鈷)、Ni、鋰(Li)、硼(B)、鈉(Na)、鉀(K)或矽(Si)之氧化物；包含鈷、鎳、鋰、硼、鈉、鉀或矽之玻璃。其中，主要由SiO
2作為燒結助劑發揮功能。
例如，將陶瓷原料粉末中包含添加化合物之化合物進行濕式混合、乾燥及粉碎來製備陶瓷材料。例如，對於以上述方式獲得之陶瓷材料，可視需要進行粉碎處理來調整粒徑，或藉由與分級處理組合來調整粒徑。藉由以上步驟，可獲得介電材料。
(積層步驟)
繼而，向所獲得之介電材料中添加聚乙烯醇縮丁醛(PVB)樹脂等黏合劑、乙醇、甲苯等有機溶劑及塑化劑，並進行濕式混合。使用所獲得之漿料，例如藉由模嘴塗佈機法或刮刀法，於基材51上塗佈介電坯片52並使其乾燥。基材51例如為PET(聚對苯二甲酸乙二酯)膜。
繼而，如圖8(a)所例示，於介電坯片52上使內部電極圖案53成膜。於圖8(a)中，作為一例，可於介電坯片52上使4層內部電極圖案53隔開特定之間隔成膜。將成膜有內部電極圖案53之介電坯片52作為積層單元。
內部電極圖案53中使用Ni漿料。Ni漿料中包含Ni粉末、及Au、Pt、Cu、Fe、Cr、Zn及In中之至少1種以上之添加元素之有機金屬錯合物或細粉末。可使用添加元素與Ni之合金之粉末。亦可使用塗佈於添加元素之表面之Ni粉末。於將Ni設為100 at%之情形時，較佳為將添加元素之有效金屬濃度設為0.01 at%以上5 at%以下。又，成膜方法可為印刷、濺射、蒸鍍、鍍覆等。
繼而，如圖8(b)所例示，一面自基材51剝離介電坯片52，一面將積層單元進行積層。
繼而，將覆蓋片54僅按特定數量(例如2～10層)積層至藉由將積層單元進行積層而獲得之積層體之上下並進行熱壓接，將其切割為特定晶片尺寸(例如1.0 mm×0.5 mm)。於圖8(b)之例中，沿虛線進行切割。覆蓋片54可與介電坯片52為相同成分，亦可添加化合物不同。
(焙燒步驟)
將以此方式獲得之陶瓷積層體於N
2氛圍中進行脫黏處理後，利用浸漬法塗佈成為外部電極20a、20b之底層之金屬漿料，並於氧分壓為10
-5～10
-8atm之還原氛圍中在1100～1300℃下焙燒10分鐘～2小時。以此方式，可獲得積層陶瓷電容器100。
藉由調整焙燒溫度、升溫至焙燒溫度之升溫速度、焙燒步驟時之氛圍等焙燒條件，可形成層19。再者，於包含作為燒結助劑之SiO
2之液相成分與以Ni為主成分之內部電極材料接觸並表現出燒結促進效果前，使層19形成於內部電極層12之表層較重要。因此，於較作為燒結助劑之SiO
2熔解並開始產生液相之溫度區域更低溫之區域(作為一例，1000℃以下之溫度區域)中，設置以下焙燒曲線：將50℃/min以下之升溫速度區域設置為3分鐘以上，或設置1分鐘以上之溫度保持期(同一溫度下之保持期)。
(再氧化處理步驟)
隨後，可於N
2氣體氛圍中在600℃～1000℃下進行再氧化處理。
(鍍覆處理步驟)
隨後，可藉由鍍覆處理，於外部電極20a、20b上塗覆Cu、Ni、Sn等金屬。
再者，於上述各實施方式中，作為陶瓷電子零件之一例而說明了積層陶瓷電容器，但並不限於此。例如，亦可使用變阻器或熱敏電阻等其他電子零件。
[實施例]
以下，製作實施方式之積層陶瓷電容器，並對其特性進行調查。
(實施例1)
將印刷有包含Ni粉末之Ni漿料之積層單元積層至包含鈦酸鋇作為介電材料之介電坯片上，進行壓接、切割、去除黏合劑並進行焙燒，藉此製作晶片形狀為1.0 mm×0.5 mm×0.5 mm之積層晶片。介電層之厚度為0.8 μm，內部電極層之厚度為0.6 μm，介電層及內部電極層之各積層數量為470層。介電體中除調配有作為主相之介電材料以外，亦調配有適量SiO
2粉末作為燒結助劑。又，Ni漿料中添加有Au源。於將Ni設為100 at%之情形時，將Au量設為1 at%。
(實施例2)
於實施例2中，除將內部電極層之厚度設為0.5 μm以外，設為與實施例1相同之條件。
(實施例3)
於實施例3中，除將內部電極層之厚度設為0.4 μm以外，設為與實施例1相同之條件。
(實施例4)
於實施例4中，向Ni漿料中添加Pt源來代替Au源。於將Ni設為100 at%之情形時，將Pt量設為1 at%。將內部電極層之厚度設為0.4 μm。除此以外，設為與實施例1相同之條件。
(實施例5)
於實施例5中，向Ni漿料中添加Cu源來代替Au源。於將Ni設為100 at%之情形時，將Cu量設為1 at%。將內部電極層之厚度設為0.4 μm。除此以外，設為與實施例1相同之條件。
(實施例6)
於實施例6中，向Ni漿料中添加Fe源來代替Au源。於將Ni設為100 at%之情形時，將Fe量設為1 at%。將內部電極層之厚度設為0.4 μm。除此以外，設為與實施例1相同之條件。
(實施例7)
於實施例7中，向Ni漿料中添加Cr源來代替Au源。於將Ni設為100 at%之情形時，將Cr量設為1 at%。將內部電極層之厚度設為0.4 μm。除此以外，設為與實施例1相同之條件。
(實施例8)
於實施例8中，向Ni漿料中添加Zn源來代替Au源。於將Ni設為100 at%之情形時，將Zn量設為1 at%。將內部電極層之厚度設為0.4 μm。除此以外，設為與實施例1相同之條件。
(實施例9)
於實施例9中，向Ni漿料中添加In源來代替Au源。於將Ni設為100 at%之情形時，將In量設為1 at%。將內部電極層之厚度設為0.4 μm。除此以外，設為與實施例1相同之條件。
(比較例1)
於比較例1中，未向Ni漿料中添加Au源。除此以外，設為與實施例1相同之條件。
(比較例2)
於比較例2中，未向Ni漿料中添加Au源。將內部電極層之厚度設為0.5 μm。除此以外，設為與實施例1相同之條件。
(比較例3)
於比較例3中，未向Ni漿料中添加Au源。將內部電極層之厚度設為0.4 μm。除此以外，設為與實施例1相同之條件。
關於實施例1～9及比較例1～3之各者，於介電層與內部電極層之界面處進行STEM-EDS線分析。關於實施例1～9，於內部電極層側確認到包含添加元素之層，並確認到該層與介電層側之二次相接觸。
圖9係表示對實施例1之積層陶瓷電容器進行STEM-EDS線分析之位置之圖。如圖9所示，於介電層與內部電極層之界面附近且二次相與包含添加元素之層接觸之部位，自介電層朝向內部電極層進行線分析。
圖10(a)～圖11(c)係表示對實施例1之積層陶瓷電容器之STEM-EDS線分析之結果。圖10(a)示出O(氧)之測定濃度。圖10(b)示出Ti之測定濃度。圖10(c)示出Ni之測定濃度。圖11(a)示出Ba之測定濃度。圖11(b)示出Au之測定濃度。圖11(c)示出Si之測定濃度。於圖10(a)～圖11(c)中，虛線表示介電層11與內部電極層12之界面。
如圖10(a)所示，O(氧)濃度以界面為界急遽下降。認為其原因在於內部電極層中氧濃度較低。如圖10(b)所示，Ti濃度以界面為界急遽下降。認為其原因在於Ti主要包含於介電層之鈦酸鋇中，內部電極層中Ti濃度較低。如圖10(c)所示，Ni濃度以界面為界急遽增高。認為其原因在於Ni主要包含於內部電極層中，介電層中Ni濃度較低。如圖11(a)所示，Ba濃度以界面為界急遽下降。認為其原因在於Ba主要包含於介電層之鈦酸鋇中，內部電極層中Ba濃度較低。
如圖11(b)及圖11(c)所示，於界面附近出現Au濃度之峰及Si濃度之峰。Au濃度之峰相較於界面更靠近內部電極層側。認為其原因在於界面處於內部電極層側形成有包含Au之層。Si濃度之峰相較於界面更靠近介電層側。認為其原因在於界面處於介電層側形成有二次相。Au峰頂位置處之Si量之濃度較介電層中之平均水準之Si量高。又，Si峰頂位置處之Au量之濃度較內部電極層中之平均水準之Au量高。與包含Au之層接觸之二次相中之Si比率(at%)較介電層中之Si量之平均值(at%)高1 at%以上。
實施例2～9中，亦與實施例1同樣地於界面附近出現添加元素濃度之峰及Si濃度之峰。添加元素濃度之峰相較於界面更靠近內部電極層側。認為其原因在於界面處於內部電極層側形成有包含添加元素之層。Si濃度之峰相較於界面更靠近介電層側。認為其原因在於界面處於介電層側形成有二次相。添加元素峰頂位置處之Si量之濃度較介電層中之平均水準之Si量高。又，Si峰頂位置處之添加元素量之濃度較內部電極層中之平均水準之添加元素量高。再者，於各實施例中，如圖11(b)所示，包含添加元素之層為以界面為基準，於內部電極層側及介電層側各自之15 nm之範圍內，添加元素之濃度最高之區域，即示出添加元素之峰位置之區域。又，於各實施例中，如圖11(c)所示，包含Si之二次相為以界面為基準，於內部電極層側及介電層側各自之15 nm之範圍內，Si之濃度最高之區域，即示出Si之峰位置之區域。
於比較例1～3中，未確認到包含添加元素之層。
關於實施例1～9之各者，於介電層與內部電極層之界面處，對積層方向上之二次相之厚度/(包含添加元素之層)之厚度進行測定。該比率於實施例1中為0.73，於實施例2中為0.96，於實施例3中為1.10，於實施例4中為1.04，於實施例5中為1.09，於實施例6中為1.14，於實施例7中為1.12，於實施例8中為0.99，於實施例9中為0.93。
關於實施例1～9及比較例1～3之各者之積層陶瓷電容器，測定內部電極層之連續率。內部電極層之連續率藉由晶片中央附近之剖面研磨面之SEM觀察(倍率5000倍、4個視野之平均值)進行測定。於實施例及比較例中，測定相同厚度彼此之連續率比。將結果示於表1。相較於比較例1之連續率，實施例1之連續率為1.05倍。相較於比較例2之連續率，實施例2之連續率為1.14倍。相較於比較例3之連續率，實施例3之連續率為1.17倍，實施例4之連續率為1.26倍，實施例5之連續率為1.16倍，實施例6之連續率為1.17倍，實施例7之連續率為1.26倍，實施例8之連續率為1.17倍，實施例9之連續率為1.17倍。根據以上結果，可知於內部電極層之厚度相同之條件下使包含添加元素之層與二次相接觸，可提高內部電極層之連續率。
[表1]
| 內部電極層 厚度 | 添加元素 | 添加元素 | 偏析層 | 厚度比 | 連續率比 | |
| 實施例1 | 0.6 μm | Au | 1 at% | 有 | 0.73 | 1.05 |
| 比較例1 | - | - | 無 | - | 1 | |
| 實施例2 | 0.5 μm | Au | 1 at% | 有 | 0.96 | 1.14 |
| 比較例2 | - | - | 無 | - | 1 | |
| 實施例3 | 0.4 μm | Au | 1 at% | 有 | 1.10 | 1.17 |
| 實施例4 | Pt | 1 at% | 有 | 1.04 | 1.26 | |
| 實施例5 | Cu | 1 at% | 有 | 1.09 | 1.16 | |
| 實施例6 | Fe | 1 at% | 有 | 1.14 | 1.17 | |
| 實施例7 | Cr | 1 at% | 有 | 1.12 | 1.26 | |
| 實施例8 | Zn | 1 at% | 有 | 0.99 | 1.17 | |
| 實施例9 | In | 1 at% | 有 | 0.93 | 1.17 | |
| 比較例3 | - | - | 無 | - | 1 |
以上詳述了本發明之實施例，但本發明並不限於該等特定之實施例，於申請專利範圍所記載之本發明之要旨之範圍內，可進行各種變化與變更。
10:積層晶片
11:介電層
12:內部電極層
13:覆蓋層
14:容量區域
15:端邊緣
16:側邊緣
17:主相
18:二次相
19:包含添加元素之層
20a:外部電極
20b:外部電極
51:基材
52:介電坯片
53:內部電極圖案
54:覆蓋片
100:積層陶瓷電容器
L0:長度
L1:長度
L2:長度
L3:長度
L4:長度
圖1係積層陶瓷電容器之部分剖視立體圖。
圖2係圖1之A-A線剖視圖。
圖3係圖1之B-B線剖視圖。
圖4係例示形成於介電層之二次相之圖。
圖5係表示連續率之圖。
圖6係例示包含添加元素之層之圖。
圖7係例示積層陶瓷電容器之製造方法之流程之圖。
圖8(a)及(b)係例示積層步驟之圖。
圖9係表示進行STEM-EDS線分析之位置之圖。
圖10(a)～(c)係表示對實施例1之積層陶瓷電容器之STEM-EDS線分析之結果。
圖11(a)～(c)係表示對實施例1之積層陶瓷電容器之STEM-EDS線分析之結果。
11:介電層
12:內部電極層
17:主相
18:二次相
19:包含添加元素之層
Claims (9)
- 一種陶瓷電子零件，其特徵在於，具備由介電層與以Ni為主相之內部電極層交替地積層而成之積層晶片， 至少任一上述介電層於與相鄰之上述內部電極層之界面處具備包含Si之二次相， 與具備上述二次相之上述介電層相鄰之上述內部電極層於上述界面中與上述二次相接觸之部位，具備包含Au、Pt、Cu、Fe、Cr、Zn及In中之任1種以上之添加元素之層。
- 如請求項1之陶瓷電子零件，其中於與具備上述二次相之上述介電層相鄰之上述內部電極層中，上述添加元素之總量相對於Ni為0.01 at%以上5 at%以下。
- 如請求項1或2之陶瓷電子零件，其中包含上述添加元素之層為上述添加元素之單金屬、合金或氧化物。
- 如請求項1或2之陶瓷電子零件，其中上述介電層與上述內部電極層之積層方向上之(上述二次相之厚度/包含上述添加元素之層之厚度)為0.1以上3以下。
- 如請求項1或2之陶瓷電子零件，其中上述介電層之厚度為0.5 μm以下。
- 如請求項1或2之陶瓷電子零件，其中於在上述介電層與上述內部電極層之積層方向上進行STEM-EDS線分析之情形時，上述二次相中出現Si濃度之峰，包含上述添加元素之層中出現上述添加元素之濃度之峰。
- 如請求項1或2之陶瓷電子零件，其中與具備上述二次相之上述介電層相鄰之上述內部電極層之厚度為0.05 μm以上0.4 μm以下。
- 如請求項1或2之陶瓷電子零件，其中上述介電層包含鈦酸鋇。
- 一種陶瓷電子零件之製造方法，其特徵在於，包括如下步驟： 藉由於含有包含SiO 2之燒結助劑之介電坯片上形成包含Au、Pt、Cu、Fe、Cr、Zn及In中之任1種以上之添加元素之Ni漿料之內部電極圖案而形成積層單元之步驟； 藉由將複數個上述積層單元積層而形成積層體之步驟；及 對上述積層體進行焙燒之步驟； 調整上述焙燒步驟之條件，以使對上述介電坯片進行焙燒而獲得之介電層中之至少任一個於與對上述內部電極圖案進行焙燒而獲得之相鄰之內部電極層之界面處形成包含Si之二次相，並於上述相鄰之內部電極層中與上述二次相接觸之部位形成包含上述添加元素之層。
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