TW202117856A - 半導體裝置的形成方法 - Google Patents
半導體裝置的形成方法 Download PDFInfo
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- TW202117856A TW202117856A TW109126661A TW109126661A TW202117856A TW 202117856 A TW202117856 A TW 202117856A TW 109126661 A TW109126661 A TW 109126661A TW 109126661 A TW109126661 A TW 109126661A TW 202117856 A TW202117856 A TW 202117856A
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- sacrificial layer
- dielectric
- dummy gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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Abstract
形成虛置閘極於基板上。形成犧牲層於虛置閘極上。形成層間介電層於虛置閘極與犧牲層上。將虛置閘極置換成含金屬閘極。移除犧牲層。移除犧牲層的步驟保留多個氣隙於含金屬閘極周圍。接著密封氣隙。
Description
本發明實施例一般關於半導體裝置,更特別關於形成氣體間隔物。
半導體積體電路產業已經歷指數成長。積體電路材料與設計的技術進展,使每一代的積體電路比前一代的積體電路具有更小且更複雜的電路。在積體電路演進中,功能密度(比如單位晶片面積的內連線裝置數目)通常隨著幾何尺寸(比如採用的製作製程所產生的最小構件或線路)縮小而增加。尺寸縮小的製程通常有利於增加產能並降低相關成本。尺寸縮小亦增加處理與製造積體電路的複雜度。
舉例來說,隨著裝置尺寸持續縮小,寄生電容可能增加。此為不想要的現象,因為寄生電容會負面影響裝置效能如速度。為了減少寄生電容,需形成低介電常數的閘極間隔物如氣體間隔物。然而習知的製作方法不能形成可信的氣體間隔物。雖然習知的半導體製作方法通常適用,但無法滿足所有方面的需求。
本發明一實施例關於半導體裝置的形成方法,包括形成虛置閘極於基板上。形成犧牲層於虛置閘極上。形成層間介電層於虛置閘極與犧牲層上。將虛置閘極置換成含金屬閘極。移除犧牲層。移除犧牲層的步驟保留多個氣隙於含金屬閘極周圍。以及密封氣隙。
本發明另一實施例關於半導體裝置的形成方法,包括形成虛置閘極於基板上。形成介電閘極間隔物於虛置閘極的側壁上;形成犧牲層於介電閘極間隔物上。犧牲層與介電閘極間隔物的材料組成不同。形成蝕刻停止層於犧牲層上。蝕刻停止層與犧牲層的材料組成不同。形成層間介電層於虛置閘極與蝕刻停止層上。移除虛置閘極,並使層間介電層、蝕刻停止層、與介電閘極間隔物維持實質上完整。形成含金屬閘極以取代移除的虛置閘極。移除犧牲層,並使層間介電層、蝕刻停止層、與介電閘極間隔物維持實質上完整。
本發明又一實施例關於半導體裝置。包括閘極位於基板上。介電閘極間隔物位於閘極的側壁上。氣隙與介電閘極間隔物直接相鄰。密封層位於氣隙、介電閘極間隔物、與閘極上。層間介電層位於密封層上。
下述內容提供的不同實施例或實例可實施本發明的不同結構。下述特定構件與排列的實施例係用以簡化本發明內容而非侷限本發明。舉例來說,形成第一構件於第二構件上的敘述包含兩者直接接觸的實施例,或兩者之間隔有其他額外構件而非直接接觸的實施例。此外,本發明之多個實例可重複採用相同標號以求簡潔,但多種實施例及/或設置中具有相同標號的元件並不必然具有相同的對應關係。
此外,空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件,而非侷限於圖示方向。此外,當數值或數值範圍的描述有「約」、「近似」、或類似用語時,除非特別說明否則其包含所述數值的+/-10%。舉例來說,用語「約5 nm」包含的尺寸範圍介於4.5 nm至5.5 nm之間。
本發明實施例一般關於半導體裝置,更特別關於場效電晶體如平面場效電晶體或三維鰭狀場效電晶體。本發明一實施例關於形成氣體間隔物。在此考量下,隨著半導體製作方法進展至更小的技術節點,寄生電容的整體影響開始嚴重劣化裝置效能如裝置速度。由於電容為介電常數的函數,採用低介電常數材料有助於降低寄生電容。舉例來說,需採用低介電常數材料形成閘極間隔物。在此考量下,氣體的介電常數近似1,其低於大部分的介電材料之介電常數。如此一來,可採用氣體實施場效電晶體的閘極間隔物。不幸的是,形成氣體間隔物的習知方法不可信,及/或最終氣體間隔物達不到適用於現代場效電晶體裝置所需的尺寸及/或形狀。
為克服上述問題,本發明實施例採用犧牲層形成氣體間隔物。舉例來說,可形成含矽層(如非晶矽或矽鍺)如閘極與介電閘極間隔物上的犧牲層。之後移除犧牲層,以形成氣隙取代移除的犧牲層。由於犧牲層與介電閘極間隔物及閘極結構本身之間的蝕刻選擇性,移除犧牲層後的介電閘極間隔物及閘極結構維持實質上完整。可形成密封層於氣隙與閘極結構上,進而封住下方氣隙。封住的氣隙可作為電晶體的氣體間隔物(具有低介電常數)。本發明的多種實施例將搭配圖1A、1B、及2至14詳述於下。
圖1A及1B分別為積體電路裝置90的一部分之三維透視圖與上視圖。積體電路裝置90可為速度很重要之積體電路裝置的種類之一,比如環形震盪器。如此一來,實施低介電常數的間隔物對積體電路裝置90而言是有利的,其可幫助降低整體的寄生電容,進而改善積體電路裝置90的速度。
如下述圖式所示,積體電路裝置90可為處理積體電路或其部分時的中間裝置,其可包含靜態隨機存取記憶體及/或其他邏輯電路、被動構件(如電阻、電容、與電感)、與主動構件(如p型場效電晶體、n型場效電晶體、鰭狀場效電晶體、金氧半場效電晶體、互補式金氧半電晶體、雙極性電晶體、高電壓電晶體、高頻電晶體、及/或其他記憶體單元)。本發明實施例不限於任何特定數目的裝置或裝置區或任何特定的裝置設置,除非記載於請求項中。舉例來說,雖然圖示的積體電路裝置90為三維鰭狀場效電晶體裝置,本發明實施例的概念亦可用於平面場效電晶體裝置。
如圖1A所示,積體電路裝置90包括基板110。基板110可包含單一半導體元素(如矽、鍺、及/或其他合適材料)、半導體化合物(如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦、及/或其他合適材料)、或半導體合金(如矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、磷砷化鎵銦、及/或其他合適材料)。基板110可為組成一致的單層材料。在其他實施例中,基板110可包含類似組成或不同組成的多種材料層以用於製造積體電路裝置。在一例中,基板110可為絕緣層上矽基板,其具有半導體矽層形成於氧化矽層上。在另一例中,基板110可包含導電層、半導體層、介電層、其他層、或上述之組合。多種摻雜區如源極/汲極區可形成於基板110之中或之上。摻雜區可摻雜n型摻質如磷或砷,及/或p型摻質如硼,端視設計需求而定。摻雜區可直接形成於基板110上、形成於p型井結構中、形成於n型井結構中、形成於雙井結構中、或採用隆起結構。摻雜區的形成方法可為佈植摻質原子、原位摻雜的磊晶成長、及/或其他合適技術。
三維的主動區形成於基板110上。主動區為自基板110向上凸出的延伸鰭狀結構。如此一來,主動區可視作鰭狀結構120。鰭狀結構120的製作方法可採用合適製程,包括光微影與蝕刻製程。光微影製程可包含形成光阻層於基板110上、曝光光阻至一圖案、進行曝光後烘烤製程、以及顯影光阻以形成含光阻的遮罩單元(未圖示)。接著採用遮罩單元,並蝕刻凹陷至基板110中,以保留鰭狀結構120於基板110上。蝕刻製程可包含乾蝕刻、濕蝕刻、反應性離子蝕刻、及/或其他合適製程。在一些實施例中,鰭狀結構120的形成方法可為雙重圖案化或多重圖案化製程。一般而言,雙重圖案化或多重圖案化製程結合光微影與自對準製程,其產生的圖案間距小於採用單一的直接光微影製程所得的圖案間距。舉例來說,可形成層狀物於基板上,並採用光微影製程圖案化層狀物。可採用自對準製程,沿著圖案化的層狀物側部形成間隔物。接著移除層狀物,再採用保留的間隔物或芯圖案化鰭狀結構120。
積體電路裝置90亦包含源極/汲極結構122形成於鰭狀結構120上。在一些實施例中,源極/汲極結構122可包含磊晶成長於鰭狀結構120上的磊晶層。
積體電路裝置90更包含隔離結構130形成於基板110上。隔離結構130電性分隔積體電路裝置90的多種構件。隔離結構130可包含氧化矽、氮化矽、氮氧化矽、摻雜氟的矽酸鹽玻璃、低介電常數的介電材料、及/或其他合適材料。在一些實施例中,隔離結構130可包含淺溝槽隔離結構。在一實施例中,隔離結構130的形成方法可為在形成鰭狀結構120時,蝕刻溝槽於基板110中。接著將上述隔離材料填入溝槽,再進行化學機械研磨製程。亦可實施其他隔離結構如場氧化物、局部氧化矽、及/或其他合適結構,以作為隔離結構130。在其他實施例中,隔離結構130可包含多層結構,比如具有一或多個熱氧化物襯墊層。
積體電路裝置90亦包含閘極結構140形成於鰭狀結構120上,並自每一鰭狀結構120的通道區中的三側上接合鰭狀結構120。閘極結構140可為虛置閘極結構(比如包含氧化物的閘極介電層與多晶矽閘極),或高介電常數的介電層與金屬閘極結構(由置換虛置閘極結構所形成)。雖然未圖示於此,閘極結構140可包含額外材料層如鰭狀結構120上的界面層、蓋層、其他合適層、或上述之組合。
如圖1B所示,多個鰭狀結構120的長度方向沿著X方向,多個閘極結構140的長度方向沿著Y方向(通常垂直於鰭狀結構120)。在許多實施例中,積體電路裝置90包含額外結構如沿著閘極結構140之側壁的閘極間隔物(包含氣體間隔物)、位於閘極結構140上的硬遮罩層、與多種其他結構。由於空間考量,圖1A及1B未具體圖示氣體間隔物形成於閘極結構140之外。然而形成這些氣體間隔物的製作製程步驟將搭配圖2至14詳述如下。在此考量下,圖2至13的剖視圖為積體電路裝置90沿著圖1A及1B所示的剖線AA'的剖視圖,而圖14係形成氣體間隔物的方法之流程圖。
如圖2所示,積體電路裝置90包含上述基板110。隔離結構(未圖示於圖2)可形成於基板110之上及/或之中,以隔離積體電路裝置90的多種區域。舉例來說,隔離結構定義主動裝置區及/或被動裝置區,並使其彼此電性隔離。在一些實施方式中,隔離結構可設置以隔離對應閘極結構與源極/汲極結構的電晶體與積體電路裝置90的其他電晶體、裝置、及/或區域。隔離結構包含隔離材料,比如氧化矽、氮化矽、氮氧化矽、其他合適的隔離材料(如含矽、氧、氮、碳、及/或其他合適的隔離成分)、或上述之組合。隔離結構可包含不同結構,比如淺溝槽隔離結構、深溝槽隔離結構、及/或局部氧化矽結構。
在一些實施例中,淺溝槽隔離結構的形成方法可為蝕刻溝槽於基板110中(比如採用乾蝕刻製程及/或濕蝕刻製程),並將絕緣材料填入溝槽(比如採用化學氣相沉積製程或旋轉塗佈玻璃製程)。可進行化學機械研磨製程,以移除多餘絕緣材料及/或平坦化淺溝槽隔離結構的上表面。在一些實施方式中,淺溝槽隔離結構的形成方法可為在形成鰭狀物之後沉積絕緣材料於基板110上,使絕緣材料層填入鰭狀結構之間的間隙(如溝槽),接著回蝕刻絕緣材料層。在一些實施方式中,隔離結構包括填入溝槽的多層結構,比如基體介電層位於襯墊介電層上,其中基體介電層與襯墊介電層包含的材料取決於設計需求而定。舉例來說,包含氮化矽的基體介電層可位於包含熱氧化物的襯墊介電層上。在一些實施例中,隔離結構包括介電層位於摻雜襯墊層(包含硼矽酸鹽玻璃或磷矽酸鹽玻璃)上。
在圖2所示的製作階段中,仍未形成閘極結構140 (如高介電常數的介電層與金屬閘極)。相反地,此製作階段形成虛置閘極結構200於基板110上。在一些實施例中,虛置閘極結構可包含高介電常數的閘極介電層(介電常數大於氧化矽的介電常數之介電材料)與虛置閘極(如多晶矽的虛置閘極)。在之後進行的置換閘極製程中,高介電常數的閘極介電層可維持完整,且虛置閘極可置換成含金屬閘極。在其他實施例中,虛置閘極結構可包含虛置閘極介電層與虛置閘極。舉例來說,虛置閘極介電層可包含氧化矽。在這些實施例中,可置換虛置閘極介電層與虛置閘極。可將虛置閘極介電層置換成高介電常數的閘極介電層,並將虛置閘極置換成含金屬閘極。此閘極置換製程的變化可視作高介電常數的介電層之後製製程。
如圖2所示,圖案化的硬遮罩層210及220位於虛置閘極結構200上。圖案化的硬遮罩層210及220的形成方法可採用一或多道的沉積製程,並採用一或多道微影製程圖案化。接著可採用圖案化的硬遮罩層210及220作為遮罩,以定義(如圖案化)虛置閘極結構200。在一些實施例中,硬遮罩層210及220可包含不同種類的介電材料。舉例來說,硬遮罩層210可含氧化矽,而硬遮罩層220可含氮化矽,反之亦然。
亦可形成介電閘極間隔物230以與虛置閘極結構200相鄰,比如在X方向中形成於虛置閘極結構200的側壁上。介電閘極間隔物230的形成方法可為沉積介電材料與圖案化介電材料。沉積的介電材料可含矽、氧、碳、氮、其他合適材料、或上述之組合,比如氧化矽、氮化矽、氮氧化矽、或碳化矽。舉例來說,所述實施例可沉積含矽與氮的介電層如氮化矽層於基板110上,接著非等向蝕刻介電層以形成介電閘極間隔物230。在一些實施方式中,介電閘極間隔物230可包含多層結構,比如含氮化矽的第一介電層與含氧化矽的第二介電層。在一些實例中,介電閘極間隔物230可包含超過一組間隔物與閘極結構140相鄰,比如密封間隔物、補償間隔物、犧牲間隔物、虛置間隔物、及/或主要間隔物。在這些實施方式中,多組間隔物可包含不同蝕刻速率的的材料。舉例來說,可沉積包含矽與氧的第一介電層於基板110上,接著非等向蝕刻第一介電層以形成與閘極堆疊相鄰的第一組間隔物。可沉積包含矽與氮的第二介電層於基板110上,接著非等向蝕刻第二介電層以形成與第一組間隔物相鄰的第二組間隔物。
在形成介電閘極間隔物230之前及/或之後可進行佈植、擴散、及/或退火製程,以形成輕摻雜源極/汲極結構及/或重摻雜源極/汲極結構(兩者均未圖式於圖2)於源極/汲極區中。亦可進行一或多道退火製程,以退火輕摻雜源極/汲極結構及/或重摻雜源極/汲極結構。
如圖3所示,對積體電路裝置90進行犧牲層形成製程240,以形成犧牲層250於虛置閘極結構200上。舉例來說,犧牲層250可形成於硬遮罩層220與介電閘極間隔物230上。犧牲層250的部分位於介電閘極間隔物230的側表面上。之後將移除犧牲層,並形成氣體間隔物以取代移除的犧牲層250,如下詳述。
犧牲層250與介電閘極間隔物230的材料組成不同,因此兩者之間可具有蝕刻選擇性。舉例來說,犧牲層250可為含矽層。在一些實施例中,犧牲層250包含非晶矽材。在其他實施例中,犧牲層250包括矽鍺材料。在一些實施例中,犧牲層形成製程240可包含以化學氣相沉積爐成長非晶矽或矽鍺。
犧牲層250在圖2所示的X方向中可具有厚度或寬度260。設置犧牲層形成製程240的製程參數如設置製程時間長度,可調整厚度或寬度260的數值。由於間隔物的形成方法為移除犧牲層250,厚度或寬度260可對應氣體間隔物的寬度。在一些實施例中,厚度或寬度260介於約1 nm至約5 nm之間。厚度或寬度所用的這些數值範圍並非隨機選擇,而是具體設置為確認之後形成的氣體間隔物具有所需的厚度或寬度。舉例來說,厚度或寬度260大到足以減少閘極間隔物的整體介電常數(因此降低寄生電容),但不會非必要地厚到消耗晶片有效面積。
亦需注意的是在X方向中,厚度或寬度260實質上小於虛置閘極結構200的寬度270。在一些實施例中,厚度或寬度260比寬度270小至少五倍。相應地,犧牲層250的高寬比可遠大於虛置閘極結構200的高寬比,因為彼此的高度大致相同。寬度260及270 (或對應的高寬比)之間的差異,在移除虛置閘極結構時會造成犧牲層250與虛置閘極結構200之間的移除速率不同,如下詳述。
如圖4所示,對積體電路裝置90進行蝕刻製程300。在一些實施例中,蝕刻製程300包括濕蝕刻製程。蝕刻製程300部分地蝕刻移除犧牲層250。舉例來說,蝕刻移除直接位於硬遮罩層220上的犧牲層250之部分,直到露出硬遮罩層220的上表面。蝕刻製程300亦蝕刻移除直接位於基板110上的犧牲層250的部分。在進行蝕刻製程300之後,犧牲層250的部分仍保留於介電閘極間隔物230的側表面上。
進行蝕刻製程300的理由之一為避免非刻意的橋接(如電性短路)。如上所述,犧牲層250包括非晶矽或矽鍺,其為至少半導體性的材料。若未自這些水平表面(比如硬遮罩層220與基板110的表面)移除犧牲層250,犧牲層250的存在將造成應彼此絕緣的微電子構件之間的非預期電性連接。換言之,若無蝕刻製程300,犧牲層250的半導體特性會造成這些微電子構件的非刻意短路。此處的蝕刻製程300可確保這些電性短路不會發生,且犧牲層250的保留部分為大部分垂直取向的結構以利形成氣體間隔物,如下詳述。
如圖5所示,對積體電路裝置90進行沉積製程310,以形成蝕刻停止層320於積體電路裝置90上。沉積製程310可包含化學氣相沉積、物理氣相沉積、原子層沉積、高密度電漿化學氣相沉積、有機金屬化學氣相沉積、遠端電漿化學氣相沉積、電漿輔助化學氣相沉積、低壓化學氣相沉積、原子層化學氣相沉積、常壓化學氣相沉積、或上述之組合。蝕刻停止層320的材料組成與犧牲層250的材料組成不同,在後續進行的一或多個蝕刻製程時可達蝕刻停止層320與犧牲層250之間的蝕刻選擇性。在多種實施例中,蝕刻停止層320可包含介電材料如氧化矽、氮化矽、氮氧化矽、碳化矽、碳氮氧化矽、或上述之組合,只要蝕刻停止層320的材料組成與犧牲層250的材料組成不同。如圖5所示,蝕刻停止層320沉積於硬遮罩層220與犧牲層250上。蝕刻停止層320的部分沉積於犧牲層250的側表面上。換言之,犧牲層250可直接位於介電閘極間隔物230與蝕刻停止層320之間。
如圖6所示,對積體電路裝置90進行層間介電層形成製程340,以形成層間介電層350。在一些實施例中,層間介電層形成製程340包括沉積製程如化學氣相沉積、物理氣相沉積、原子層沉積、高密度電漿化學氣相沉積、有機金屬化學氣相沉積、遠端電漿化學氣相沉積、電漿輔助化學氣相沉積、低壓化學氣相沉積、原子層化學氣相沉積、常壓化學氣相沉積、或上述之組合。在一些實施方式中,沉積製程可包含可流動的化學氣相沉積製程,其包含沉積可流動材料(如液體化合物)於基板110上,並以合適技術如熱退火及/或紫外線處理使可流動材料轉換成固體材料。層間介電層形成製程340亦可包含在沉積製程之後,進行一或多道化學機械研磨製程及/或其他平坦化製程。化學機械研磨製程可平坦化層間介電層350的上表面,使層間介電層350具有實質上平坦的上表面。
層間介電層形成製程340造成層間介電層350在Z方向中位於基板110與蝕刻停止層320上,並在X方向中橫向圍繞虛置閘極結構200。在一些實施例中,層間介電層350可包含介電材料如氧化矽、氮化矽、氮氧化矽、四乙氧基矽烷形成的氧化物、磷矽酸鹽玻璃、硼磷矽酸鹽玻璃、低介電常數的介電材料、其他合適的介電材料、或上述之組合。例示性的低介電常數的介電材料包括摻雜氟的矽酸鹽玻璃、摻雜碳的氧化矽、Black Diamond® (Applied Materials,加州Santa Clara)、乾凝膠、氣膠、非晶氟化碳、聚對二甲苯、苯并環丁烯、SiLK (Dow Chemical,密西根州,Midland)、聚醯亞胺、其他低介電常數的介電材料、或上述之組合。層間介電層350亦可視作第零層間介電層。
如圖7所示,對積體電路裝置90進行硬遮罩移除製程370,以移除硬遮罩層210及220。硬遮罩移除製程370亦移除介電閘極間隔物230、犧牲層250、蝕刻停止層320、與層間介電層350的上側部分。在一些實施例中,硬遮罩移除製程370包含一或多道的蝕刻製程及/或研磨製程。在完成硬遮罩移除製程370之後,露出虛置閘極結構200的上表面,且虛置閘極結構200的上表面與介電閘極間隔物230、犧牲層250、蝕刻停止層320、及層間介電層350的上表面實質上共平面。
如圖8所示,進行虛置閘極移除製程390以移除虛置閘極結構200。虛置閘極移除製程390可包含一或多道的蝕刻製程,以蝕刻移除虛置閘極結構200的部分,而實質上不影響介電閘極間隔物230、犧牲層250、蝕刻停止層320、與層間介電層350。在虛置閘極結構200包括虛置多晶矽閘極的實施例中,可移除虛置多晶矽閘極。在虛置閘極結構200包含虛置閘極介電層(如氧化矽的閘極介電層)與虛置多晶矽閘極的實施例中,可由虛置閘極移除製程390移除虛置閘極介電層與虛置多晶矽閘極。在進行虛置閘極移除製程390之後,可形成開口400取代移除的虛置閘極結構200。
值得注意的是,虛置閘極移除製程390亦可部分地移除犧牲層250,如圖8所示。換言之,虛置閘極移除製程390可減少犧牲層250的高度。這是因為虛置閘極結構200與犧牲層250均為含矽結構。舉例來說,虛置閘極結構200可包含多晶矽,且犧牲層250可包含非晶矽或矽鍺。由於虛置閘極結構200與犧牲層250的材料組成類似,因此難以設置兩者之間具有高蝕刻選擇性。然而犧牲層250的橫向尺寸遠小於虛置閘極結構200的橫向尺寸(比如寬度260比寬度270小至少五倍),且犧牲層250的高寬比大於虛置閘極結構200的高寬比。與虛置閘極結構200的移除速率相較,會減緩犧牲層250的移除速率。綜上所述,虛置閘極移除製程390不完全移除犧牲層250,此屬不想要的現象。因為最終氣隙(若完全移除犧牲層250所產生)將填有後續金屬閘極形成製程所沉積的金屬材料。在任何狀況下,雖然此處的虛置閘極移除製程390可部分移除犧牲層250,但犧牲層250的實質部分將保留於虛置閘極移除製程390之後,如圖8所示。後續製程將移除犧牲層250的這些部分以形成氣隙。
如圖9所示,進行金屬閘極形成製程420以形成閘極結構140於開口400中。在一些實施例中,金屬閘極形成製程420包括一或多道沉積製程,以沉積含金屬的閘極填入開口400。在一些實施例中,金屬閘極形成製程420包括一或多道沉積製程,以沉積高介電常數的閘極介電層於開口400中,接著沉積含金屬的閘極於高介電常數的閘極介電層上。閘極結構140各自夾設於源極區與汲極區之間,其中通道區定義於源極區與汲極區之間的基板110中。閘極結構140接合通道區,使操作時的電流可流動於源極/汲極區之間。在一些實施方式中,閘極結構140形成於鰭狀結構(比如圖1A及1B的鰭狀結構120)上,使閘極結構140各自包覆鰭狀結構的一部分。舉例來說,閘極結構140包覆鰭狀結構的通道區,進而夾設於鰭狀結構的源極區與汲極區之間。
在一些實施例中,閘極介電層順應性地位於開口400之側壁表面與下表面上,使閘極介電層通常為U形且具有實質上一致的厚度。在實施例中,閘極介電層包含高介電常數的介電材料,比如介電常數大於氧化矽的介電常數(如約3.9)的介電材料。例示性的高介電常數的介電材料包括鉿、鋁、鋯、鑭、鉭、鈦、釔、氧、氮、其他合適成分、或上述之組合。舉例來說,高介電常數的介電層可包含氧化鉿、氧化鉿矽、氮氧化鉿矽、氧化鉿鉭、氧化鉿鈦、氧化鉿鋯、氧化鋯、氧化鋁、氧化鉿-氧化鋁、氧化鈦、氧化鉭、氧化鑭、氧化釔、其他合適的高介電常數的介電材料、或上述之組合。在一些實施方式中,閘極介電層包含多層結構,比如界面層(如氧化矽)與界面層上的合適高介電常數的介電層。
閘極結構140的閘極包含導電材料。在一些實施方式中,閘極包含多層,比如一或多個蓋層、功函數層、黏著及/或阻障層、及/或金屬填充(或基體)層。蓋層包含的材料可避免及/或消除閘極介電層與閘極的其他層之間的成分反應及/或擴散。在一些實施方式中,蓋層包括金屬與氮,比如氮化鈦、氮化鉭、氮化鎢、氮化鈦矽、氮化鉭矽、或上述之組合。功函數層包括導電材料如n型功函數材料及/或p型功函數材料,其可調整為具有所需功函數(如n型功函數或p型功函數)。p型功函數材料包含氮化鈦、氮化鉭、釕、鉬、鋁、氮化鎢、鋯矽化物、鉬矽化物、鉭矽化物、鎳矽化物、其他p型功函數材料、或上述之組合。n型功函數材料包括鈦、鋁、銀、錳、鋯、鈦鋁、碳化鈦鋁、碳化鉭、碳氮化鉭、氮化鉭矽、鉭鋁、碳化鉭鋁、氮化鈦鋁、其他n型功函數材料、或上述之組合。閘極結構140可包含黏著層及/或阻障層,其包含的材料可促進相鄰層狀物(比如功函數層與金屬填充層)之間的黏著性,及/或阻擋及/或減少閘極層(比如功函數層與金屬填充層)之間的擴散。舉例來說,黏著層及/或阻障層包含金屬(比如鎢、鋁、鉭、鈦、鎳、銅、鈷、其他合適金屬、或上述之組合)、金屬氧化物、金屬氮化物(比如氮化鈦)、或上述之組合。金屬填充層可包含合適的導電材料如鋁、鎢、及/或銅。
應理解的是,金屬閘極形成製程420可包含一或多道平坦化製程,比如化學機械研磨製程。舉例來說,在形成閘極結構140於開口400中之後,化學機械研磨製程可平坦化閘極結構140的上表面,直到閘極結構140的上表面與介電閘極間隔物230、犧牲層250、蝕刻停止層320、與層間介電層350的上表面實質上共平面。
如圖10所示,對積體電路裝置90進行犧牲層移除製程440,以移除犧牲層250。犧牲層移除製程440可包含一或多道蝕刻製程。由於材料組成不同,犧牲層250與閘極結構140之間、犧牲層250與介電閘極間隔物230之間、犧牲層250與蝕刻停止層320之間、以及犧牲層250與層間介電層350之間具有蝕刻選擇性。舉例來說,可設置一或多道蝕刻製程,使犧牲層250的蝕刻移除速率實質上大於閘極結構140、介電閘極間隔物230、蝕刻停止層320、與層間介電層350的蝕刻移除速率(比如大十倍以上)。在此方式中,可完全蝕刻移除犧牲層250,且閘極結構140、介電閘極間隔物230、蝕刻停止層320、與層間介電層350可維持實質上完整。
移除犧牲層250可形成氣隙450取代移除的犧牲層250,之後可密封氣隙450以形成積體電路裝置90所用的氣體間隔物。如圖10所示,氣隙450位於介電閘極間隔物230與蝕刻停止層320之間。氣隙450亦各自呈現圖10的剖視圖中,實質上垂直伸長的輪廓或形狀。換言之,氣隙450可類似在Z方向中垂直站立的柱狀物或條狀物。在一些實施例中,氣隙的寬度可與犧牲層250的寬度260實質上相同,比如前述範圍(介於約1 nm至約5 nm之間)。同樣地,可設置圖3所示的上述犧牲層形成製程240的參數以調整寬度260。
應理解的是,雖然圖式中的氣隙450形成於基板110上,但氣隙450亦可形成於隔離結構如淺溝槽隔離上。
如圖11所示,對積體電路裝置90進行密封層沉積製程470以形成密封層500。密封層500形成於閘極結構140、介電閘極間隔物230、蝕刻停止層320、與層間介電層350上。密封層500可密封下方的氣隙450,且氣隙450可作為積體電路裝置90所用的氣體間隔物。
在一些實施例中,密封層沉積製程470包括填隙特性不大的沉積製程,比如化學氣相沉積製程。這是因為沉積製程用於密封氣隙450而非完全填入氣隙450。雖然填隙特性不良,密封層沉積製程470仍可部分填入氣隙450。舉例來說,密封層500的部分仍可在Z方向中向下延伸或凸出至氣隙450中,使密封層500的下表面低於閘極結構140、介電閘極間隔物230、蝕刻停止層320、與層間介電層350的上表面(比如低1 nm至2 nm)。在一些實施例中,密封層500可包含介電材料如氮化矽。
如圖12所示,對積體電路裝置90進行層間介電層形成製程540,以形成另一層間介電層550。層間介電層形成製程540包含的步驟可與搭配圖6說明的上述層間介電層形成製程340類似,且最終的層間介電層550之材料組成與層間介電層350之材料組成類似。為了簡化的理由,此處不重述層間介電層形成製程540與層間介電層550的細節。層間介電層550形成於密封層500上。如圖13所示,對積體電路裝置90進行內連線結構形成製程580,以形成多層內連線結構600的多種內連線構件。多層內連線結構600使積體電路裝置90的多種裝置(比如電晶體、電阻、電容、及/或電感)及/或構件(比如閘極結構及/或源極/汲極結構)電性耦接在一起,使多種裝置及/或構件依照積體電路裝置90的設計需求規格操作。多層內連線結構600包括介電層與導電層(如金屬層)的組合,其設置以形成多種內連線結構。導電層設置以形成垂直內連線結構如接點及/或通孔(以提供結構之間的垂直連接及/或垂直電性線路),及/或水平內連線結構如導電線路(以提供水平電性線路)。垂直內連線結構通常可連接多層內連線結構600之不同層(或不同平面)中的水平內連線結構。在操作時,多層內連線結構600可設置積體電路裝置90的裝置及/或構件之間的訊號(比如時間訊號、電壓訊號、及/或地線訊號)之路徑,及/或輸送訊號至積體電路裝置90的裝置及/或構件。
如圖13所示,內連線結構600包括密封層500、層間介電層550、形成於層間介電層550上的層狀物610,以及形成於層狀物610上的另一層間介電層620。舉例來說,層狀物610可為蝕刻停止層,而層間介電層620可與層間介電層550或350類似。由於層間介電層350可視作第零層間介電層,且層間介電層550可視作第一層間介電層,因此層間介電層620可視作第二層間介電層。多層內連線結構600亦包含導電構件如源極/汲極接點650 (電性耦接至積體電路裝置90的源極/汲極結構)、形成於源極/汲極接點650上的源極/汲極通孔660、以及形成於閘極結構140上的閘極接點670。源極/汲極接點650、源極/汲極通孔660、與閘極接點670可包含金屬或金屬化合物。舉例來說,源極/汲極接點650、源極/汲極通孔660、與閘極接點670可包含鈷、鎢、釕、銅、銀、或鈦。源極/汲極接點650、源極/汲極通孔660、與閘極接點670的形成方法可為蝕刻溝槽於密封層500、層狀物610、與層間介電層550及620中,接著將金屬材料填入溝槽。可進行平坦化製程如化學機械研磨製程,以平坦化源極/汲極接點650、源極/汲極通孔660、與閘極接點670的上表面。
應理解的是,雖然圖式中的多層內連線結構600具有給定數目的介電層與導電層,本發明實施例的多層內連線結構600可具有更多或更少的介電層及/或導電層。
圖14係本發明另一實施例中,製作半導體裝置的方法900之流程圖。方法900包含的步驟910可形成虛置閘極於基板上。
方法900包含的步驟920可形成犧牲層於虛置閘極上。在一些實施例中,步驟920包括形成非晶矽層如犧牲層。
方法900包含的步驟930可形成層間介電層於虛置閘極與犧牲層上。
方法900包含的步驟940可置換虛置閘極成含金屬閘極。在一些實施例中,步驟940包括採用一或多道蝕刻製程移除虛置閘極。一或多道蝕刻製程可部分蝕刻移除犧牲層。
方法900包含的步驟950可移除犧牲層,其中移除犧牲層的步驟留下氣隙於含金屬閘極周圍。在一些實施例中,氣隙各自具有伸長的輪廓。
方法900包含的步驟960可密封氣隙。在一些實施例中,步驟960包括形成密封層於氣隙與含金屬閘極上。在一些實施例中,密封層的部分可部分延伸至氣隙中。在一些實施例中,步驟960包括採用化學氣相沉積製程沉積介電材料如密封層。
應理解的是在步驟910至960之前、之中、或之後可進行額外步驟。舉例來說,在形成犧牲層之前,方法900可形成介電閘極間隔物於虛置閘極的側壁上。犧牲層的部分形成於介電閘極間隔物上。氣隙直接與介電閘極間隔物相鄰。在一些實施例中,移除犧牲層的步驟包括進行蝕刻製程以蝕刻移除犧牲層,且蝕刻製程對「犧牲層」與「虛置閘極及介電閘極間隔物」具有蝕刻選擇性。在一些實施例中,方法900可包含形成蝕刻停止層於犧牲層上的步驟。額外步驟可包含形成額外的內連線結構、封裝、與測試製程。
總結而言,本發明實施例關於形成電晶體所用的氣體間隔物。舉例來說,可形成含矽犧牲層(如含多晶矽或矽鍺)於虛置閘極上。「犧牲層」與「介電閘極間隔物及蝕刻停止層」具有蝕刻選擇性。在置換虛置閘極成金屬閘極之後,移除犧牲層以形成氣隙取代移除的犧牲層。由於犧牲層與其他構件(如金屬閘極、介電閘極間隔物、與蝕刻停止層)之間的蝕刻選擇性,移除犧牲層的步驟不會損傷這些其他構件而使其維持完整。接著以密封層密封氣隙頂部。
基於上述內容,本發明實施例比習知源極/汲極通孔提供多種優點。然而應理解此處不必說明所有優點,不同實施例可提供不同優點,且任何實施例不必具有特定優點。本發明實施例的優點之一係以可信方式形成氣體間隔物。習知的製作方法不是未採用氣體間隔物,就是難以形成可信的氣體間隔物。如上所述,氣體間隔物具有低介電常數(近似1),其有助於降低寄生電容。減少寄生電容可改良裝置效能如速度,特別有利於高速的積體電路應用於環形震盪器。本發明實施例形成的氣體間隔物亦可達閘極間隔物所需的垂直伸長形狀。此外,可在沉積時設置犧牲層厚度,以彈性調整氣體間隔物尺寸。如此一來,可調整閘極間隔物(含氣體間隔物)的介電常數以符合特定的設計需求。其他優點可包含與現存的製作製程相容、使實施方法易於進行、以及降低實施方法的成本。
上述進階的微影製程、方法、與材料可用於許多應用,包含鰭狀場效電晶體。舉例來說,可圖案化鰭狀物以產生結構之間的較緊密間隔,以適用於上述內容。此外,形成鰭狀場效電晶體的鰭狀物所用的間隔物(亦視作芯)可依據上述內容處理。
本發明一實施例關於半導體裝置的形成方法。形成虛置閘極於基板上。形成犧牲層於虛置閘極上。形成層間介電層於虛置閘極與犧牲層上。將虛置閘極置換成含金屬閘極。移除犧牲層。移除犧牲層的步驟保留多個氣隙於含金屬閘極周圍。以及密封氣隙。
在一些實施例中,形成犧牲層的步驟包括形成非晶矽層作為犧牲層。
在一些實施例中,上述方法更包括在形成犧牲層之前,形成介電閘極間隔物於虛置閘極的側壁上,其中犧牲層的部分形成於介電閘極間隔物上,且其中氣隙與介電閘極間隔物直接相鄰。
在一些實施例中,移除犧牲層的步驟包括進行蝕刻製程以蝕刻移除犧牲層,且其中蝕刻製程在犧牲層與虛置閘極及介電閘極間隔物之間具有蝕刻選擇性。
在一些實施例中,上述方法更包括形成蝕刻停止層於犧牲層上。
在一些實施例中,密封氣隙的步驟包括形成密封層於氣隙與含金屬閘極上。
在一些實施例中,密封層的部分部分延伸至氣隙中。
在一些實施例中,密封氣隙的步驟包括採用化學氣相沉積製程沉積介電材料作為密封層。
在一些實施例中,氣隙各自具有伸長輪廓。
在一些實施例中,置換虛置閘極的步驟包括採用一或多道蝕刻製程移除虛置閘極,且一或多道蝕刻製程部分地蝕刻移除犧牲層。
本發明另一實施例關於半導體裝置的形成方法。形成虛置閘極於基板上。形成介電閘極間隔物於虛置閘極的側壁上;形成犧牲層於介電閘極間隔物上。犧牲層與介電閘極間隔物的材料組成不同。形成蝕刻停止層於犧牲層上。蝕刻停止層與犧牲層的材料組成不同。形成層間介電層於虛置閘極與蝕刻停止層上。移除虛置閘極,並使層間介電層、蝕刻停止層、與介電閘極間隔物維持實質上完整。形成含金屬閘極以取代移除的虛置閘極。移除犧牲層,並使層間介電層、蝕刻停止層、與介電閘極間隔物維持實質上完整。
在一些實施例中,形成犧牲層的步驟包括形成非晶矽層作為犧牲層。
在一些實施例中,移除犧牲層的步驟形成氣體間隔物以取代移除的犧牲層,且其中氣體間隔物垂直延伸並位於蝕刻停止層與介電閘極間隔物之間。
在一些實施例中,上述方法更包括形成介電層於含金屬閘極上,其中介電層密封下方的氣體間隔物。
在一些實施例中,形成介電層的步驟包括採用化學氣相沉積製程沉積氮化矽。
本發明又一實施例關於半導體裝置。閘極位於基板上。介電閘極間隔物位於閘極的側壁上。氣隙與介電閘極間隔物直接相鄰。密封層位於氣隙、介電閘極間隔物、與閘極上。層間介電層位於密封層上。
在一些實施例中,上述半導體裝置更包括蝕刻停止層,且氣隙位於蝕刻停止層與介電閘極間隔物之間。
在一些實施例中,氣隙在剖面圖中具有伸長形狀。
在一些實施例中,密封層部分延伸至氣隙中。
在一些實施例中,閘極包括金屬閘極。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明作基礎,設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解,這些等效置換並未脫離本發明精神與範疇,並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
AA’:剖線
90:積體電路裝置
110:基板
120:鰭狀結構
122:源極/汲極結構
130:隔離結構
140:閘極結構
200:虛置閘極結構
210,220:硬遮罩層
230:介電閘極間隔物
240:犧牲層形成製程
250:犧牲層
260,270:寬度
300:蝕刻製程
310:沉積製程
320:蝕刻停止層
340,540:層間介電層形成製程
350,550,620:層間介電層
370:硬遮罩移除製程
390:虛置閘極移除製程
400:開口
420:金屬閘極形成製程
440:犧牲層移除製程
450:氣隙
470:密封層沉積製程
500:密封層
580:內連線結構形成製程
600:多層內連線結構
610:層狀物
650:源極/汲極接點
660:源極/汲極通孔
670:閘極接點
900:方法
910,920,930,940,950,960:步驟
圖1A係本發明多種實施例中,積體電路裝置的透視圖。
圖1B係本發明多種實施例中,積體電路裝置的平面上視圖。
圖2至13係本發明多種實施例中,積體電路裝置在製作的多種階段中的剖視圖。
圖14係本發明多種實施例中,製作半導體裝置的方法之流程圖。
900:方法
910,920,930,940,950,960:步驟
Claims (1)
- 一種半導體裝置的形成方法,包括: 形成一虛置閘極於一基板上; 形成一犧牲層於該虛置閘極上; 形成一層間介電層於該虛置閘極與該犧牲層上; 將該虛置閘極置換成一含金屬閘極; 移除該犧牲層,其中移除該犧牲層的步驟保留多個氣隙於該含金屬閘極周圍;以及 密封該些氣隙。
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