TW202036733A - 半導體裝置及半導體封裝 - Google Patents

半導體裝置及半導體封裝 Download PDF

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TW202036733A
TW202036733A TW109107376A TW109107376A TW202036733A TW 202036733 A TW202036733 A TW 202036733A TW 109107376 A TW109107376 A TW 109107376A TW 109107376 A TW109107376 A TW 109107376A TW 202036733 A TW202036733 A TW 202036733A
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bump
semiconductor device
length
layer
semiconductor
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TW109107376A
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TWI822971B (zh
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劉瑋瑋
翁煇翔
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日月光半導體製造股份有限公司
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Abstract

本案提供一種半導體裝置及一種包含該半導體裝置之半導體封裝。該半導體裝置包括：半導體元件；保護層，其設置鄰近於該半導體元件之表面，該保護層界定開口以曝露該半導體元件；第一凸塊，其設置於該半導體元件上；及第二凸塊，其設置至該保護層之表面上。該第一凸塊相比於該第二凸塊具有較大橫截面表面積。

Description

半導體裝置及半導體封裝
本案係關於一種半導體裝置，且更特定言之，係關於一種包括凸塊之半導體裝置及一種包含該裝置之半導體封裝。
在半導體覆晶接合製程中，晶片係置放於基板(或另一晶片)上。可經由設置於晶片上之金屬凸塊且經由設置於基板上之接合墊將晶片電連接至基板。可使用焊料以實體上連接金屬凸塊與接合墊。
小型化已對在半導體裝置上模製金屬凸塊(molding of metal bumps)期間產生之組裝應力(assembly stresses)造成了嚴重的影響。此類應力可能會在凸塊中產生裂紋或甚至產生晶片或晶粒之分離，從而在晶片與基板之間引起不良的電連接。因此，將需要提供一種具有新穎且具進步性之凸塊的半導體裝置，以減少在模製製程期間產生之組裝應力且防止晶片與基板之間的不良的電連接。
在一方面，一種半導體裝置包括：半導體元件；保護層，其設置鄰近於該半導體元件之表面，該保護層界定開口以曝露該半導體元件；第一凸塊，其設置於該半導體元件上；及第二凸塊，其設置至該保護層之表面上。該第一凸塊相比於該第二凸塊具有較大橫截面表面積。
在一方面，一種半導體裝置包括：半導體元件；第一凸塊，其設置緊鄰於該半導體元件之表面，其中該第一凸塊包括第一柱及第一焊料層；及第二凸塊，其設置緊鄰於該半導體元件之該表面，其中該第二凸塊包括第二柱及第二焊料層。該第一柱與該第二柱具有實質上相同高度，且該第一焊料層與該第二焊料層不具有實質上相同高度。另外，該第一凸塊相比於該第二凸塊具有較大橫截面表面積。
在一方面，一種半導體封裝包含半導體裝置及第二半導體元件。該半導體裝置包含：第一半導體元件；保護層，其設置鄰近於該第一半導體元件之表面，該保護層界定開口以曝露該第一半導體元件；第一凸塊，其設置於該第一半導體元件上；及第二凸塊，其設置至該保護層之表面上，其中該第一凸塊相比於該第二凸塊具有較大橫截面表面積。該第二半導體元件包含第一接合墊，該第一接合墊設置鄰近於該第二半導體元件之表面且對應於第一凸塊；其中該第一凸塊接合至該第一接合墊。
在一方面，一種形成半導體裝置之方法包含：提供半導體元件，該半導體元件包含設置鄰近於該半導體元件之表面的至少一個接合墊；將保護層設置鄰近於該半導體元件之該表面，該保護層界定開口以曝露該接合墊；在該接合墊上設置第一柱；及將第二柱設置鄰近於該保護層之表面，其中該第一柱相比於該第二柱具有較大橫截面表面積。
除非另有指定，否則關於各圖中所展示之定向來指示諸如「上方」、「頂部」、「底部」、「較高」、「下部」、「下方」等之空間描述。應理解，本文中所使用之空間描述僅出於說明之目的，且本文中所描述之結構之實際實施方案可以任何定向或方式在空間上配置，其限制條件為本發明之實施例之優點不會因此類配置而有偏差。
在半導體覆晶接合製程中，晶片係置放於基板(或另一晶片)上。可經由設置於晶片上之金屬凸塊且經由設置於基板上之接合墊將晶片電連接至基板。可使用焊料以實體上連接金屬凸塊與接合墊。回焊製程使焊料熔融，使得金屬凸塊可與接合墊接合，以形成覆晶接合結構。然而，此類接合結構可能會易碎，此係因為在金屬凸塊之模製製程期間常常會產生組裝應力。組裝應力可能會使金屬凸塊破裂或甚至造成晶片或晶粒之分離。結果可為晶片與基板之間的不良電連接以及低可靠性。
本案實現了一種具有改良型金屬凸塊之改良型半導體裝置，其可減少在金屬凸塊之模製製程期間常常產生之組裝應力。
圖1繪示根據本案之實施例的半導體裝置100的剖面圖。圖1之半導體裝置100包括半導體元件102、保護層104、多個第一凸塊106及多個第二凸塊108。
半導體元件102可為晶粒、晶片、封裝或中介層。半導體元件102具有第一表面102a、與第一表面102a相對之第二表面102b，及一或多個接合墊110。接合墊110被設置鄰近於半導體元件102之第一表面102a。接合墊110可為例如跡線之接觸墊。在圖1之實施例中，第一表面102a為主動表面，接合墊110為接觸墊，且接合墊110直接設置於半導體元件102之第一表面102a上。接合墊110可包括例如銅、金、銦、錫、銀、鈀、鋨、銥、釕、鈦、鎂、鋁、鈷、鎳或鋅或其他金屬或金屬合金中之一者或其組合。
保護層104被設置鄰近於半導體元件102之第一表面102a。如圖1中所展示，保護層104設置於半導體元件102之第一表面102a上方。保護層104界定一或多個開口104c。每一開口104c對應於各別接合墊110且曝露接合墊110之至少一部分。保護層104包括聚醯亞胺或其他合適材料(例如，感光材料)。保護層104可為鈍化層或絕緣層(其材料可為氧化矽或氮化矽，或另一絕緣材料)。在諸如圖1中所繪示之實施例的一些實施例中，保護層104可設置於絕緣層(或另一保護層) 112上。絕緣層(或另一保護層) 112可覆蓋接合墊110之部分且覆蓋半導體元件102之第一表面102a。
第一凸塊106為導電柱狀結構(conductive column structure)。第一凸塊106被設置緊鄰於半導體元件102之第一表面102a。圖1中所繪示之第一凸塊106設置於所繪示之接合墊110之曝露部分上。如在圖1中所見，第一凸塊106可包括第一凸塊下金屬化物(under bump metallization，UBM)層1061、第一柱(pillar)1063、第一障壁層1065及第一焊料層1067。在一些實施例中，第一UBM層1061、第一障壁層1045及第一焊料層1047中之一者、兩者或三者自第一凸塊106被省略(例如，第一凸塊為柱)。
第二凸塊108為導電或絕緣柱狀結構。第二凸塊被設置緊鄰於半導體元件102之第一表面102a。第二凸塊108被設置鄰近於保護層104之表面104a。圖1中所繪示之第二凸塊108設置至保護層104之表面104a上。如在圖1中所見，第二凸塊108可包括第二凸塊下金屬化物(UBM)層1081、第二柱1083、第二障壁層1085及第二焊料層1087。在一些實施例中，第二UBM層1081、第二障壁層1085及第二焊料層1087中之一者、兩者或三者自第二凸塊108被省略(例如，第二凸塊為柱)。如上文所描述，接合結構可能會易碎，此係因為在金屬凸塊之模製製程期間常常會產生組裝應力。因此，第二凸塊108被設置鄰近於保護層104之表面104a，以分擔及減少在金屬凸塊之模製製程期間對第一凸塊106產生之組裝應力。因此，在金屬凸塊之模製製程期間，第一凸塊106之破裂或晶片或晶粒之分離情況可以減少或消除，且可對應地改良電連接及可靠性。
如在圖1中所見，第二凸塊108設置於高於第一凸塊106之平面處。因此，若第一凸塊106與第二凸塊108具有相同高度(例如，第一UBM層1061與第二UBM層1081具有相同高度；第一柱1063與第二柱1083具有相同高度；第一障壁層1065與第二障壁層1085具有相同高度；且第一焊料層1067與第二焊料層1087具有相同高度)，則在第一凸塊106之頂部與第二凸塊108之頂部之間將存在高度差。此類高度差可能會造成不良共面性(poor co-planarity)，且又造成不良焊料連接(poor solder connection)，從而導致不良電連接(poor electrical connection)。因此，本案進一步提供，第一凸塊106相比於第二凸塊108應具有較大橫截面表面積，使得在回焊之後的第一焊料層1067之高度S1可大於第二焊料層1087之高度S2，因此，自第一凸塊106之與半導體元件102接觸之表面至第一凸塊106之頂部量測的第一凸塊106之第一高度H1與自第一凸塊106之底部至第二凸塊108之頂部量測的第三高度H3之間的差在焊料回焊之後可被控制為小於15 μm、小於12 μm、小於8 μm，或實質上相同(例如，在製造容限內)。
已意外地發現，若將焊料層設置於具有較大橫截面表面積之柱上，則焊料層將在回焊之後具有較小厚度。此可與焊料層1067、1087與障壁層1065、1085及/或下方柱1063、1083之間的表面張力相關聯。
圖2(a)繪示圖1之半導體裝置之實施例的俯視圖，第一凸塊106 (包括柱1063)定位於半導體元件102上之接合墊110上。第一凸塊106可呈任何形狀，只要第一凸塊106相比於第二凸塊108具有較大橫截面表面積即可。在一些實施例中，第一凸塊106具有圓形或類圓形形狀，或橢圓形或類橢圓形形狀。第一凸塊106具有相對於第一方向之第一長度L1及相對於第二方向之第二長度L2。第一長度L1可長於、短於或等於第二長度L2。圖2(a)中所繪示之第一凸塊106具有橢圓形或類橢圓形形狀，其中第一長度L1對第二長度L2之比率為約1:1.2、約1:1.5、約1:1.7、約1:1.9或約1:2。
圖2(b)繪示圖1之半導體裝置之實施例的俯視圖，第二凸塊108 (包括柱1083)定位於保護層104上。第二凸塊108可呈任何形狀，只要第二凸塊108相比於第一凸塊106具有較小橫截面表面積即可。在一些實施例中，第二凸塊108具有圓形或類圓形形狀，或橢圓形或類橢圓形形狀。第二凸塊108具有相對於第一方向之第三長度L3及相對於第二方向之第四長度L4。第三長度L3可長於、短於或等於第四長度L4。圖2(b)中所繪示之第二凸塊108具有圓形或類圓形形狀，其中第三長度L3對第四長度L4之比率為約1:1。
第一凸塊106可具有與第二凸塊108之形狀不同的形狀，或具有與第二凸塊108之形狀相同或相似的形狀。在一些實施例中，第二凸塊108之第三長度L3在第一凸塊106之第一長度L1與約10 μm之間的差之90%至110%的範圍內(例如，當第一凸塊106具有橢圓形或類橢圓形形狀且第二凸塊108具有圓形或類圓形形狀時)。在一些實施例中，第二凸塊108之第三長度L3在第一長度與0.7之乘積之90%至110%的範圍內(例如，當第一凸塊106具有圓形或類圓形形狀且第二凸塊108具有圓形或類圓形形狀時)。在圖2(a)、圖2(b)及圖1所繪示之實施例中，第一凸塊106具有與第二凸塊108之形狀不同的形狀。第一凸塊106具有橢圓形或類橢圓形形狀且第二凸塊108具有圓形或類圓形形狀。
蓋部比率(cap ratio)可由焊料層1067、1087之厚度對凸塊106、108相對於第一方向之長度L1、L3決定。蓋部比率係取決於設計規格而決定。若焊料層之蓋部比率大於0.8，則焊料層可能會塌陷且無法達成提供有效電連接之目的。另一方面，若焊料層之蓋部比率小於0.3，則焊料層可能會曝露下方柱，此亦無法達成其提供有效電連接之目的。在一些實施例中，第一焊料層1067具有約0.55至約0.65之蓋部比率、約0.57至約0.63之蓋部比率，或約0.58至約0.59之蓋部比率。在一些實施例中，第二焊料層1087具有約0.50至約0.70之蓋部比率、約0.52至約0.68之蓋部比率，或約0.53至約0.66之蓋部比率。在一些實施例中，第一焊料層1067具有0.55至0.65之蓋部比率且第二焊料層1087具有0.50至0.70之蓋部比率(例如，當第一凸塊106具有橢圓形或類橢圓形形狀且第二凸塊108具有圓形或類圓形形狀時)。在一些實施例中，第一焊料層1067具有0.55至0.65之蓋部比率且第二焊料層1087具有0.60至0.80之蓋部比率(例如，當第一凸塊106具有圓形或類圓形形狀且第二凸塊108具有圓形或類圓形形狀時)。
圖3(a)繪示圖1之半導體裝置之實施例的俯視圖，第一凸塊107定位於半導體元件102上之接合墊110上。該半導體裝置與圖1中所繪示之半導體裝置相似，差異為圖3(a)中之第一凸塊107具有圓形或類圓形形狀，其中第一長度L1對第二長度L2之比率為約1:1。
圖3(b)繪示圖1之半導體裝置之實施例的俯視圖，第二凸塊109定位於保護層104上。該半導體裝置及第二凸塊109與圖1中所繪示之半導體裝置及第二凸塊相似，差異為第二凸塊109之第三長度L3在圖3(a)中所繪示之第一凸塊107之第一長度L1與0.7之乘積之90%至110%的範圍內。
圖4繪示根據本案之實施例的半導體裝置的剖面圖。圖4中之半導體裝置400與圖1中之半導體裝置100相似，差異包括保護層404覆蓋接合墊110之部分。保護層404具有或界定一或多個開口404c。每一開口404c對應於各別接合墊110且曝露接合墊110之至少一部分。在圖4之實施例中，第一凸塊106設置於所繪示之接合墊110之曝露部分上及保護層404之部分上。
圖5繪示包括圖1之半導體裝置100之半導體封裝500之實施例的剖面圖。圖5之半導體封裝500包括圖1之半導體裝置100、第二半導體元件101、底填充料524，及用於外部連接之複數個連接元件522。
第二半導體元件101可為晶片、基板、封裝或中介層。第二半導體元件101包括被設置鄰近於第二半導體元件101之表面的第二接合墊518及第三接合墊519。如在圖5中所見，第二接合墊518可經由設置於第二半導體元件101上之導孔520及連接元件522 (例如，接合墊及/或跡線)而電連接至外部環境。第二接合墊518、519可包括例如銅、金、銦、錫、銀、鈀、鋨、銥、釕、鈦、鎂、鋁、鈷、鎳或鋅或其他金屬或金屬合金中之一者或其組合。
半導體裝置100可經由設置於半導體裝置100上之第一凸塊106且經由被設置鄰近於第二半導體元件101之表面的第二接合墊518而電連接至第二半導體元件101。半導體裝置100可經由設置於半導體裝置100上之第二凸塊108且經由設置於第二半導體元件101上之第三接合墊519而熱或絕緣連接至第二半導體元件101。應注意，第三接合墊519可能並非必要的。在一些實施例中，半導體裝置100可經由設置於半導體裝置100上之第二凸塊108且經由被設置鄰近於第二半導體元件101之表面的第三接合墊519而熱連接至第二半導體元件101。在此等實施例中，來自半導體裝置100之熱可通過第二凸塊108及第三接合墊519而耗散。
底填充料524設置於半導體裝置100與第二半導體元件101之間，以保護第一凸塊106免於氧化、濕氣及其他環境條件以滿足封裝應用要求。在一些實施例中，底填充料524設置於半導體裝置100與第二半導體元件101之間，以保護第一凸塊106及第二凸塊108免於氧化、濕氣及其他環境條件。應注意，底填充料524可能並非必要的。
圖6繪示根據本案之實施例的半導體封裝600的剖面圖。半導體封裝600與圖5中所繪示之半導體封裝500相似，惟以下情形除外：第二絕緣層626設置於半導體裝置100與第二半導體元件101之間，以保護第一凸塊106免於氧化、濕氣及其他環境條件以滿足封裝應用要求。在一些實施例中，第二絕緣層626設置於半導體裝置100與第二半導體元件101之間，以保護第一凸塊106及第二凸塊108免於氧化、濕氣及其他環境條件。在此實施例中，第二絕緣層626為包含模製化合物(molding compound)之模製層。
圖7(a)至圖7(f)繪示用於製造諸如圖1之半導體裝置100之半導體裝置的方法。
參看圖7(a)，提供半導體元件(例如，晶粒) 102。半導體元件102包括在半導體元件102之主動表面102a上的至少一個接合墊110。每一半導體元件102可包括基板、一或多個積體電路裝置，及在其中之一或多個上覆互連結構(overlying interconnection structures)。積體電路裝置可包括諸如電晶體之一或多個主動裝置，及/或諸如電阻器、電容器、電感器或其兩者或多者之組合之被動裝置。
絕緣層(或保護層) 112設置於半導體元件102之主動表面102a上。絕緣層112具有或界定一或多個開口112c以曝露接合墊110。在一些實施例中，絕緣層112可覆蓋接合墊110之部分。替代地，絕緣層112完全曝露接合墊110。在一些實施例中，可藉由例如佈線、蝕刻或其他合適製程形成開口112c。在一些實施例中，絕緣層112為包括氧化矽、氮化矽、氧化鎵、氧化鋁、氧化鈧、氧化鋯、氧化鑭、氧化鉿或另一金屬或非金屬氧化物或氮化物之鈍化層。
保護層105被設置鄰近於半導體元件102之主動表面102a。在圖7(a)中所繪示之實施例中，保護層105設置於絕緣層112之表面112a上且覆蓋接合墊110。在一些實施例中，保護層105之厚度為約3 μm至約7 μm，或約4 μm至約7 μm。在一些實施例中，保護層105包括聚醯亞胺或其他合適材料(例如，感光材料)。
參看圖7(b)，形成開口104c以曝露接合墊110以及絕緣層112之部分。如圖7(b)中所展示，開口104c之寬度大於開口112c之寬度。替代地，取決於設計規格，開口104c之寬度可小於或實質上等於開口112c之寬度。在一些實施例中，可藉由光微影、蝕刻、雷射鑽孔或其他合適製程形成開口104c。
參看圖7(c)，將經圖案化光罩714設置鄰近於保護層104之表面104a以曝露接合墊110之部分及保護層104之部分。經圖案化光罩714界定或具有第一開口714c以曝露接合墊110之部分，且界定或具有第二開口714d以曝露保護層104之部分。第一開口714c具有自開口714c之一個側至開口714c之相對側的第一寬度L1，且具有自開口714d之一個側至開口714d之相對側的第二寬度L3，其中第一寬度L1大於第二寬度L3。可例如藉由光微影技術形成經圖案化光罩1401。
參看圖7(d)，在接合墊110之曝露部分上形成第一UBM層1061，且在保護層104之曝露部分上形成第二UBM層1081。第一UBM層1061與第二UBM層1081可被形成為具有實質上相同高度。可例如藉由鍍膜技術形成第一UBM層1061及第二UBM層1081。第一UBM層1061及第二UBM層1081可獨立地包括但不限於金屬、金屬合金、多金屬或多合金堆疊，諸如多合金堆疊，包括例如銅、鎳、釩、鉻與金之組合。
具有第一高度P1之第一柱1063形成於第一UBM層1061上，且具有第二高度P2之第二柱1083形成於第二UBM層1081上。第一高度P1可大於、小於或等於第二高度P2。在圖7(d)中所繪示之實施例中，第一高度P1與第二高度P2實質上相同。可例如藉由鍍膜技術形成第一柱1063及第二柱1083。第一柱1063及第二柱1083可獨立地包括但不限於銅或另一合適金屬或其合金。
參看圖7(e)，在第一柱1063上形成第一障壁層1065且在第二柱1083上形成第二障壁層1085。第一障壁層1065與第二障壁層1085可被形成為具有實質上相同高度。可例如藉由鍍膜技術形成第一障壁層1065及第二障壁層1085。第一障壁層1065及第二障壁層1085可獨立地包括但不限於鎳、銅、其合金，或另一合適金屬或合金。
另外，具有第一高度S1*之第一焊料層1068形成於第一障壁層1065上，且具有第二高度S2*之第二焊料層1088形成於第二障壁層1085上。第一高度S1*可大於、小於或等於第二高度S2*。在圖7(e)中所繪示之實施例中，第一高度S1*與第二高度S2*實質上相同。可例如使用光微影及蝕刻技術形成焊料層1047a。
參看圖7(f)，移除經圖案化光罩714。接著，將第一焊料層1068及第二焊料層1088回焊以形成如圖1中所繪示之半導體裝置100。如在圖7(f)中所見，在焊料回焊之前，自第一UBM層1061與半導體元件102接觸之表面至第一焊料層1068之頂部量測的第一高度H1*小於自第一UBM層1061與半導體元件102接觸之表面之底部至第二焊料層1088之頂部量測的第三高度H3*，此係因為第二柱1083設置於高於第一柱1063之平面上且第一高度S1*與第二高度S2*實質上相同，第一高度P1與第二高度P2實質上相同，且第一UBM層1061連同第一障壁層1065之厚度與第二UBM層1081連同第二障壁層1085之厚度實質上相同。
圖8(a)至圖8(b)繪示用於製造諸如圖5之半導體裝置500之半導體封裝的方法。
參看圖8(a)，提供半導體裝置100及半導體元件101。圖8(a)之半導體裝置100與圖1之半導體裝置相同，且具有第一凸塊106及第二凸塊108。第一凸塊106具有相對於第一方向之第一長度L1，且第二凸塊108具有相對於第一方向之第三長度L3。
圖8(a)之第二半導體元件101與圖5之第二半導體元件101相同，且具有被設置鄰近於第二半導體元件101之表面的第二接合墊518及第三接合墊519。第一接合墊518對應於第一柱106且具有第一寬度W1，其中第一寬度W1大於或等於第一凸塊106之第一長度L1。第二接合墊519對應於第二柱108且具有第二寬度W2，其中第二寬度W2大於或等於第二凸塊108之第二長度L2。當第一長度L1大於第二長度L2時，第一寬度W1大於第二寬度W2。
參看圖8(b)，將半導體裝置100之第一柱106接合至第二半導體元件101之第一接合墊518，且將半導體裝置100之第二柱108接合至第二半導體元件101之第二接合墊519。可藉由熱壓縮接合來形成接合製程。接著，將底填充料524設置於半導體裝置100與第二半導體元件101之間以形成如圖5中所繪示之半導體封裝500。
如本文中所使用且不加以另外定義，術語「實質上」、「實質的」、「大約」及「約」用以描述及考慮小的變化。當結合事件或情境而使用時，該等術語可涵蓋該事件或情境精確地發生之例項，以及該事件或情境極近似地發生之例項。舉例而言，當結合數值而使用時，該等術語可涵蓋小於或等於該數值之±10%的變化範圍，諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%，或小於或等於±0.05%。作為另一實例，若線或平面之峰部或凹陷不大於5 μm、不大於1 μm或不大於0.5 μm，則線或平面可為實質上平坦的。
儘管本發明已參考其特定實施例予以描述及繪示，但此等描述及繪示並非限制性的。熟習此項技術者應理解，在不脫離如由所附申請專利範圍所界定的本發明之真實精神及範疇的情況下，可作出各種改變且可取代等效者。繪示可能未必按比例繪製。歸因於製造製程及容限，本發明中之藝術再現與實際設備之間可存在區別。本發明可存在未特定地繪示之其他實施例。應將本說明書及圖式視為說明性而非限制性的。可作出修改以使特定情形、材料、物質組成、方法或製程適應於本發明之目標、精神及範疇。所有此類修改均意欲在本文所附之申請專利範圍的範疇內。儘管已參考按特定次序執行之特定操作描述了本文中所揭示之方法，但應理解，可在不脫離本發明之教示的情況下對此等操作進行組合、細分或重新排序以形成等效方法。因此，除非本文中有特定指示，否則操作之次序及分組並非限制。
100:半導體裝置 101:半導體元件 102:半導體元件 102a:第一表面/主動表面 102b:第二表面 104:保護層 104a:表面 104c:開口 105:保護層 106:第一凸塊 107:第一凸塊 108:第二凸塊 109:第二凸塊 110:接合墊 112:絕緣層 112a:開口 112c:開口 400:半導體裝置 404:保護層 404c:開口 500:半導體封裝 518:第二接合墊 519:第三接合墊 520:導孔 522:連接元件 524:底填充料 600:半導體封裝 626:第二絕緣層 714:經圖案化光罩 714c:第一開口 714d:第二開口 1045:第一障壁層 1047:第一焊料層 1047a:焊料層 1061:第一凸塊下金屬化物(UBM)層 1063:第一焊料層 1065:第一障壁層 1067:第一焊料層 1068:第一焊料層 1081:第二凸塊下金屬化物(UBM)層 1083:第二柱 1085:第二障壁層 1087:第二焊料層 1088:第二焊料層 1401:經圖案化光罩 H1:第一高度 H1*:第一高度 H3:第三高度 H3*:第三高度 L1:第一長度 L2:第二長度 L3:第三長度 L4:第四長度 P1:第一高度 P2:第二高度 S1:高度 S1*:第一高度 S2:高度 S2*:第二高度 W1:第一寬度 W2:第二寬度
圖1繪示根據本案之實施例的半導體裝置的剖面圖。
圖2(a)繪示根據本案之實施例的圖1中所繪示之半導體裝置的俯視圖。
圖2(b)繪示根據本案之實施例的圖1中所繪示之半導體裝置的俯視圖。
圖3(a)繪示根據本案之實施例的圖1中所繪示之半導體裝置的俯視圖。
圖3(b)繪示根據本案之實施例的圖1中所繪示之半導體裝置的俯視圖。
圖4繪示根據本案之實施例的半導體裝置的剖面圖。
圖5繪示根據本案之實施例的半導體封裝之實施例的剖面圖。
圖6繪示根據本案之實施例的半導體封裝之實施例的剖面圖。
圖7(a)至圖7(f)繪示根據本案之實施例的製造方法。
圖8(a)至圖8(b)繪示根據本案之實施例的製造方法。
100:半導體裝置
102:半導體元件
102a:第一表面/主動表面
102b:第二表面
104:保護層
104a:表面
104c:開口
106:第一凸塊
108:第二凸塊
110:接合墊
112:絕緣層
1061:第一凸塊下金屬化物(UBM)層
1063:第一焊料層
1065:第一障壁層
1067:第一焊料層
1081:第二凸塊下金屬化物(UBM)層
1083:第二柱
1085:第二障壁層
1087:第二焊料層
H1:第一高度
H3:第三高度
L1:第一長度
L3:第三長度
P1:第一高度
P2:第二高度
S1:高度
S2:高度

Claims (22)

  1. 一種半導體裝置，其包含： 半導體元件； 保護層，其設置鄰近於該半導體元件之表面，該保護層界定開口以曝露該半導體元件； 第一凸塊，其設置於該半導體元件上；及 第二凸塊，其設置至該保護層之表面上， 其中該第一凸塊相比於該第二凸塊具有較大橫截面表面積。
  2. 如請求項1之半導體裝置，其中該第一凸塊具有與該第二凸塊之形狀不同的形狀。
  3. 如請求項2之半導體裝置，其中該第一凸塊具有橢圓形或類橢圓形形狀且該第二凸塊具有圓形或類圓形形狀。
  4. 如請求項1之半導體裝置，其中該第一凸塊具有與該第二凸塊之形狀相同或相似的形狀。
  5. 如請求項4之半導體裝置，其中該第一凸塊具有圓形或類圓形形狀且該第二凸塊具有圓形或類圓形形狀。
  6. 如請求項1之半導體裝置，其中該第一凸塊具有相對於第一方向之第一長度及相對於第二方向之第二長度，且該第二凸塊具有相對於該第一方向之第三長度及相對於該第二方向之第四長度，其中該第一長度對該第二長度之比率為約1且該第三長度對該第四長度之比率為約1。
  7. 如請求項1之半導體裝置，其中該第一凸塊包含第一焊料層且該第二凸塊包含第二焊料層，其中該第一焊料層具有0.55至0.65之蓋部比率且該第二焊料層具有0.50至0.70之蓋部比率，其中該蓋部比率係由該焊料層之厚度對該凸塊相對於第一方向之長度決定。
  8. 如請求項1之半導體裝置，其中該第一凸塊包含第一焊料層且該第二凸塊包含第二焊料層，其中該第一焊料層具有0.55至0.65之蓋部比率且該第二焊料層具有0.60至0.80之蓋部比率，其中該蓋部比率係由該焊料層之厚度對該凸塊相對於第一方向之長度決定。
  9. 如請求項1之半導體裝置，其中該第一凸塊具有相對於第一方向之第一長度及相對於第二方向之第二長度，且該第二凸塊具有相對於該第一方向之第三長度及相對於該第二方向之第四長度，其中該第三長度在該第一長度與約10 μm之間的差之90%至110%的範圍內。
  10. 如請求項1之半導體裝置，其中該第一凸塊具有相對於第一方向之第一長度及相對於第二方向之第二長度，且該第二凸塊具有相對於該第一方向之第三長度及相對於該第二方向之第四長度，其中該第三長度在該第一長度與0.7之乘積之90%至110%的範圍內。
  11. 如請求項1之半導體裝置，其中自該第一凸塊與該半導體元件接觸之表面至該第一凸塊之頂部量測的第一高度與自該第一凸塊與該半導體元件接觸之表面至該第二凸塊之頂部量測的第二高度實質上相同。
  12. 如請求項1之半導體裝置，其中該第一凸塊之頂部與該第二凸塊之頂部之間的差小於8 μm。
  13. 如請求項1之半導體裝置，其中該半導體元件進一步包含設置鄰近於該半導體元件之表面的接合墊，且該第一凸塊設置於該接合墊上。
  14. 如請求項1之半導體裝置，其中該第一凸塊及該第二凸塊為柱。
  15. 一種半導體裝置，其包含： 半導體元件； 第一凸塊，其設置緊鄰於該半導體元件之表面，其中該第一凸塊包括第一柱及第一焊料；及 第二凸塊，其設置緊鄰於該半導體元件之該表面，其中該第二凸塊包括第二柱及第二焊料； 其中該第一柱與該第二柱具有實質上相同高度，且該第一焊料與該第二焊料不具有實質上相同高度， 其中該第一凸塊相比於該第二凸塊具有較大橫截面表面積。
  16. 如請求項15之半導體裝置，其中該第一凸塊之高度與自該第一凸塊之底部至該第二凸塊之頂部量測的高度實質上相同。
  17. 如請求項15之半導體裝置，其中該第一凸塊之頂部與該第二凸塊之頂部之間的差小於8 μm。
  18. 如請求項15之半導體裝置，其中該第一凸塊具有沿著第一方向的第一長度及沿著第二方向的第二長度，且該第二凸塊具有沿著該第一方向的第三長度及沿著該第二方向的第四長度，其中該第一長度對該第二長度之比率為約1且該第三長度對該第四長度之比率為約1。
  19. 如請求項15之半導體裝置，其中該第一凸塊具有相對於第一方向之第一長度及相對於第二方向之第二長度，且該第二凸塊具有相對於該第一方向之第三長度及相對於該第二方向之第四長度，其中該第三長度在該第一長度與約10 μm之間的差之90%至110%的範圍內。
  20. 如請求項15之半導體裝置，其中該第一凸塊具有相對於第一方向之第一長度及相對於第二方向之第二長度，且該第二凸塊具有相對於該第一方向之第三長度及相對於該第二方向之第四長度，其中該第三長度在該第一長度與0.7之乘積之90%至110%的範圍內。
  21. 一種半導體封裝，其包含： 半導體裝置，其包含： 第一半導體元件； 保護層，其設置鄰近於該第一半導體元件之表面，該保護層界定開口以曝露該第一半導體元件； 第一凸塊，其設置於該第一半導體元件上；及 第二凸塊，其設置至該保護層之表面上， 其中該第一凸塊相比於該第二凸塊具有較大橫截面表面積；及 第二半導體元件，其包含： 第一接合墊，其設置鄰近於該第二半導體元件之表面且對應於該第一凸塊；其中該第一凸塊接合至該第一接合墊。
  22. 如請求項21之半導體封裝，其中該第二半導體元件進一步包含設置鄰近於該第二半導體元件之該表面且對應於該第二凸塊的第二接合墊，該第一接合墊具備具有第一寬度W1之開口且該第二接合墊具備具有第二寬度W2之開口，且該第一寬度W1大於該第二寬度W2。
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