TW202014536A - 用於襯墊鈍化及黏著性改善的金屬襯墊之鋅化及摻雜 - Google Patents
用於襯墊鈍化及黏著性改善的金屬襯墊之鋅化及摻雜 Download PDFInfo
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- TW202014536A TW202014536A TW108123063A TW108123063A TW202014536A TW 202014536 A TW202014536 A TW 202014536A TW 108123063 A TW108123063 A TW 108123063A TW 108123063 A TW108123063 A TW 108123063A TW 202014536 A TW202014536 A TW 202014536A
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- zinc
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- 229910052751 metal Inorganic materials 0.000 title claims description 56
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- 239000010941 cobalt Substances 0.000 claims description 5
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Abstract
提供用於在基材的特徵部中形成自成形障壁之方法,包括以下操作:將金屬襯墊沉積於基材的特徵部中,所述金屬襯墊沉積在基材之電介質上方;將含鋅前驅物沉積於金屬襯墊上方;施行基材的熱浸泡;將含鋅前驅物之沉積和基材的熱浸泡重複預定之循環次數;其中所述方法在金屬襯墊和電介質之間的界面形成含鋅之障壁層。
Description
本發明係相關於在基材的特徵部中形成自成形障壁。
用於創建摻雜銅互連部的當前技術主要係經由物理氣相沉積(PVD)。藉由PVD沉積二個感興趣之主要摻雜銅(Cu)物種的CuMn(摻雜錳之銅)和CuAl(摻雜鋁的銅)。對於具有較小臨界尺寸(CD)和較大縱橫比(AR)之未來技術節點,這不是可擴縮的技術。設計用於高AR和狹窄結構之CuMn或CuAl的原子層沉積(ALD)共沉積製程非常具有挑戰性。再者,Mn和Al摻雜劑亦可顯著地提高Cu線之電阻率(分別為2.8和1.25 uohm-cm / at %)。因此,亦期望帶來較少的電阻損失之替代摻雜劑。
而且,藉由電沉積對諸如Co或Ru之類的襯墊之直接Cu金屬化一直是生產線後端(BEOL)的挑戰。在外來基材(例如襯墊材料)上直接電鍍需要寬廣之表面預處理,以減少天然金屬氧化物。以別的方式,在上述襯墊上之Cu成核性不佳。其結果是,表面處理和排隊時間管理對於將來互連部的金屬化至關重要,因為這些互連部需要在薄襯墊上直接電鍍。
在此情況下,產生本揭示內容之實施例。
由於諸多理由(例如,自成形的障壁、電遷移之改良),人們期望對互連金屬進行摻雜。按照本揭示內容的實施例,提供自上向下摻雜互連金屬之新穎方法。這涉及藉由完善的技術(例如,CVD、ALD、PVD等)在互連結構上方沉積保形之金屬氧化物層。然後藉由熱處理將互連金屬上的金屬氧化物選擇性地還原為元素金屬。還原之金屬擴散進入互連金屬,從而提供摻雜的互連部。
同樣,保形之氧化鋅層用於保護襯墊免於氧化。在還原環境中熱處理之後,ZnO還原為金屬鋅,其後續遷移至鋅/介電界面,從而提供黏著性和可能的障壁性質。襯墊層中之未反應的金屬鋅之一部分藉由優先形成氧化鋅層而當暴露於空氣時保護襯墊免受氧化。
在一些實施例中,提供用於在基材的特徵部中形成自成形障壁之方法,包括以下操作:將金屬襯墊沉積於基材的特徵部中,所述金屬襯墊沉積在基材之電介質上方;將含鋅前驅物沉積於金屬襯墊上方;施行基材的熱浸泡;將含鋅前驅物之沉積和基材的熱浸泡重複預定之循環次數;其中所述方法在金屬襯墊和電介質之間的界面形成含鋅之障壁層。
於一些實施例中,金屬襯墊由釕所組成。
在一些實施例中,金屬襯墊由鈷所組成。
於一些實施例中,特徵部為通孔。
在一些實施例中,特徵部為互連部。
於一些實施例中,含鋅前驅物為二乙基鋅。
在一些實施例中,沉積所述含鋅前驅物藉由化學氣相沉積製程來施行。
於一些實施例中,熱浸泡在約180至400℃的溫度下施行。
於一些實施例中,所述方法更包括:在重複預定循環次數之後,接著將導體沉積於基材的特徵部中。
在一些實施例中,導體為銅。
於一些實施例中,提供用於在基材之特徵部中形成自成形的障壁之方法,包括以下操作:將金屬襯墊沉積於基材的特徵部中,所述金屬襯墊沉積在基材之電介質上方;將含銦前驅物沉積於金屬襯墊上方;施行基材的熱浸泡;將含銦前驅物之沉積和基材的熱浸泡重複預定之循環次數;其中所述方法在金屬襯墊和電介質之間的界面形成含銦之障壁層。
於一些實施例中,金屬襯墊由釕所組成。
在一些實施例中,金屬襯墊由鈷所組成。
於一些實施例中,特徵部為通孔。
在一些實施例中,特徵部為互連部。
於一些實施例中,含銦前驅物為三甲基銦。
在一些實施例中,沉積所述含銦前驅物藉由化學氣相沉積製程來施行。
於一些實施例中,熱浸泡在約180至400℃的溫度下施行。
於一些實施例中,所述方法更包括:在重複預定的循環次數之後,接著將導體沉積於基材的特徵部中。
在一些實施例中,導體為銅。
通過以下結合附圖之詳細敘述,本揭示內容的其他態樣和優點將變得顯而易見,所述附圖當作範例地說明本揭示內容之原理。
在以下敘述中,提出許多具體細節以便提供示範實施例之透徹理解。然而,對於本領域的技術人員將顯而易見的是,可在沒有這些具體細節之一些的情況下實踐示範實施例。於其他情況下,如果已經眾所周知,則沒有詳細敘述製程操作和實施例細節。
如本文中所使用,「大約」和「約略」等詞意指特定參數可在合理之公差內變動,例如於一些實施例中為±10%、在一些實施例中為±15%、或於一些實施例中為±20%。
本揭示內容的實施例提供用於摻雜金屬互連部之方法,包括藉由無電共沉積、藉由金屬氧化物的選擇性還原、及藉由熱解離。
自上而下之摻雜方法消除在高AR結構中用於CuX(在此X =摻雜元素)的共沉積製程之需要。於金屬化之後,可能經過以下方式將摻雜元素驅入互連金屬:(1)金屬氧化物層的沉積,在此金屬為摻雜元素(例如,諸如用於Al2O3、ZnO、MnO2、SnO2、和In2O3之金屬氧化物製程為完善的(例如ALD、CVD或PVD);(2)經過在高溫下用熱解離之前驅物(例如,可能是ALD前驅物)來將互連金屬施劑。再者,經過當前敘述的自上而下之摻雜方法,諸如Zn和In的替代摻雜元素是可能的,它們之電阻較小(分別為0.25和1.1 uohm-cm / at %)。
此方法能夠摻雜Cu,用於產生自成形的障壁(SFB),並允許將電遷移(EM)改進到較小的尺寸,這是目前無法以PVD實施的。由於障壁縮放停止(電阻率增加)和Jmax(最大電流)增加(EM故障),將來之技術節點將需要此類SFB和EM升壓器。
當前敘述的概念適用於諸如ZnO、SnO2、InO2、和MnO2 (ALD和PVD)的金屬氧化物。當作範例但沒限制,考慮ZnO作為金屬氧化物,然後在熱處理之後,將ZnO選擇性地還原為Cu和Ru上的金屬Zn,其擴散進入於下面之金屬,而建立摻雜的及互連部。
直接在諸如Ru或Co的襯墊上電鍍之當前技術涉及於> 300°C下進行表面預處理,以還原天然的金屬氧化物。後續之排隊時間管理對於防止襯墊再氧化至關重要。這是一項巨大的挑戰,因為外來基材上之電化學成核性對表面條件和狀態極為敏感。
鋅化係用於金屬化鋁的已知方法。在此製程中,金屬鋁於非常鹼性之溶液中與Zn(OH)2-反應,以將鋅沉積在鋁上。此鋅層防止鋁再次氧化,並能夠讓鋁金屬化。
然而,於本揭示內容的實施例中,「鋅化」係藉由ALD或CVD製程後續進行熱處理來提供。習知之「鋅化」中所使用的鹼性製程對使用於半導體製造係不實用的。
沉積在諸如Ru、Co、Mo之襯墊材料上的保形氧化鋅可經由在還原環境中之熱處理而還原為金屬鋅。還原的鋅可(1)在襯墊/金屬界面形成矽酸鋅化合物,從而改善黏著性;(2)保護襯墊在暴露至周遭條件時免受再次氧化;(3)藉由「填充」襯墊的晶界並經過形成界面化合物來改善障壁性質。
數個其他金屬氧化物可顯示類似之性質-SnO2、In2O3、GeO2、FexOy、MnO2、CoOx。
圖1A說明隨著CD尺寸縮小以啟用下一代技術節點而發生的問題。隨著特徵部尺寸縮小,相對障壁層和襯墊層,導電面積會有所損失,以致障壁層和襯墊層之高電阻將占主導地位。於如所示的導體線和通孔之情況中,導體的橫截面被襯墊層和障壁層擠出,且因此當前之襯墊/障壁配置將無法針對未來的技術節點微縮。同樣,通孔電阻正成為支配電阻,例如,在1D圖案化中,因除了縮小之導體橫截面以外,當前的襯墊層和障壁層產生電阻式接觸。
圖1B說明用於按照揭示內容之實施例形成自成形的障壁層之製程。在參考標號100處,顯示基材中的蝕刻互連特徵部之橫截面。所述特徵部包括通孔108及溝道106。特徵部於電介質中圖案化,在一些實施例中,電介質可為氧化物,諸如SiO2或低k電介質。下面的導體(Cu)線104處於通孔之底部。如在參考標號110所示,採用無電沉積製程來沉積由摻雜的銅物質CuX(其中X為摻雜劑)所組成的通孔預填充物(VPF)112。於諸多實施例中,X可為Zn、In、Sn、或其他元素,所述元素可為藉由無電沉積製程與諸如銅之導體共沉積,並提供如本文所述的自成形障壁或黏附層。
然後,在還原環境中施行熱處理。如於參考標號112所示,這造成及/或加速摻雜劑X向通孔之側壁的遷移,在此其形成自成形之障壁層114。自成形的障壁層114既改善對側壁之黏著性並防止電遷移。據信摻雜劑X與氧化物反應,以形成複合的矽酸鹽。應當理解,當摻雜劑已遷移至側壁時,通孔預填充物112現在大部分是純銅。
於生成自成形的障壁層114之後,接著可如在參考標號116所示地施行標準的金屬化製程,包括例如障壁層/襯墊層118之沉積,後續沉積塊狀導體120。於另一實施例中,僅沉積襯墊,並可施行另一摻雜的銅填充,後續進行退火以形成類似於相對於通孔預填充物所敘述之自成形障壁。
前述製程具有數個優點。隨著通孔的導體部分之橫截面積最大化,通孔電阻減小,且再者,由於業已填充通孔,此製程能夠對減小縱橫比的溝道進行電鍍(ECP)Cu。這是有利的,因為它可實施更高縱橫比之通孔。過去,溝道和通孔的縱橫比不能超過約4:1(高度對寬度)。但是,通過本文所述之此製程,現在可將溝道的填充與通孔之填充解耦,且從而可創建遠加更高的通孔,這將降低中間層之間的電容。亦可能具有更高之溝道,儘管它受縱橫比所限制,但是現在其係可能具有更高的溝道,因為填充製程(例如ECP)不需要向下填充進入通孔。故此製程減少通孔電阻及允許減少之縱橫比,從而延長電鍍製程的可行性。
圖2示範按照揭示內容之實施例在毯覆基材上以無電銅銦(Cu-In)的界面層形成。如在參考標號200所示,基材表面最初由在熱氧化物層202上的Cu層204(例如5 nm厚度)所組成,其當作範例但沒限制地模仿通孔之界面結構。然後,如於參考標記206所示,藉由無電沉積在Cu層204上方來沉積Cu-In層208(例如~100 nm厚度),並藉由無電沉積於Cu-In層208上方來沉積Cu層210(例如~40 nm厚度)。
形成氣體退火在350°C下施行。所得膜結構於參考標號212顯出。大多數銦遷移至與氧化物層202的界面,於此據信其至少一部分形成氧化銦層214(例如In2O3)。包括二層208和210之剩餘的塊狀Cu層216大部分是純銅,儘管它可含有痕量之銦。大多數銦已遷移至氧化物界面,且如果暴露至氧氣(諸如當暴露至大氣條件時可能發生),亦可能遷移至在結構頂部的空氣界面。
為了進行黏著性測試之目的,如於參考標號218所示,藉由PVD在塊狀銅層216上方沉積額外之厚銅層220(例如,~400 nm厚度)。於參考標號222處,顯示按照上面製程所處理之基材,後續進行剝離測試以測試黏著性。如所示,表面結構的含銅層在剝離試驗之後大部分保持完好無損,指示源自氧化銦層214的很強之黏著性。
於毯覆基材上施行控制製程。如在參考標號230所示,藉由無電沉積於Cu層204上方來沉積Cu層232(~160 nm厚度)。在350℃下施行相同的形成氣體退火,導致於氧化物層202上方形成塊狀銅層236。藉由PVD在Cu層236上方沉積厚銅層238。如於參考標號242所示,使用剝離測試來測試所得之基材。如可看出,含銅層從基材上分層,與上述含銦結構的黏著性相比指示相對不佳之黏著性。
在參考標號250,透射電子顯微鏡(TEM)影像顯示如所敘述於形成氣體退火之後按參考標號212處理的基材之一部份的橫截面,包括銅至氧化物界面之區域,現在所述區域包括銦。藉由電子繞射光譜(EDS)研究一小節252,並於參考標號260顯示EDS圖解。如可看出,銦(參考標號264)坐落於銅(參考標號266)和氧化矽(262)之間。曲線圖270說明作為深度的函數之Cu(曲線272)、In(曲線274)、和Si(曲線276)的原子百分比。再者,在從銅到氧化矽之過渡中看到銦。
圖3顯示按照揭示內容的實施例藉由銅-銦之無電沉積所施行的通孔填充物之諸多影像。影像300係藉由無電沉積進行的通孔填充之後的具有圖案化溝道和通孔之基材表面的自上向下掃描隧道式顯微鏡(STM)影像。在形成氣體下於200℃使基材遭受5分鐘之預清潔。銅銦的無電沉積施行40秒,隨後於350℃進行20分鐘的形成氣體退火。影像302顯示影像300之一部分的放大視圖。影像308(以nm顯示通孔填充物之尺寸),310和312是橫截面TEM影像,顯示按照影像300/302在通孔填充之後的通孔結構302。
影像304是與上述類似處理之基材的自上向下掃描隧道顯微鏡(STM)影像,但是銅銦之無電沉積施行達90秒的更長時間。影像306顯示影像304之一部分的放大視圖。影像314、316和318係橫截面TEM影像,按照影像304/306顯示於通孔填充之後的通孔結構。如可看出,通孔填充之高度和溢出寬度增加超過40秒填充的高度和溢出寬度。
應當理解,用於無電沉積銅銦之電解質沉積溶液將包括銅和銦來源兩者,諸如銅和銦的氯化物鹽(例如,InCl3、CuCl2)。在一些實施例中,所述溶液包括作為還原劑之鈷。於一些實施例中,所述溶液包括作為配體的乙二胺或另一含胺分子。在一些實施例中,於約5至10之pH範圍中和在約20至80℃的溫度下施行無電沉積。於一些實施例中,pH在約7至9的範圍中。於一些實施例中,溫度為室溫,或接近或約25℃。
圖4說明按照揭示內容之實施例的諸多退火條件及在基材之通孔結構中的銦之所得分佈。按照上述技術,用銅銦對通孔進行無電填充(形成通孔預填充(VPF))達90秒,並施行不同的退火方法。影像400和404顯示如所示不同退火條件之後的通孔填充之TEM橫截面。對應的EDS圖解影像402和406顯示在TEM橫截面下方,指示銦之存在和位置。
如可看出,通過二階段退火(在還原環境,例如形成氣體中),包括較短的較低溫度退火、和後續之較長較高溫度退火,如藉由EDS影像406所示,顯著改善對於通孔預填充界面(具有氧化物和空氣)的銦偏析。銦向通孔預填充界面之遷移,與僅對其施行一次低溫或高溫退火的其他樣品相比,明顯地更有區別的。
因此,於一些實施例中,利用二階段退火,其由在較低溫度(例如,於約150至200℃之範圍中)的第一退火、隨後在較高溫度(例如,於約300至400°C之範圍中)的第二退火所組成。在一些實施例中,第一退火具有較短之持續時間(例如,於約1至5分鐘的範圍中,反之第二退火具有較長的持續時間(例如,在約10至30分鐘之範圍中)。
圖5顯示EDS圖解影像500,說明按照揭示內容的實施例在如上所述的二階段退火之後的通孔預填充中之銦和銅的存在。如所示,銦集中於通孔預填充結構之外緣,而使通孔預填充物本身大部分為純銅。
如本揭示內容中所敘述的,可對導體金屬(銅)進行摻雜和退火,以達成自成形之障壁。應注意的,任何電負性之摻雜劑金屬(例如,Zn、In、Sn)應向氧化物側壁遷移並對側壁中的氧化劑淬火,並藉此防止銅被氧化。然而,如何具體摻雜某些金屬仍然是一項挑戰。如上所述之無電沉積對於提供選擇性沉積(例如在通孔中)是有利的。然而,儘管可相當容易地無電沉積銅,但是取決於摻雜劑,無電摻雜之銅可為具有挑戰性。例如,像鋅和錳的高電負性元素可為難以經由無電沉積與銅共沉積。
鑑於前述者,提供達成自成形障壁所需之金屬的另一方式係採用氣相製程,以從結構(例如,經由通孔預填充結構)之頂部注入金屬(例如Zn、In、Sn、Mn)。因此,在一些實施例中,可沉積保形的氧化鋅層,然後還原成金屬鋅,其擴散進入導體金屬。最近已發現之另一方式係使用CVD類的製程進行直接熱解離。例如,已發現可將鋅前驅物分配至被加熱的晶圓上,且鋅前驅物選擇性地分解在晶圓之金屬部分上,並擴散進入金屬。
圖6說明按照揭示內容的實施例之用於經由金屬氧化物層的退火來產生自成形障壁之製程。如在參考標號600所示,顯示基材表面中的圖案化特徵部,包括於氧化物602中蝕刻之通孔606和溝道608,以形成至下面的導體線604(例如,銅)之互連部。如在參考標記610所示,採用無電沉積製程來沉積通孔預填充物612(例如,銅)。無電沉積製程係有利的,因為其對於導體線604是選擇性的。
如在參考標記614所示,藉由諸如ALD、PVD、或CVD之保形沉積製程將保形金屬氧化物層616(例如ZnO、MnO2、SnO2、In2O3)沉積於溝道608中。然後在還原環境中施行熱處理(或退火)。於一些實施例中,熱處理在約200至350℃的範圍中。於一些實施例中,還原環境藉由形成氣體環境所界定。熱處理造成坐落在通孔預填充物612上方之金屬氧化物選擇性地分解,以致金屬擴散進入於下面的通孔預填充物中,並進一步遷移至與通孔之氧化物側壁的界面,從而在界面處形成自成形之障壁層620,所述障壁層620改善黏著性並抑制電遷移。
影像630係使用沉積於Cu通孔預填充物上方的氧化鋅膜,按照上述方法處理通孔結構之TEM橫截面影像。如所示,在熱處理之後,通孔預填充物本身上沒有ZnO,因為ZnO已還原為金屬Zn,然後已擴散進入Cu通孔預填充物。Zn可遷移至通孔側壁到銅和氧化物之間的界面,並形成自成形障壁。如上所述,自成形障壁層可部分為由於在側壁形成矽酸鋅。
於一些實施例中,熱處理亦造成剩餘之氧化鋅層616(其不在通孔預填充物612上方)形成矽酸鋅(例如,沿著溝道608的側壁)。這是有利的,因為其經過相同製程沿著溝道和通孔壁兩者達成連續之障壁。再者,可施行溝道的大塊填充(例如,藉由對銅提供選擇性之無電沉積),並使導體的橫截面積最大化,且避免電阻性接觸,所有這些都改善電氣性能。
於一些實施例中,用例如水或酸移除剩餘之氧化鋅層616(其不在通孔預填充物612上方)。
圖7顯示按照上述製程處理的通孔結構之特色,按照揭示內容的實施例示範氧化鋅和鋅擴散進入通孔預填充物中。尤其是,藉由ALD且後續藉由350℃形成氣體退火來沉積氧化鋅層。
EDS圖解影像700顯示Zn、O和N之存在(於如所示結構中包括SiN膜)。如可看出,儘管鋅有一些擴散進入側壁氧化物中,但是鋅主要沿著側壁於介電氧化物的氧上方。顯著地是,鋅不存在通孔預填充物上方或通孔預填充物中(超過痕量)。氧化鋅層已消失,且鋅已擴散經過銅通孔預填充物。代替地,鋅存在於銅和SiN之間的界面。
曲線702顯示作為深度之函數的O、Cu、Zn、和N之原子百分比,並與下面的銅線平行。曲線704、706、708和710分別顯示N、Cu、O、和Zn之原子百分比。
曲線712顯示作為深度的函數之N、O、Cu、和Zn的原子百分比,並與下面之銅線垂直。曲線714、716、718和720分別顯示O、Cu、Zn、和N的原子百分比。
曲線722顯示作為整個銅至氮化物界面之深度的函數之Si、Cu、Zn、和N的原子百分比。曲線724、726、728和730分別顯示Si、Cu、Zn、和N之原子百分比。
由前文可看出,Cu中的Zn濃度為約6至8原子百分比,其隨深度而減少。與In類似,Zn亦累積在Cu / SiN界面。同樣,有一些Zn前驅物滲透進入多孔低k電介質中。
圖8A顯示按照揭示內容之實施例的用於摻雜ALD前驅物之製程。在參考標記800,顯示壓力對時間的曲線,說明ALD製程。ALD製程由交替之30 ms的二乙基鋅(DEZ)脈衝(參考標號802)和15 ms之水脈衝(參考標號806)所組成,相隔20秒的清除時間(參考標號804),並在175 ℃之製程溫度下施行。
TEM影像810顯示於沒有後退火操作的情況下,在上述ALD製程的50個循環之後形成的通孔預填充物之尺寸和ZnO層的厚度(以nm為單位)。對應之EDS圖解影像812顯示鋅經由預填充擴散進入銅中。這亦藉由作為通過通孔預填充物的深度之函數的鋅和銅之原子百分比的曲線814所顯示。曲線816和818分別顯示鋅和銅之原子百分比。如可看出,鋅存在於通孔預填充結構的上部中,因此指示金屬鋅已從DEZ解離並擴散進入銅中。
如可看出,諸如DEZ之ALD前驅物可於金屬存在下並以足夠的溫度(例如約150至200℃及以上)拆散。在當前情況下,銅充當將DEZ解離成金屬鋅之催化劑。
鑑於這些發現,提供利用ALD前驅物的此自發熱離解之CVD摻雜製程。曲線820顯示CVD摻雜製程的壓力與時間之關係,其中施行含金屬的ALD前驅物(例如DEZ)之劑量步驟(參考標號822),後續施行熱浸泡(參考標號824)。製程在相當高的溫度施行,所述溫度足以當沉積於金屬通孔預填充物時達成ALD前驅物之熱解離。在一些實施例中,製程溫度於約175至300℃的範圍中。重複此循環,直到所期望數量之摻雜劑金屬擴散進入通孔預填充物中。
在參考標記830,顯示蝕刻的互連結構,包括於電介質832中蝕刻之通孔836和溝道838,以形成與下面的Cu線834之連接。施行無電沉積製程以在通孔836中選擇性沉積Cu通孔預填充物842,如於參考標號840所示。然後,藉由在如上所述的重複循環中進行含金屬的ALD前驅物(例如DEZ)施劑、並允許其浸泡達預定時間來摻雜所述通孔預填充物842。DEZ熱解離成銅通孔預填充物上之金屬鋅,並擴散進入銅。於足夠的溫度下,鋅可擴散進入銅,且亦遷移至與電介質之界面,以形成如先前所述的自成形障壁846。
應當理解,可能需要足夠高之溫度以在電介質界面形成矽酸鹽。於一些實施例中,在第一較低溫度(例如,約175至300℃)下施行摻雜製程,且接著於第二較高溫度下隨之進行後退火製程,以促進矽酸鹽形成(例如,約300至400℃)。再者,應注意,鋅亦可遷移至下面的銅線834和電介質832之間的界面(或當存在時可能為SiN層)。因此,自成形之障壁可不僅增強通孔區域的黏著性,而且還可增強下面的導體之黏著性。
上述製程的優點是不需要氧化劑。將任何氧化劑與暴露之電介質一起使用能建立更多的缺陷部位並損壞電介質,故期望的是不將水或臭氧與暴露之電介質一起使用,且因此以本製程更好地維持電介質完整性。
注意,如於上述ALD製程中,在沒有水脈衝的情況下,發現在氧化物上檢測不到太多鋅,並因此,鋅前驅物對氧化物沒有良好之黏著性。
儘管上面已具體敘述鋅的摻雜和鋅前驅物DEZ之使用,但是將理解,可替代以其他元素和對應的前驅物。於一些實施例中,二甲基鋅用作鋅前驅物。在諸多實施例中,可應用其他有機金屬ALD前驅物,諸如用於Zn、In(例如三甲基銦)、Sn、或Mn作為摻雜劑金屬。
圖8B概念性地說明按照揭示內容之實施例的用於自成形障壁(SFB)形成之Ru襯墊的摻雜製程。如在參考標號850所示,於電介質852中形成之通孔(例如SiO2,低k)已鍍有Ru襯墊854。可施行多次劑量和熱浸泡製程循環,從而形成自成形的障壁858,如在參考標號856所示。於約4托(725 sccm N2)之基本壓力下施行一範例製程。每一循環包括暴露至DEZ約1分鐘,後續用2014 sccm H2(8托)熱浸泡1分鐘,台座的溫度約為350℃。
在十個循環之後,作為深度的函數之所得原子百分比分佈圖藉由曲線860所顯示。曲線862、864、866、和868分別顯示Si、Zn、Ru、和氧化鋅的原子百分比。如可看出,Zn既分佈於Ru-空氣界面,又分佈在Ru-SiO2界面。
圖8C概念性地說明按照揭示內容之實施例的用於金屬化通孔之製程。如在參考標號850所示,形成於電介質852中的通孔已電鍍有Ru或Co襯墊854。在參考標號870,施行按照參考圖8B所敘述之熱摻雜的循環製程,將諸如Zn或In之元素X沉積至Ru襯墊上,其中元素X遷移至襯墊854與電介質852之間的界面,而形成自成形之黏著性/障壁層858。於一些實施例中,在約180至400℃的溫度下施行循環/摻雜製程。於將基材暴露至空氣時,則如在參考標號872所示,於表面形成元素X之氧化物層874(XO保護層),所述氧化物層用作使襯墊的表面鈍化之保護層。
在通孔的金屬化之前,諸如藉由在還原環境中退火(例如,形成氣體退火)來移除氧化物層874。然後,藉由任何已知用於填充沉積的方法(諸如ALD、CVD、電鍍、無電沉積等),用導體878(例如Cu)大量填充通孔。
在毯覆晶圓上示範上述製程,並顯示TEM和EDS圖解結果。參考標號880係橫截面之TEM影像,其顯示於Zn摻雜之後的Ru之能帶。對應的EDS圖解882顯示Ru部分,但是Zn分佈在Ru層之兩側上。TEM影像884顯示於移除表面上的氧化鋅和Cu金屬化之後的SiO2、Ru和Cu層。對應之EDS圖解影像886說明在Ru-氧化物界面的Zn。
圖9更說明按照揭示內容之實施例,如何可經過沉積ZnO層後續進行熱處理將Zn摻雜進入Cu和Ru。顯示於氫處理之前和之後在銅上沉積有PVD氧化鋅層的毯覆晶圓之結果。
EDS圖解影像900及902顯示鋅氧化物層於施行退火之後消失。氧化鋅還原至金屬鋅,其接著擴散進入銅層。這亦藉由元素深度輪廓904所顯示。
EDS圖解影像906和908、以及深度輪廓910顯示與釕類似的概念。
圖10說明按照揭示內容之實施例,Cu中的摻雜之Zn如何是金屬的,反之當暴露至空氣時,鋅可於Cu的頂部上形成氧化鋅層。所說明之圖面示範當鋅還原並擴散進入銅時,所述製程在真空中完成,且當暴露至空氣時,藉由在銅層的頂部上創建自成形之氧化鋅層來防止銅的氧化,一些擴散之金屬鋅會出現並使銅鈍化。TEM影像1000顯示Cu和TaN層,於Cu的頂部上具有ZnO層。
在參考標號1010顯示對銅表面狀態之XPS研究,示範在對應於ZnO的0埃濺射深度(亦即,在表面處)之Zn峰。這顯示於表面的鋅為氧化鋅;反之,如果頂部層被濺射掉,則銅中的鋅為金屬鋅(形成留在銅層中之金屬鋅的儲集層)。
參考標號1020說明表面Cu之化學狀態,示範其為金屬的。
於參考標號1030所顯示之Zn深度輪廓分析顯示在表面的鋅之高濃度,且隨著深度而減小。
於參考標號1040,其顯示作為催化劑的Cu或Ru之存在可將ZnO的還原溫度降低到小於400℃。
在所說明之實施例中,存在TaN層,故阻止鋅遷移至下面的氧化物。然而,於沒有TaN層之情況下(例如在通孔中),則氧化鋅會還原為金屬鋅,其擴散進入釕並分離成具有氧的二界面-於底部之Ru-氧化物界面、及Zn當暴露至空氣時氧化的Ru之頂部。
參考標號1050顯示一機理-由此將氧化鋅還原為金屬鋅,其擴散進入銅;且鋅具有反應性,故當將基板置於大氣條件時,其一部分會析出並形成ZnO層,以保護銅免受氧化。
圖11說明按照揭示內容的實施例,可如何應用本揭示內容之概念,以實施可直接電鍍的襯墊。
在一些實施例中,控制器為系統之一部分,其可配置來按照揭示內容的實施例施行操作或方法。此系統可包含半導體處理設備,包括一個處理工具或多個處理工具、一個腔室或多個腔室、一個或多個用於處理之平台、及/或特定的處理部件(晶圓臺座、氣流系統等)。這些系統可為與電子器件整合在一起,用於控制它們在處理半導體晶圓或基材之前、期間和之後的操作。電子設備可稱為「控制器」,其可控制一系統或多系統之諸多部件或子零件。取決於處理要求及/或系統的類型,可將控制器編程以控制本文所揭示之任何製程,包括處理氣體的輸送、溫度設定(例如,加熱及/或冷卻)、壓力設定、真空設定、功率設定、射頻(RF)發生器設定、RF匹配電路設定、頻率設定、流速設定、流體輸送設定、位置和操作設定、晶圓進出工具和其他傳送工具及/或連接至特定系統或與特定系統介接之負載鎖定室。
廣義地說,控制器可定義為具有諸多積體電路、邏輯、記憶體、及/或軟體的電子設備,其接收指令、發布指令、控制操作、啟用清潔操作、啟用端點測量等。積體電路可包括儲存程式指令之呈韌體形式的晶片、數位信號處理器(DSP)、定義為特定應用積體電路(ASIC)之晶片、及/或執行程式指令(例如軟體)的一或更多微處理器、或微控制器。程式指令可為以諸多個別設定(或程式檔案)之形式傳遞給控制器的指令,其定義用於在半導體晶圓或系統上或針對半導體晶圓或系統執行特別製程之操作參數。於一些實施例中,操作參數可為製程工程師所定義的配方之一部分,以在晶圓的一或更多層、材料、金屬、氧化物、矽、二氧化矽、表面、電路、及/或裸晶之製造期間完成一或更多處理步驟。
於一些實施例中,控制器可為電腦的一部分或耦接至電腦,所述電腦與系統整合、耦接至系統,以別的方式聯網至所述系統,或以上方式組合。例如,控制器可位於“雲端”中或為工廠主機電腦系統之全部或一部份,其可允許晶圓處理的遠端存取。電腦可啟用對系統之遠端存取,以監控製造操作的當前進度、檢查過去製造操作之歷史、檢查來自複數個製造操作的趨勢或性能度量,以改變當前處理之參數將處理步驟設定成遵循當前處理、或啟動新的製程。在一些範例中,遠端電腦(例如伺服器)能透過網路向系統提供製程配方,所述網路可包括區域網路或網際網路。遠端電腦可包括實施參數及/或設定之輸入或編程的使用者介面,所述參數及/或設定接著從遠端電腦被傳遞至該系統。於一些範例中,控制器接收資料形式的指令,其指定在一或更多操作期間待施行之每一處理步驟的參數。應該理解的是,所述參數可專用於待施行之製程的類型及控制器配置成與之介接或對其加以控制的工具之類型。如此,如上面所述,控制器可為分佈式,諸如藉由包含一或更多以網路連結在一起且朝著共同目的(諸如在此敘述之製程和控制)工作的離散控制器。用於此等目的之分佈式控制器的範例將為腔室上之一或更多積體電路,其與遠端定位的一或更多積體電路(諸如在平台等級或作為遠端電腦之一部分)通訊,其組合以在腔室上控制製程。
非限制性地,示範系統可包括電漿蝕刻室或模組、沈積室或模組、自旋洗滌室或模組、金屬電鍍室或模組、清潔室或模組、斜邊蝕刻室或模組、物理氣相沈積(PVD)室或模組、化學氣相沈積(CVD)室或模組、原子層沈積(ALD)室或模組、原子層蝕刻(ALE)室或模組、離子植入室或模組、軌道室或模組、及可關聯於或用於半導體晶圓之製造及/或製作的任何其他半導體處理系統。
如上面所提及,取決於待由工具施行之一或更多製程步驟,控制器可與其他工具電路或模組、其他工具部件、集束型工具、其他工具介面、相鄰工具、附近工具、遍布工廠的工具、主電腦、另一控制器、或用於材料運送將晶圓容器攜帶進出半導體製造工廠中的工具位置及/或裝載埠之工具的一或更多者通訊。
圖12是用於實施本揭示內容之實施例的電腦系統之簡化概要圖。應當理解,本文所敘述的方法能以數位處理系統施行,諸如習知、通用之電腦系統。可在替代方案中使用設計或編程為僅施行一項功能的專用電腦。電腦系統1800包括中央處理單元(CPU)1804,其通過匯流排1810耦接至隨機存取記憶體(RAM)1828、唯讀記憶體(ROM)1812、和大容量儲存裝置1814。系統控制器程式1808常駐於隨機存取記憶體(RAM)1828中,但也可常駐在大容量儲存裝置1814中。
大容量儲存裝置1814代表可為本地或遠端之持久資料儲存裝置,諸如軟碟驅動器或固定碟驅動器。網路界面1830經由網路1832提供連接,從而允許與其他裝置通訊。應當理解,CPU 1804可在通用處理器、專用處理器、或專門編程的邏輯裝置中具體化。輸入/輸出(I / O)界面1820提供與不同週邊通訊,並經過匯流排1810與CPU 1804、RAM 1828、ROM 1812、和大容量儲存裝置1814連接。樣本週邊包括顯示器1818、鍵盤1822、游標控制器1824、可移除之媒體裝置1834等。
顯示器1818配置成顯示本文所述的使用者界面。鍵盤1822、游標控制器(鼠標)1824、可移除之媒體裝置1834、和其他週邊耦接至I / O界面1820,以將命令選擇中的資訊傳遞給CPU 1804。應當理解,可經過I / O界面1820將資料傳遞至外部裝置或從外部裝置傳遞資料。這些實施例亦可在分散式計算環境中實踐,在此任務藉由基於有線或無線網路鏈接之遠端處理裝置施行。
可利用包括手持式裝置、微處理器系統、基於微處理器的或可編程之消費電子產品、小型電腦、大型電腦等的諸多電腦系統配置來實踐實施例。亦可在分佈式計算環境中實踐這些實施例,在此藉由經過網路鏈接之遠端處理裝置施行任務。
考慮到以上實施例,應當理解,這些實施例可採用涉及儲存於電腦系統中的資料之諸多電腦實施的操作。這些操作是需要物理操縱之物理量的操作。在此所敘述之形成實施例的一部分之任何操作為有用的機器操作。實施例亦有關用於施行這些操作之裝置或設備。所述設備可為專門構造用於所需目的、諸如專用電腦。當被定義為專用電腦時,所述電腦亦可施行不屬於專用電腦之其他處理、程式執行、或子程式,同時仍然能夠針對專用電腦進行操作。另一選擇係,這些操作可藉由通用電腦處理,所述通用電腦藉由儲存在電腦記憶體、快閃記憶體中、或透過網路所獲得的一或更多電腦程式選擇性地啟動或配置。當透過網路獲得資料時,所述資料可藉由網路上之其他電腦(例如,計算資源的雲端)處理。
一或更多實施例亦可製造為電腦可讀媒體上之電腦可讀碼。所述電腦可讀媒體是可儲存資料的任何資料儲存裝置,所述資料其後可藉由電腦系統讀取。電腦可讀媒體之範例包括硬碟、網路附加儲存裝置(NAS)、唯讀記憶體、隨機存取記憶體、CD-ROM、CD-R、CD-RW、磁帶、及其他光學和非光學資料儲存裝置。電腦可讀媒體可包括分佈在網路耦接的電腦系統之電腦可讀實質媒體,以致用分佈式方式儲存和執行電腦可讀碼。
儘管以特定順序敘述了方法操作,但是應該理解,其他內務處理操作可於操作之間施行,或可調整操作以致它們在稍微不同的時間發生,或可分佈於系統中,只要以期望之方式施行覆疊操作的處理,這允許在與所述處理相關聯之諸多間隔處發生處理操作。
因此,示範實施例的揭示內容是意欲為本揭示內容之說明性、而不是限制性範圍,本揭示內容的範圍於以下申請專利範圍及其同等項中提出。儘管為了清楚理解之目的已詳細敘述本揭示內容之示範實施例,但是將顯而易見的是,可在以下申請專利之範圍內實踐某些改變和修改。於所附申請專利中,除非在申請專利中明確地陳述或藉由本揭示內容所暗含地要求,否則元件及/或步驟並未暗示任何特別的操作順序。
104:導體(Cu)線
106:溝道
108:通孔
112:通孔預填充物
114:障壁層
118:障壁層/襯墊層
120:塊狀導體
202:氧化物層
204:Cu層
208:Cu-In層
210:Cu層
214:氧化銦層
216:Cu層
220:銅層
232:Cu層
236:塊狀銅層
238:銅層
252:小節
260:EDS圖解
262:氧化矽
264:銦
266:銅
270:曲線圖
272:曲線
274:曲線
276:曲線
300:影像
302:影像
304:影像
306:影像
308:影像
310:影像
312:影像
314:影像
316:影像
318:影像
400:影像
402:影像
404:影像
406:影像
500:影像
602:氧化物
604:導體線
606:通孔
608:溝道
612:通孔預填充物
616:金屬氧化物層
620:障壁層
630:影像
700:影像
702:曲線
704:曲線
706:曲線
708:曲線
710:曲線
712:曲線
714:曲線
716:曲線
718:曲線
720:曲線
722:曲線
724:曲線
726:曲線
728:曲線
730:曲線
810:影像
812:影像
814:曲線
816:曲線
818:曲線
820:曲線
832:電介質
834:Cu線
836:通孔
838:溝道
842:Cu通孔預填充物
846:自成形障壁
852:電介質
854:襯墊
858:障壁
860:曲線
862:曲線
864:曲線
866:曲線
868:曲線
874:氧化物層
878:導體
882:EDS圖解
884:TEM影像
886:EDS圖解影像
900:EDS圖解影像
902:EDS圖解影像
904:元素深度輪廓
906:EDS圖解影像
908:EDS圖解影像
910:深度輪廓
1800:電腦系統
1804:中央處理單元
1808:系統控制器程式
1810:匯流排
1812:唯讀記憶體
1814:大容量儲存裝置
1818:顯示器
1820:輸入/輸出(I/O)界面
1822:鍵盤
1824:游標控制器
1828:隨機存取記憶體
1830:網路界面
1832:網路
1834:媒體裝置
將參考所說明的圖示了解本揭示內容之實施例。
圖1A說明隨著CD尺寸縮小以啟用下一代技術節點而出現的問題。
圖1B說明用於按照揭示內容之實施例形成自成形的障壁層之製程。
圖2示範按照揭示內容的實施例在毯覆基材上形成有無電銅銦(Cu-In)之界面層。
圖3顯示按照揭示內容的實施例藉由銅銦之無電沉積所施行的通孔填充之諸多影像。
圖4說明按照揭示內容的實施例之諸多退火條件以及在基材的通孔結構中之銦的所得分佈。
圖5顯示EDS圖解影像500,按照揭示內容之實施例說明在如上所述的二階段退火之後於通孔預填充物中的銦和銅之存在。
圖6說明按照揭示內容的實施例用於經由金屬氧化物層之退火來產生自成形障壁的製程。
圖7顯示按照上述製程處理之通孔結構的表徵,按照揭示內容之實施例示範氧化鋅和鋅擴散進入通孔預填充物。
圖8A說明按照揭示內容的實施例用於摻雜ALD前驅物之製程。
圖8B概念性地說明按照揭示內容的實施例用於摻雜Ru襯墊之製程,而用於自成形障壁(SFB)形成。
圖8C概念性地說明按照揭示內容的實施例用於金屬化通孔之製程。
圖9更說明按照揭示內容的實施例如何經過沉積ZnO層然後進行熱處理將Zn摻雜進入Cu和Ru。
圖10說明按照揭示內容之實施例的Cu中之摻雜的Zn如何是金屬的,反之當暴露至空氣時,鋅可在Cu的頂部上建立氧化鋅層。
圖11說明按照揭示內容之實施例如何可將本揭示內容的概念應用於實施可直接電鍍之襯墊。
圖12係用於實施本揭示內容的實施例之電腦系統的簡化概要圖。
852:電介質
854:襯墊
858:障壁
874:氧化物層
878:導體
882:EDS圖解
884:TEM影像
886:EDS圖解影像
Claims (20)
- 一種用於在基材的特徵部中形成自成形障壁之方法,包括: 將金屬襯墊沉積於該基材的該特徵部中,該金屬襯墊沉積在該基材之電介質上方; 將含鋅前驅物沉積於該金屬襯墊上方; 施行該基材的熱浸泡; 將該含鋅前驅物之該沉積步驟和該基材的熱浸泡步驟重複預定之循環次數; 其中該方法在該金屬襯墊和該電介質之間的界面形成含鋅之障壁層。
- 如申請專利範圍第1項之方法,其中該金屬襯墊由釕所組成。
- 如申請專利範圍第1項之方法,其中該金屬襯墊由鈷所組成。
- 如申請專利範圍第1項之方法,其中該特徵部為通孔。
- 如申請專利範圍第1項之方法,其中該特徵部為互連部。
- 如申請專利範圍第1項之方法,其中該含鋅前驅物為二乙基鋅。
- 如申請專利範圍第1項之方法,其中沉積該含鋅前驅物的步驟藉由化學氣相沉積製程來施行。
- 如申請專利範圍第1項之方法,其中該熱浸泡在約180至400℃的溫度下施行。
- 如申請專利範圍第1項之方法,更包含: 在該重複該預定循環次數的步驟之後,接著將導體沉積於該基材的該特徵部中。
- 如申請專利範圍第9項之方法,其中該導體為銅。
- 一種用於在基材的特徵部中形成自成形障壁之方法,包含: 將金屬襯墊沉積於該基材的該特徵部中,該金屬襯墊沉積在該基材之電介質上方; 將含銦前驅物沉積於該金屬襯墊上方; 施行該基材的熱浸泡; 將該含銦前驅物之該沉積步驟和該基材的熱浸泡步驟重複預定之循環次數; 其中該方法在該金屬襯墊和該電介質之間的界面形成含銦之障壁層。
- 如申請專利範圍第11項之方法,其中該金屬襯墊由釕所組成。
- 如申請專利範圍第11項之方法,其中該金屬襯墊由鈷所組成。
- 如申請專利範圍第11項之方法,其中該特徵部為通孔。
- 如申請專利範圍第11項之方法,其中該特徵部為互連部。
- 如申請專利範圍第11項之方法,其中該含銦前驅物為三甲基銦。
- 如申請專利範圍第11項之方法,其中沉積該含銦前驅物的步驟藉由化學氣相沉積製程來施行。
- 如申請專利範圍第11項之方法,其中該熱浸泡在約180至400℃的溫度下施行。
- 如申請專利範圍第11項之方法,更包含: 在該重複該預定循環次數的步驟之後,接著將導體沉積於該基材的該特徵部中。
- 如申請專利範圍第19項之方法,其中該導體為銅。
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US20230298936A1 (en) * | 2020-08-13 | 2023-09-21 | Lam Research Corporation | Combined self-forming barrier and seed layer by atomic layer deposition |
FR3115046B1 (fr) * | 2020-10-09 | 2023-12-01 | Aveni | Procédé pour la fabrication d’une mémoire 3D-NAND |
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