FR3115046B1 - Procédé pour la fabrication d’une mémoire 3D-NAND - Google Patents

Procédé pour la fabrication d’une mémoire 3D-NAND Download PDF

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Publication number
FR3115046B1
FR3115046B1 FR2010350A FR2010350A FR3115046B1 FR 3115046 B1 FR3115046 B1 FR 3115046B1 FR 2010350 A FR2010350 A FR 2010350A FR 2010350 A FR2010350 A FR 2010350A FR 3115046 B1 FR3115046 B1 FR 3115046B1
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France
Prior art keywords
manufacturing
nand memory
alloy
manganese
layer
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Active
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FR2010350A
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English (en)
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FR3115046A1 (fr
Inventor
Frédéric Raynal
Vincent Mevellec
Mikailou Thiam
Amine Lakhdari
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Aveni SA
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Aveni SA
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Publication date
Priority to FR2010350A priority Critical patent/FR3115046B1/fr
Application filed by Aveni SA filed Critical Aveni SA
Priority to EP21790429.1A priority patent/EP4225977A1/fr
Priority to TW110137558A priority patent/TW202220112A/zh
Priority to US18/030,158 priority patent/US20230335496A1/en
Priority to KR1020237014956A priority patent/KR20230079430A/ko
Priority to JP2023521504A priority patent/JP2023544833A/ja
Priority to CN202180082535.6A priority patent/CN116568864A/zh
Priority to PCT/EP2021/077913 priority patent/WO2022074221A1/fr
Publication of FR3115046A1 publication Critical patent/FR3115046A1/fr
Application granted granted Critical
Publication of FR3115046B1 publication Critical patent/FR3115046B1/fr
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/56—Electroplating: Baths therefor from solutions of alloys
    • C25D3/58—Electroplating: Baths therefor from solutions of alloys containing more than 50% by weight of copper
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/30—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
    • C23C28/32—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one pure metallic layer
    • C23C28/321—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one pure metallic layer with at least one metal alloy layer
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/30—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
    • C23C28/34—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates
    • C23C28/345—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates with at least one oxide layer
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/38—Electroplating: Baths therefor from solutions of copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/48—After-treatment of electroplated surfaces
    • C25D5/50—After-treatment of electroplated surfaces by heat-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Electrochemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Mechanical Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electroplating And Plating Baths Therefor (AREA)

Abstract

Procédé pour la fabrication d’une mémoire 3D-NAND L’invention se rapporte à un procédé pour la fabrication d’une mémoire 3D-NAND comprenant une première étape d’électrodéposition d’un alliage de cuivre et d’un métal dopant choisi parmi le manganèse et le zinc suivie d’une deuxième étape de recuit de l’alliage pour former une première couche de cuivre et une deuxième couche comprenant le zinc ou le manganèse, par démixtion de l’alliage. Figure pour l’abrégé : Figure 3C
FR2010350A 2020-10-09 2020-10-09 Procédé pour la fabrication d’une mémoire 3D-NAND Active FR3115046B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR2010350A FR3115046B1 (fr) 2020-10-09 2020-10-09 Procédé pour la fabrication d’une mémoire 3D-NAND
TW110137558A TW202220112A (zh) 2020-10-09 2021-10-08 用於製備3d-nand快閃記憶體之方法
US18/030,158 US20230335496A1 (en) 2020-10-09 2021-10-08 Process for Fabricating a 3D-NAND Flash Memory
KR1020237014956A KR20230079430A (ko) 2020-10-09 2021-10-08 3차원 낸드 플래시 메모리를 제조하기 위한 공정
EP21790429.1A EP4225977A1 (fr) 2020-10-09 2021-10-08 Procédé de fabrication d'une mémoire flash non-et 3d
JP2023521504A JP2023544833A (ja) 2020-10-09 2021-10-08 ３ｄ ｎａｎｄフラッシュメモリを作製するためのプロセス
CN202180082535.6A CN116568864A (zh) 2020-10-09 2021-10-08 制造3d-nand闪存的方法
PCT/EP2021/077913 WO2022074221A1 (fr) 2020-10-09 2021-10-08 Procédé de fabrication d'une mémoire flash non-et 3d

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2010350 2020-10-09
FR2010350A FR3115046B1 (fr) 2020-10-09 2020-10-09 Procédé pour la fabrication d’une mémoire 3D-NAND

Publications (2)

Publication Number Publication Date
FR3115046A1 FR3115046A1 (fr) 2022-04-15
FR3115046B1 true FR3115046B1 (fr) 2023-12-01

Family

ID=74859987

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2010350A Active FR3115046B1 (fr) 2020-10-09 2020-10-09 Procédé pour la fabrication d’une mémoire 3D-NAND

Country Status (8)

Country Link
US (1) US20230335496A1 (fr)
EP (1) EP4225977A1 (fr)
JP (1) JP2023544833A (fr)
KR (1) KR20230079430A (fr)
CN (1) CN116568864A (fr)
FR (1) FR3115046B1 (fr)
TW (1) TW202220112A (fr)
WO (1) WO2022074221A1 (fr)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10163695B1 (en) * 2017-06-27 2018-12-25 Lam Research Corporation Self-forming barrier process
JP7368394B2 (ja) * 2018-06-30 2023-10-24 ラム リサーチ コーポレーション ライナの不動態化および接着性改善のための金属ライナのジンケート処理およびドーピング
FR3092589A1 (fr) * 2019-02-08 2020-08-14 Aveni Electrodéposition d’un alliage de cobalt et utilisation en microélectronique

Also Published As

Publication number Publication date
WO2022074221A1 (fr) 2022-04-14
US20230335496A1 (en) 2023-10-19
CN116568864A (zh) 2023-08-08
KR20230079430A (ko) 2023-06-07
TW202220112A (zh) 2022-05-16
EP4225977A1 (fr) 2023-08-16
FR3115046A1 (fr) 2022-04-15
JP2023544833A (ja) 2023-10-25

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