TW201820388A - 用於半導體處理之矽基沉積 - Google Patents

用於半導體處理之矽基沉積 Download PDF

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TW201820388A
TW201820388A TW106128210A TW106128210A TW201820388A TW 201820388 A TW201820388 A TW 201820388A TW 106128210 A TW106128210 A TW 106128210A TW 106128210 A TW106128210 A TW 106128210A TW 201820388 A TW201820388 A TW 201820388A
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substrate
processing
containing gas
processing chamber
silicon
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忠魁 譚
晴 徐
謙 符
華 相
臨 趙
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美商蘭姆研究公司
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Abstract

一種於處理腔室中處理基板的方法，其包含在該基板上形成一沉積物。使一含矽氣體流入該處理腔室中。使一含COS氣體流入該處理腔室中。於該處理腔室中由該含矽氣體及該含COS氣體形成一電漿，其中該電漿在該基板上提供該沉積物。

Description

用於半導體處理之矽基沉積
本揭露內容係關於在半導體晶圓上形成半導體元件的方法。更具體而言，本揭露內容係關於在半導體元件之形成中形成矽基沉積物。
在形成半導體元件之步驟中，將各樣的層進行沉積。
為達成上述內容且根據本揭示內容之目的，提供一種於處理腔室中處理基板的方法，其包含在該基板上形成一沉積物。使一含矽氣體流入該處理腔室中。使一含COS氣體流入該處理腔室中。於該處理腔室中由該含矽氣體及該含COS氣體形成一電漿，其中該電漿在該基板上提供該沉積物。
本發明之這些與其他特徵將會於以下實施例之實施方式中配合下述圖式而詳細描述。
現在將參照本發明的一些較佳實施例來詳細說明本發明之內容，該等較佳實施例係繪示於隨附圖式中。為提供對本揭露內容的周密了解，接下來的敘述中將提出許多特定的細節。然而，顯而易見的，對於熟悉本技藝者而言，可實行本揭露內容而無須其中部分或全部的特定細節。在其他情況下，為了不對本發明造成不必要地混淆，眾所周知的程序步驟與/或結構則沒有加以詳述。
圖1為一實施例之高階流程圖。在此實施例中，將處理層置於處理腔室中(步驟104)。將特徵部分地蝕刻至處理層中(步驟108)。將包含矽、氧、及硫的鈍化層沉積於經部分蝕刻之特徵上(步驟112)。繼續處理層中之特徵的蝕刻(步驟116)。將鈍化層移除(步驟120)。從處理腔室將處理層移除(步驟124)。範例
在一較佳實施例中，處理層包含ONON(矽氧化物、矽氮化物、矽氧化物、矽氮化物並繼續重複)堆疊。圖2A為基板208之示意性橫剖面圖，具有在圖案化遮罩220下方之處理層204。一或更多層可設置於處理層204與基板208之間。在此實施例中，處理層204為複數記憶體堆疊， 其係由在一層矽氮化物層212頂部上的一層矽氧化物(SiO2 )層216的複數雙層所形成。圖案化遮罩220為碳硬遮罩。
根據本發明的一實施例，圖3示意性地繪示了可用以對處理層204進行處理的電漿處理系統300之範例。電漿處理系統300包含電漿反應器302，該電漿反應器302具有被腔室壁352包圍的電漿處理腔室304。由匹配網路308調諧的電漿電源供應器306將功率供應至位於電力窗(power window)312附近的TCP線圈310，以藉由提供感應耦合功率而在電漿處理腔室304中產生電漿314。TCP線圈(上功率源)310可建構成在電漿處理腔室304內產生均勻的擴散輪廓(diffusion profile)。舉例而言，TCP線圈310可建構成在電漿314中產生環形功率分布。電力窗312係設置用以使TCP線圈310與電漿處理腔室304分開，並同時容許能量從TCP線圈310通至電漿處理腔室304。由匹配網路318調諧的晶圓偏電壓電源供應器316將功率提供至電極320以設定在處理層204上的偏壓電壓，該處理層204係被支撐在電極320上方。控制器324針對電漿電源供應器306、及晶圓偏電壓電源供應器316設定數值。
電漿電源供應器306及晶圓偏電壓電源供應器316可建構成以特定射頻(例如，13.56 MHz、27 MHz、2 MHz、400 kHz、或其組合)運作。為了達到期望的製程效能，可適當地選擇電漿電源供應器306及晶圓偏電壓電源供應器316之尺寸以供應一範圍的功率。舉例而言，在本發明的一實施例中，電漿電源供應器306可供應在50至5000瓦特之範圍內的功率，且晶圓偏電壓電源供應器316可供應在20至2000伏特之範圍內的偏壓電壓。此外，TCP線圈310及/或電極320可由二或更多子線圈或子電極所構成，該等子線圈或子電極可由單一電源供應器加以供電或由多個電源供應器加以供電。
如圖3中所示，電漿處理系統300更包含一氣體來源/氣體供應機構330。該氣體源/氣體供應機構330提供氣體至氣體饋送部336，該氣體饋送部336係採取噴嘴之形式。處理氣體及副產物係經由壓力控制閥342及泵浦344而從電漿處理腔室304移除，該壓力控制閥342及泵浦344亦用以維持電漿處理腔室304中的特定壓力。氣體來源/氣體供應機構330係由控制器324加以控制。由加州Fremont之Lam Research Corp.生產之Kiyo可用以實行本發明的實施例。
圖4係顯示了電腦系統400之高階方塊圖，該電腦系統400係適用於實現實施例中所使用的控制器324。該電腦系統可具有從積體電路、印刷電路板、及小型手持裝置至大型超級電腦的許多實體形式。電腦系統400包含一或更多處理器402，且更可包含電子顯示裝置404(用於顯示圖形、文字、及其他資料)、主記憶體406(例如，隨機存取記憶體(RAM))、儲存裝置408(例如，硬碟機)、可移除式儲存裝置410(例如，光碟機)、使用者介面裝置412(例如，鍵盤、觸控螢幕、小鍵盤(keypads)、滑鼠、或其他指向裝置等)、及通訊介面414(例如，無線網路介面)。通訊介面414允許軟體及資料經由一連結而在電腦系統400與外部裝置之間傳輸。該系統亦可包含通訊設施416(例如，通訊匯流排、交越條(cross-over bar)、或網路)，上述裝置/模組係連接至該通訊設施416。
經由通訊介面414傳輸的資訊可採取訊號之形式，例如能夠經由通訊連結而被通訊介面414接收的電子、電磁、光學、或其他訊號，該通訊連結攜帶訊號且可藉由使用導線或纜線、光纖、電話線、行動電話連結、射頻連結、及/或其他通訊通道加以實現。在使用此種通訊介面之情況下，吾人預期一或更多處理器402可於執行上述方法步驟期間內從網路接收資訊、或可將資訊輸出至網路。此外，方法實施例可僅在該等處理器上執行，或可透過網路(例如，網際網路)而結合遠端處理器(其分擔一部分的處理)執行。
術語「非暫態電腦可讀媒體」通常係用以意指媒體，例如主記憶體、輔助記憶體、可移除式儲存裝置及儲存裝置(例如硬碟)、快閃記憶體、磁碟機記憶體、CD-ROM、及其他形式的持續性記憶體，且不應被理解為涵蓋暫時性標的(例如，載波或訊號)。電腦碼之範例包含機器碼(例如，藉由編譯器產生)、及含有較高階碼的檔案，該較高階的碼係藉由使用解譯器的電腦而執行。電腦可讀媒體亦可為藉由電腦數據訊號而傳輸的電腦碼，該電腦數據訊號係包含在載波中且代表了可由處理器執行之指令的序列。
在基板208已置於電漿處理系統300中之後，將特徵部分地蝕刻至處理層中(步驟108)。在此範例中，在處理層204為ONON堆疊之情況下，使包含C4 F6 、O2 、NF3 、CH2 F2 之蝕刻氣體流入電漿處理腔室304中並轉換為電漿以對ONON堆疊進行蝕刻。圖2B為對特徵進行部分蝕刻(其形成具有側壁228的經蝕刻特徵224)之後的堆疊200之橫剖面圖。
將包含矽、氧、及硫的鈍化層沉積在處理層上(步驟112)。圖5為沉積鈍化層之實施例(步驟112)的更詳細流程圖。使含矽的氣體流入電漿處理腔室304中(步驟504)。使含COS的氣體流入電漿處理腔室304中(步驟508)。於電漿處理腔室304中形成電漿(步驟512)。較佳地，該電漿為原位電漿(in situ plasma)而非遠距電漿。該電漿導致包含矽、氧、及硫的沉積物沉積在處理層上。較佳地，該沉積層亦包含碳。此處理之配方的範例使100 sccm之SiCl4 、及100 sccm之COS流入在50毫托之壓力下的處理腔室304中。以13.56 MHz之頻率提供2500瓦特的電漿RF功率，其將SiCl4 氣體及COS氣體轉換為電漿。沒有提供偏壓。使該處理維持10秒。接著藉由停止RF功率及氣體的流量而停止該處理。對於具有約50至100 nm之寬度的特徵而言，鈍化係提供至約1至4微米的深度。圖2C為鈍化層232已沉積於處理層204的經蝕刻側壁228上之後的堆疊200之橫剖面圖。為了更清楚地繪示各樣的特徵，該圖並非為按比例繪製。
接著繼續蝕刻處理(步驟116)。在此實施例中，使蝕刻處理繼續直到處理層係加以完全蝕刻。這裡可以使用與對堆疊進行部分蝕刻之配方類似的蝕刻配方。圖2D為處理層204已完全蝕刻(步驟116)之後的堆疊200之橫剖面圖。
將鈍化層移除(步驟120)。在一實施例中，上述蝕刻處理將鈍化層完全移除。若在上述蝕刻處理之後殘留一些鈍化層，則可提供獨立的鈍化移除處理。用以移除鈍化層的配方之範例在20 mT的腔室壓力下提供100 sccm的CF4 、及20 sccm的O2 之流量。提供TCP的1000 W之RF信號以使氣體形成電漿。沒有提供偏壓。提供30℃的晶圓溫度。使電漿維持20秒。接著可停止功率及氣體之流量。圖2E為鈍化層已完全移除之後(步驟120)的堆疊200之剖面圖。
從電漿處理腔室304將基板上的處理層移除(步驟124)。可於從電漿處理腔室移除基板之前或之後執行額外的處理。
此實施例提供特徵，其沒有若沒有於完成蝕刻之前提供沉積層會導致的翹曲。一般而言，翹曲會是由在特徵之頂部附近的側壁蝕刻所引起，而沉積層已經於該處沉積在側壁上。由於沉積層對側壁蝕刻具有高度抵抗力，因此減少了翹曲。較佳地，側壁上的鈍化層之厚度係小於2 nm。
不受理論所限制，吾人相信該沉積步驟沉積了包含矽、氧、及硫的一層 ，且該層可更包含碳。該沉積層據信為對蝕刻導電或介電材料(例如，多晶矽、矽氧化物、矽氮化物、含金屬層(例如，摻雜鎢)、或含碳層)用的各種蝕刻處理具有高度抵抗力的。當單獨使用例如O2 、Cl2 、SF6 、NF3 、CF4 、HBr、及CHx Fy (其中x和y為正整數)這樣的蝕刻劑時，該沉積層能夠抵抗使用這樣的蝕刻劑之蝕刻處理中的側壁蝕刻。
在一實施例中，沉積層係藉由使用SiCl4 及COS以形成電漿而加以形成。吾人已經發現，依序地、同時地、或循環地提供SiCl4 及COS提供了自特徵之頂部起幾微米深的鈍化。吾人已發現該蝕刻抵抗力針對不同的蝕刻化學品持續了20-1000秒。
這樣的抗蝕刻層提供了對蝕刻輪廓(etch profile)、選擇性、線邊緣粗糙度、及微負載的更好控制。隨著特徵尺寸縮小，在高的深寬比特徵之情況下，將鈍化物種提供至在特徵深處的目標位置變得更加困難。本說明書及申請專利範圍中的高深寬比特徵係定義為具有大於20：1的高度對寬度之深寬比。更佳地，藉由使用一實施例而形成具有大於50：1之高度對寬度比例的高深寬比特徵。此外，藉由一實施例而達成了在沒有翹曲之情況下保持直的蝕刻輪廓。
若鈍化層不是這麼耐蝕刻，則需要更多的鈍化，而這可導致蝕刻停止。在各樣的實施例中所使用之鈍化層為足夠地耐蝕刻的，以防止蝕刻停止。由於沈積層對各種蝕刻劑為抗蝕刻的，所以可使用沉積層做為蝕刻許多不同材料及多層不同材料(例如，記憶體堆疊)用的鈍化層。
吾人已經發現，該沉積層可輕易地藉由含鹵素的成分氣體及氧 所形成的電漿而加以移除。較佳地，沉積移除氣體包含NF3 及O2 、或CF4 和O2 。由於有能夠輕易且完全移除沉積層的蝕刻劑之組合，因此可在不損傷蝕刻特徵且具有高生產量之情況下移除沉積層。
在SiCl4 及COS係分開且循環地提供達幾個循環的實施例中，處理可花費更長時間。然而，針對寬度小於20 nm的小特徵尺寸，發現了更好的階梯覆蓋性及保形性。
由於任何氣相反應處理會形成頭重腳輕型（top-heavy）之沉積且不具有將高深寬比特徵鈍化的能力，吾人相信該沉積層係藉由電漿之間的表面反應所形成。雖然吾人相信沈積層更包含碳(由於COS所提供的碳成分)，然而難以對沉積層進行測試以證明碳的存在。吾人亦相信鈍化層為SiO2 、SiC、及SiS2 之混合物，其中SiS2 為沉積層之結構的支柱。SiS2 為可形成交聯結構的聚合物材料，其對氟、氯、或氧自由基具有抵抗力。SiO2 及SiC在此聚合物中係做為填料以製造一緻密化薄膜來阻止反應性物種的化學擴散。
實驗已經顯示，相較於包含SiO2 、SiN、或Si之原子層沉積(ALD)膜的其他沉積和鈍化處理，實施例提供了優異且改良的階梯覆蓋性。實施例顯示了對導電及介電處理層二者的改良之鈍化。由於5至100秒的沉積會為約200至1000秒之蝕刻ONON層提供翹曲保護，因此實施例亦展現了改良的產量。這樣的沉積可用在形成記憶體中的介電質蝕刻上。
各樣的實施例提供了非自限性的沉積層，因此並非使用原子層沉積。因此，各樣的實施例中之此沉積層的形成係較藉由使用原子層沉積形成沉積層快得多。沉積率係隨時間及電漿功率而變化。另外，在循環且依序的實施例中，實施例不需要ALD用以防止氣體混合所需的吹淨(purge)。由於若氣體有一些混合不會是有害的，因此吹淨為不需要的。消除吹淨的需要提供了甚至更快的處理。另外，該沉積提供了較習知化學氣相沉積(CVD)更好的沉積。
在各樣的實施例中，含矽氣體包含SiH4 、SiF4 、SiCl4 、SiHx Fy 、SiHx Cly 、SiFx Cly 其中至少一者，其中x及y為正整數且x + y = 4。較佳地，含矽氣體為SiCl4 。
其他實施例可將包含矽、氧、及硫的沉積層用於側壁鈍化之外的其他用途。例如，該沉積層可做為蝕刻遮罩。在另一實施例中，沉積層可做為間隔部。這樣的間隔部可於形成鰭片結構中使用。這樣的沉積可相對於後續處理而原位或異位執行。
雖然本揭露內容已就數個較佳實施例加以描述，但仍存在變更、修改、變化、及各種同等替代物，其皆落入本揭露內容之範圍內。亦應注意本發明之方法及設備有許多替代的實行方式。因此，以下隨附申請專利範圍應被解釋為包含所有落入本發明之真正精神及範圍內的變更、修改、變化、及同等替代物。
104‧‧‧步驟
108‧‧‧步驟
112‧‧‧步驟
116‧‧‧步驟
120‧‧‧步驟
124‧‧‧步驟
200‧‧‧堆疊
204‧‧‧處理層
208‧‧‧基板
212‧‧‧矽氮化物層
216‧‧‧矽氧化物層
220‧‧‧圖案化遮罩
224‧‧‧經蝕刻特徵
228‧‧‧側壁
232‧‧‧鈍化層
300‧‧‧電漿處理系統
302‧‧‧電漿反應器
304‧‧‧處理腔室
306‧‧‧電漿電源供應器
308‧‧‧匹配網路
310‧‧‧TCP線圈
312‧‧‧電力窗
314‧‧‧電漿
316‧‧‧晶圓偏壓電壓電源供應器
318‧‧‧匹配網路
320‧‧‧電極
324‧‧‧控制器
330‧‧‧氣體來源/氣體供應機構
336‧‧‧氣體饋送部
342‧‧‧壓力控制閥
344‧‧‧泵浦
352‧‧‧腔室壁
400‧‧‧電腦系統
402‧‧‧處理器
404‧‧‧電子顯示裝置
406‧‧‧主記憶體
408‧‧‧儲存裝置
410‧‧‧可移除式儲存裝置
412‧‧‧使用者介面裝置
414‧‧‧通訊介面
416‧‧‧通訊設施
504‧‧‧步驟
508‧‧‧步驟
512‧‧‧步驟
516‧‧‧步驟
本揭露內容在隨附圖式中係以舉例的方式說明，而非限制的方式，隨附圖式中相似的元件符號係代表類似的元件，且其中：
圖1為一實施例之高階流程圖。
圖2A-E為根據一實施例進行處理之堆疊體的示意性橫剖面圖。
圖3為可於一實施例中使用之蝕刻腔室的示意圖。
圖4為可在實行一實施例中使用之電腦系統的示意圖。
圖5為一沉積層形成步驟之詳細流程圖。

Claims (20)

  1. 一種於處理腔室中處理基板的方法，該方法包含在該基板上形成一沉積物的步驟，該步驟包含： 使一含矽氣體流入該處理腔室中； 使一含COS氣體流入該處理腔室中；及 於該處理腔室中由該含矽氣體、及該含COS氣體形成一電漿，其中該電漿在該基板上提供該沉積物。
  2. 如申請專利範圍第1項之於處理腔室中處理基板的方法，其中該沉積物包含矽、氧、及硫。
  3. 如申請專利範圍第2項之於處理腔室中處理基板的方法，其中該沉積物更包含碳。
  4. 如申請專利範圍第3項之於處理腔室中處理基板的方法，更包含：於在該基板上形成該沉積物之後，對在該沉積物下方的一蝕刻層進行蝕刻。
  5. 如申請專利範圍第4項之於處理腔室中處理基板的方法，更包含於在該基板上形成該沉積物之前對該蝕刻層中之特徵進行部分蝕刻，其中一圖案化遮罩係位於在該蝕刻層上方，且其中該沉積物係位於該特徵之側壁的至少一部分上。
  6. 如申請專利範圍第5項之於處理腔室中處理基板的方法，更包含將該沉積物移除。
  7. 如申請專利範圍第6項之於處理腔室中處理基板的方法，其中該移除該沉積物之步驟包含： 提供一移除氣體，該移除氣體包含了含鹵素成分及O2 ；及 由該移除氣體形成一電漿，其移除該沉積物。
  8. 如申請專利範圍第7項之於處理腔室中處理基板的方法，其中該含矽氣體包含SiH4 、SiF4 、SiCl4 、SiHx Fy 、SiHx Cly 、SiFx Cly 其中至少一者，其中x及y為正整數，且x + y = 4。
  9. 如申請專利範圍第3項之於處理腔室中處理基板的方法，其中該含矽氣體及該含COS氣體係同時提供。
  10. 如申請專利範圍第3項之於處理腔室中處理基板的方法，其中該含矽氣體及該含COS氣體係依序提供，其中該含矽氣體與該含COS氣體之間有一些混合。
  11. 如申請專利範圍第3項之於處理腔室中處理基板的方法，其中該含矽氣體及該含COS氣體係循環地提供達複數循環，其中該含矽氣體與該含COS氣體之間有一些混合。
  12. 如申請專利範圍第3項之於處理腔室中處理基板的方法，更包含於在該基板上形成該沉積物之後對在該沉積物下方的一蝕刻層進行蝕刻。
  13. 如申請專利範圍第12項之於處理腔室中處理基板的方法，更包含於在該基板上形成該沉積物之前對該蝕刻層中之特徵進行部分蝕刻，其中一圖案化遮罩係位於在該蝕刻層上方，且其中該沉積物係位於該特徵之側壁的至少一部分上。
  14. 如申請專利範圍第13項之於處理腔室中處理基板的方法，更包含將該沉積物移除。
  15. 如申請專利範圍第14項之於處理腔室中處理基板的方法，其中該移除該沉積物之步驟包含： 提供一移除氣體，該移除氣體包含了含鹵素成分及O2；及 由該移除氣體形成一電漿，其移除該沉積物。
  16. 如申請專利範圍第1項之於處理腔室中處理基板的方法，其中該含矽氣體包含SiH4 、SiF4 、SiCl4 、SiHx Fy 、SiHx Cly 、SiFx Cly 其中至少一者，其中x及y為正整數，且x + y = 4。
  17. 如申請專利範圍第1項之於處理腔室中處理基板的方法，其中該矽氣體及該含COS氣體係同時提供。
  18. 如申請專利範圍第1項之於處理腔室中處理基板的方法，其中該含矽氣體及該含COS氣體係依序提供，其中該含矽氣體與該含COS氣體之間有一些混合。
  19. 如申請專利範圍第1項之於處理腔室中處理基板的方法，其中該含矽氣體及該含COS氣體係循環地提供達複數循環，其中該含矽氣體與該含COS氣體之間有一些混合。
  20. 如申請專利範圍第1項之於處理腔室中處理基板的方法，更包含將該沉積物移除。
TW106128210A 2016-08-23 2017-08-21 用於半導體處理之矽基沉積 TW201820388A (zh)

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