CN107768233A - 用于半导体处理的硅基沉积 - Google Patents

用于半导体处理的硅基沉积 Download PDF

Info

Publication number
CN107768233A
CN107768233A CN201710695559.4A CN201710695559A CN107768233A CN 107768233 A CN107768233 A CN 107768233A CN 201710695559 A CN201710695559 A CN 201710695559A CN 107768233 A CN107768233 A CN 107768233A
Authority
CN
China
Prior art keywords
gas
deposit
silicon
plasma
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710695559.4A
Other languages
English (en)
Inventor
谭忠魁
许青
傅乾
向华
赵林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lam Research Corp
Original Assignee
Lam Research Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Research Corp filed Critical Lam Research Corp
Publication of CN107768233A publication Critical patent/CN107768233A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • C23C16/45544—Atomic layer deposition [ALD] characterized by the apparatus
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/52—Controlling or regulating the coating process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/3244—Gas supply means
    • H01J37/32449—Gas control, e.g. control of the gas flow
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02527—Carbon, e.g. diamond-like carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02557—Sulfides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H01L21/0212—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Analytical Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

本发明涉及用于半导体处理的硅基沉积。提供了一种在处理室中处理衬底的方法，其包括在衬底上形成沉积物。使含硅气体流入处理室。使含COS的气体流入处理室。在处理室中由含硅气体和含COS气体形成等离子体，其中等离子体在衬底上提供沉积物。

Description

用于半导体处理的硅基沉积
技术领域
本发明涉及在半导体晶片上形成半导体器件的方法。更具体地，本公开涉及在半导体器件的形成中形成硅基沉积物。
背景技术
在形成半导体器件中，沉积各种层。
发明内容
为了实现上述内容并且根据本公开的目的，提供了一种用于处理在处理室中的衬底的方法，其包括在所述衬底上形成沉积物。使含硅气体流入所述处理室。使含COS的气体流入所述处理室。在所述处理室中由所述含硅气体和所述含COS气体形成等离子体，其中所述等离子体在所述衬底上提供所述沉积物。
具体而言，本发明的一些方面可以阐述如下：
1.一种用于在处理室中处理衬底的方法，其包括在所述衬底上形成沉积物，所述方法包括：
使含硅气体流入所述处理室；
使含COS气体流入所述处理室；以及
在所述处理室中由所述含硅气体和所述含COS气体形成等离子体，其中所述等离子体在所述衬底上提供所述沉积物。
2.根据条款1所述的方法，其中所述沉积物包括硅、氧和硫。
3.根据条款2所述的方法，其中所述沉积物还包含碳。
4.根据条款3所述的方法，其还包括在所述衬底上形成所述沉积物之后蚀刻所述沉积物下方的蚀刻层。
5.根据条款4所述的方法，其还包括在所述衬底上形成所述沉积物之前在所述蚀刻层中部分地蚀刻特征，其中图案化掩模位于所述蚀刻层的上方，并且其中所述沉积物在所述特征的侧壁的至少部分上。
6.根据条款5所述的方法，其还包括去除所述沉积物。
7.根据条款6所述的方法，其中去除所述沉积物包括：
提供包含含卤素组分和O2的去除气体；以及
由所述去除气体形成等离子体，从而去除所述沉积物。
8.根据条款7所述的方法，其中所述含硅气体包括SiH4、SiF4、SiCl4、SiHxFy、SiHxCly、SiFxCly中的至少一种，其中x和y是正整数并且x+y＝4。
9.根据条款3所述的方法，其中同时提供所述含硅气体和所述含COS气体。
10.根据条款3所述的方法，其中依次提供所述含硅气体和所述含COS气体，其中在所述含硅气体和所述含COS气体之间存在一些混合。
11.根据条款3所述的方法，其中循环地提供所述含硅气体和所述含COS气体持续多个循环，其中在所述含硅气体和所述含COS气体之间存在一些混合。
12.根据条款1所述的方法，其还包括在所述衬底上形成所述沉积物之后蚀刻所述沉积物下方的蚀刻层。
13.根据条款12所述的方法，其还包括在所述衬底上形成所述沉积物之前在所述蚀刻层中部分地蚀刻特征，其中图案化掩模在所述蚀刻层的上方，并且其中所述沉积物在所述特征的侧壁的至少部分上。
14.根据条款13所述的方法，其还包括去除所述沉积物。
15.根据条款14所述的方法，其中去除所述沉积物包括：
提供包含含卤素组分和O2的去除气体；以及
由所述去除气体形成等离子体，从而去除所述沉积物。
16.根据条款1所述的方法，其中所述含硅气体包括SiH4、SiF4、SiCl4、SiHxFy、SiHxCly、SiFxCly中的至少一种，其中x和y是正整数并且x+y＝4。
17.根据条款1所述的方法，其中同时提供所述含硅气体和所述含COS气体。
18.根据条款1所述的方法，其中依次提供所述含硅气体和所述含COS气体，其中在所述含硅气体和所述含COS气体之间存在一些混合。
19.根据条款1所述的方法，其中循环地提供所述含硅气体和所述含COS气体持续多个循环，其中在所述含硅气体和所述含COS气体之间存在一些混合。
20.根据条款1所述的方法，其还包括去除所述沉积物。
下面将在实施方式的详细描述中并结合以下附图更详细地描述本公开的这些和其它特征。
附图说明
本发明以示例性而非限制的方式在附图中示出，其中相同的附图标记表示相似的元件，其中：
图1是一个实施方式的高级流程图。
图2A-E是根据一个实施方式处理的堆叠的示意性横截面图。
图3是可以在实施方式中使用的蚀刻室的示意图。
图4是可以用于实施一个实施方式的计算机系统的示意图。
图5是沉积层形成步骤的详细流程图。
具体实施方式
现在将参照附图中所示的几个优选实施方式来详细描述本实施方式。在下面的描述中，阐述了许多具体细节以便提供对本发明的透彻理解。然而，对于本领域技术人员显而易见的是，可以在没有这些具体细节中的一些或全部的情况下实践本公开。在其他情况下，未详细描述公知的工艺步骤和/或结构，以免不必要地模糊本公开。
图1是一个实施方式的高级流程图。在该实施方式中，将工艺层放置在处理室中(步骤104)。将特征部分地蚀刻到工艺层中(步骤108)。将包含硅、氧和硫的钝化层沉积在部分蚀刻的特征上(步骤112)。继续在工艺层中蚀刻特征(步骤116)。去除钝化层(步骤120)。从处理室中去除工艺层(步骤124)。
实施例
在一个优选实施方式中，工艺层包括ONON(二氧化硅、氮化硅、二氧化硅、氮化硅并重复)堆叠。图2A是衬底208的示意性横截面视图，其中工艺层204在图案化掩模220下方。可以在工艺层204和衬底208之间设置一个或多个层。在该实施方式中，工艺层204是多个存储器堆叠，其由氮化硅层212的顶部上的二氧化硅层(SiO2)216的双层形成。图案化掩模220是碳硬掩模。
图3示意性地示出了根据本发明的一个实施方式的可用于处理工艺层204的等离子体处理系统300的示例。等离子体处理系统300包括具有由室壁352包围的等离子体处理室304的等离子体反应器302。由匹配网络308调谐的等离子体电源306向位于功率窗312附近的TCP线圈310提供功率，以通过提供电感耦合功率在等离子体处理室304中产生等离子体314。TCP线圈(上电源)310可以被配置为在等离子体处理室304内产生均匀的扩散分布。例如，TCP线圈310可被配置为在等离子体314中产生环形功率分布。功率窗312被提供以将TCP线圈310与等离子体处理室304分离，同时允许能量从TCP线圈310传递到等离子体处理室304。由匹配网络318调谐的晶片偏置电压电源316向电极320提供功率，以将偏置电压设置在被支撑在电极320上的工艺层204上。控制器324为等离子体电源306和晶片偏置电压电源316设置点。
等离子体电源306和晶片偏置电压电源316可以被配置为在诸如13.56MHz、27MHz、2MHz、400kHz或其组合之类的特定射频下操作。等离子体电源306和晶片偏置电压电源316可以被适当地设定尺寸以提供一定范围的功率，以便实现期望的工艺性能。例如，在本发明的一个实施方式中，等离子体电源306可以提供在50至5000瓦的范围内的功率，并且晶片偏置电压电源316可以提供在20至2000V的范围内的偏置电压。此外，TCP线圈310和/或电极320可以由两个或更多个子线圈或子电极组成，其可以由单个电源供电或由多个电源供电。
如图3所示，等离子体处理系统300还包括气体源/气体供应机构330。气体源/气体供应机构330将气体提供给喷嘴形式的气体进料336。工艺气体和副产物经由压力控制阀342和泵344从等离子体处理室304中除去，压力控制阀342和泵344还用于保持等离子体处理室304内的特定压力。气体源/气体供应机构330由控制器324控制。可以使用加利福尼亚州弗里蒙特市的Lam Research Corp.生产的Kiyo来实施本发明的实施方式。
图4是示出适用于实现实施方式中使用的控制器324的计算机系统400的高级框图。计算机系统可以具有许多物理形式，范围从集成电路、印刷电路板和小型手持设备到巨大的超级计算机。计算机系统400包括一个或多个处理器402，并且还可以包括(用于显示图形、文本和其他数据的)电子显示设备404、主存储器406(例如，随机存取存储器(RAM))、存储设备408(例如，硬盘驱动器)、可移动存储设备410(例如，光盘驱动器)、用户接口设备412(例如，键盘、触摸屏、小键盘、鼠标或其他定点设备等)和通信接口414(例如，无线网络接口)。通信接口414允许通过链路在计算机系统400和外部设备之间传送软件和数据。系统还可以包括连接到上述设备/模块的通信基础设施416(例如，通信总线、交叉连接条或网络)。
经由通信接口414传送的信息可以是能够通过通信接口414经由承载信号并且可以使用电线或电缆、光纤、电话线、蜂窝电话链路、射频链路和/或其他通信信道实现的通信链路接收的信号(例如，电子、电磁、光学或其他信号)的形式。利用这样的通信接口，可以设想一个或多个处理器402可以在执行上述方法步骤的过程中从网络接收信息或者可以向网络输出信息。此外，方法实施方式可以仅在处理器上执行，或者可以通过诸如因特网之类的网络与共享处理的一部分的远程处理器一起执行。
术语“非瞬态计算机可读介质”通常用于指诸如主存储器、辅助存储器、可移动存储器和存储设备(例如，硬盘、闪速存储器、磁盘驱动器存储器、CD-ROM和其他形式的持久性存储器)之类的介质，不应被解释为涵盖瞬态的主题(如载波或信号)。计算机代码的示例包括诸如由编译器产生的机器代码和包含由计算机使用解释器执行的较高级代码的文件。计算机可读介质也可以是通过体现在载波中的计算机数据信号发送并且表示可由处理器执行的指令序列的计算机代码。
在衬底208已经被放置到等离子体处理系统300中之后，将特征部分地蚀刻到工艺层中(步骤108)。在该示例中，在工艺层204是ONON堆叠的情况下，包含C4F6、O2、NF3、CH2F2的蚀刻气体流入等离子体处理室304并转化成等离子体以蚀刻ONON堆叠。图2B是在特征被部分地蚀刻之后形成具有侧壁228的蚀刻特征224的堆叠200的横截面图。
包含硅、氧和硫的钝化层沉积在工艺层上(步骤112)。图5是沉积钝化层(步骤112)的实施方式的更详细的流程图。使含硅气体流入等离子体处理室304(步骤504)。使含有COS的气体流入等离子体处理室304(步骤508)。在等离子体处理室304中形成等离子体(步骤512)。优选地，等离子体是原位等离子体且非远程的。等离子体引起包含硅、氧和硫的沉积物沉积在工艺层上。优选地，沉积层还包含碳。该工艺的配方的示例使100sccm的SiCl4和100sccm的COS在50mTorr的压强下流入处理室304。以13.56MHz的频率提供2500瓦的等离子体RF功率，从而将SiCl4气体和COS气体转变成等离子体。不提供偏置。该工艺维持10秒。然后通过停止气体流动和RF功率来停止该工艺。对于宽度为约50至100nm的特征，提供钝化至约1至4微米的深度。图2C是在钝化层232已经沉积在工艺层204的蚀刻侧壁228上之后的堆叠200的横截面视图。为了更清楚地示出各种特征，该图未被按比例绘制。
然后继续蚀刻工艺(步骤116)。在该实施方式中，继续蚀刻工艺，直到工艺层被完全蚀刻。这里可以使用类似于用于部分地蚀刻堆叠的配方的蚀刻配方。图2D是在工艺层204被完全蚀刻(步骤116)之后的堆叠200的横截面视图。
去除钝化层(步骤120)。在一个实施方式中，上述蚀刻工艺完全去除钝化层。如果在上述蚀刻工艺之后保留钝化层中的一些，则可以提供单独的钝化去除工艺。用于去除钝化层的配方的一个示例在室压强为20mT的情况下提供100sccm的CF4和20sccm的O2的流动。提供TCP的1000W的RF信号以使气体形成为等离子体。不提供偏置电压。提供30℃的晶片温度。等离子体维持20秒。然后可以停止气体流动和功率。图2E是钝化层已被完全去除(步骤120)之后的堆叠200的横截面图。
从等离子体处理室304去除衬底上的工艺层(步骤124)。可以在从等离子体处理室移除衬底之前或之后执行附加处理。
该实施方式提供了无弯曲的特征，如果在完成蚀刻之前没有提供沉积层，则会导致弯曲。通常，弯曲将由特征顶部附近的侧壁蚀刻引起，其中沉积层已经沉积在侧壁上。因为沉积层对侧壁蚀刻具有高耐受性，所以弯曲减少。优选地，侧壁上的钝化层的厚度小于2nm。
不受理论的限制，相信沉积物沉积包含硅、氧和硫并且其可以进一步包含碳的层。认为这样的沉积层对于用于蚀刻诸如多晶硅、二氧化硅、氮化硅、含金属层(例如掺杂钨)或含碳层之类的导电或介电材料的各种蚀刻工艺是高耐受性的。当单独使用蚀刻剂(例如，O2、Cl2、SF6、NF3、CF4、HBr和CHxFy(其中x和y是正整数))时，沉积层能够抵制使用这种蚀刻剂的蚀刻工艺中的侧壁蚀刻。
在一个实施方式中，使用SiCl4和COS形成等离子体来形成沉积层。已经发现，顺序地、同时地或循环地提供SiCl4和COS已经提供距特征顶部几微米深的钝化。对于不同的蚀刻化学物质，已经发现耐蚀刻性持续20-1000秒。
这种耐蚀刻层提供对蚀刻轮廓、选择性、线边缘粗糙度和微加载的更好控制。在高深宽比特征的情况下，当特征尺寸缩小时，将钝化物质提供到特征深处的目标位置变得更加困难。说明书和权利要求中的高深宽比特征被定义为具有大于20:1的高度比宽度的深宽比。更优选地，使用一个实施方式形成高度与宽度比大于50:1的高深宽比特征。此外，通过一个实施方式提供保持没有弯曲的直线蚀刻轮廓。
如果钝化层不耐蚀刻，则需要更多的钝化，这可能导致蚀刻停止。在各种实施方式中使用的钝化层具有足够的耐蚀刻性，以防止蚀刻停止。由于沉积层对各种蚀刻剂具有耐受性，所以沉积层可用作蚀刻许多不同材料和多层不同材料(例如存储堆叠)的钝化层。
已经发现，沉积层可以通过由含卤素组分气体和氧气形成的等离子体容易地去除。优选地，沉积去除气体包括NF3和O2或CF4和O2。由于存在可以容易且完全去除沉积层的蚀刻剂的组合，所以可以去除沉积层而不损害蚀刻特征并具有高生产量。
在一个实施方式中，其中SiCl4和COS单独地提供并循环地提供几个循环，该工艺可能需要更长时间。然而，对于宽度小于20nm的小特征尺寸，已经发现较好的阶梯覆盖度和共形性。
据信，沉积层由等离子体之间的表面反应形成，因为任何气相反应过程将形成顶部重沉积并且不具有钝化高深宽比特征的能力。虽然据信沉积层由于由COS提供的碳成分而进一步包含碳，但难以测试沉积层以证明碳的存在。还认为钝化层是SiO2、SiC和SiS2的混合物，其中SiS2是沉积层结构的主链(backbone)。SiS2是可以形成交联结构的聚合物材料，其可以耐氟、氯或氧自由基。SiO2和SiC用作该聚合物中的填料，以制造致密化的薄膜来阻止反应性物质的化学扩散。
实验已经表明，与包括SiO2、SiN或Si的原子层沉积(ALD)膜的其它沉积和钝化工艺相比，多个实施方式提供优异且改进的阶梯覆盖。多个实施方式显示了对于导电工艺层和介电工艺层两者的改进的钝化。多个实施方式还显示出提高的产量，因为5至100秒的沉积将提供用于蚀刻ONON层持续约200至1000秒的弯曲保护(bow protection)。这样的沉积可以在形成存储器的过程中用于介质电池蚀刻中。
各种实施方式提供不是自限制的沉积层，因此不使用原子层沉积。结果，在各种实施方式中这种沉积层的形成比使用原子层沉积形成沉积层要快得多。沉积速率随时间和等离子体功率的变化而变化。此外，在循环和顺序的实施方式中，本发明的实施方式不需要ALD用来防止气体混合所需的吹扫。不需要吹扫，因为如果气体有一些混合物不是不利的。消除吹扫的需要甚至可以提供更快的工艺。此外，所述沉积提供比常规化学气相沉积(CVD)更好的沉积。
在各种实施方式中，含硅气体可以是包括SiH4、SiF4、SiCl4、SiHxFy、SiHxCly、SiFxCly(其中x和y是正整数并且x+y＝4)中的至少一种的含硅气体中的至少一种。优选地，含硅气体是SiCl4。
除了侧壁钝化之外，其它实施方式可以使用包含硅、氧和硫的沉积层用于其它用途。例如，沉积层可以用作蚀刻掩模。在另一个实施方式中，沉积层可以用作间隔件。这种间隔件可用于形成翅形结构。这样的沉积可以相对于后续工艺原位或非原位进行。
虽然已经根据几个优选实施方式描述了本公开，但是存在落入本公开的范围内的改变、修改、置换和各种替代等同方案。还应当注意，存在实现本公开的方法和装置的许多替代方式。因此，以下所附权利要求旨在被解释为包括落在本公开的真实精神和范围内的所有这样的改变、修改、置换和各种替代等同方案。

Claims (10)

1.一种用于在处理室中处理衬底的方法，其包括在所述衬底上形成沉积物，所述方法包括：
使含硅气体流入所述处理室；
使含COS气体流入所述处理室；以及
在所述处理室中由所述含硅气体和所述含COS气体形成等离子体，其中所述等离子体在所述衬底上提供所述沉积物。
2.根据权利要求1所述的方法，其中所述沉积物包括硅、氧和硫。
3.根据权利要求2所述的方法，其中所述沉积物还包含碳。
4.根据权利要求3所述的方法，其还包括在所述衬底上形成所述沉积物之后蚀刻所述沉积物下方的蚀刻层。
5.根据权利要求4所述的方法，其还包括在所述衬底上形成所述沉积物之前在所述蚀刻层中部分地蚀刻特征，其中图案化掩模位于所述蚀刻层的上方，并且其中所述沉积物在所述特征的侧壁的至少部分上。
6.根据权利要求5所述的方法，其还包括去除所述沉积物。
7.根据权利要求6所述的方法，其中去除所述沉积物包括：
提供包含含卤素组分和O2的去除气体；以及
由所述去除气体形成等离子体，从而去除所述沉积物。
8.根据权利要求7所述的方法，其中所述含硅气体包括SiH4、SiF4、SiCl4、SiHxFy、SiHxCly、SiFxCly中的至少一种，其中x和y是正整数并且x+y＝4。
9.根据权利要求3所述的方法，其中同时提供所述含硅气体和所述含COS气体。
10.根据权利要求3所述的方法，其中依次提供所述含硅气体和所述含COS气体，其中在所述含硅气体和所述含COS气体之间存在一些混合。
CN201710695559.4A 2016-08-23 2017-08-15 用于半导体处理的硅基沉积 Pending CN107768233A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/244,311 US10658194B2 (en) 2016-08-23 2016-08-23 Silicon-based deposition for semiconductor processing
US15/244,311 2016-08-23

Publications (1)

Publication Number Publication Date
CN107768233A true CN107768233A (zh) 2018-03-06

Family

ID=61243353

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710695559.4A Pending CN107768233A (zh) 2016-08-23 2017-08-15 用于半导体处理的硅基沉积

Country Status (4)

Country Link
US (1) US10658194B2 (zh)
KR (1) KR20180022572A (zh)
CN (1) CN107768233A (zh)
TW (1) TW201820388A (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI790327B (zh) * 2017-12-08 2023-01-21 日商東京威力科創股份有限公司 使用原子層沉積保護層的高深寬比介層窗蝕刻
JP6811202B2 (ja) * 2018-04-17 2021-01-13 東京エレクトロン株式会社 エッチングする方法及びプラズマ処理装置
WO2020096808A1 (en) * 2018-11-05 2020-05-14 Lam Research Corporation Method for etching an etch layer
JP7229033B2 (ja) * 2019-02-01 2023-02-27 東京エレクトロン株式会社 基板処理方法及び基板処理装置
JP7339032B2 (ja) * 2019-06-28 2023-09-05 東京エレクトロン株式会社 基板処理方法および基板処理装置
WO2023215040A1 (en) * 2022-05-02 2023-11-09 Lam Research Corporation Co-deposition and etch process
WO2024044217A1 (en) * 2022-08-25 2024-02-29 Lam Research Corporation High aspect ratio etch with a re-deposited helmet mask

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101131927A (zh) * 2006-08-22 2008-02-27 兰姆研究有限公司 增强等离子体蚀刻性能的方法
US8815685B2 (en) * 2013-01-31 2014-08-26 GlobalFoundries, Inc. Methods for fabricating integrated circuits having confined epitaxial growth regions
CN104364886A (zh) * 2012-07-10 2015-02-18 东京毅力科创株式会社 等离子体处理方法和等离子体处理装置
US9076735B2 (en) * 2013-11-27 2015-07-07 Globalfoundries Singapore Pte. Ltd. Methods for fabricating integrated circuits using chemical mechanical polishing

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5545290A (en) 1987-07-09 1996-08-13 Texas Instruments Incorporated Etching method
US7977390B2 (en) * 2002-10-11 2011-07-12 Lam Research Corporation Method for plasma etching performance enhancement
US7141505B2 (en) 2003-06-27 2006-11-28 Lam Research Corporation Method for bilayer resist plasma etch
GB0401622D0 (en) 2004-01-26 2004-02-25 Oxford Instr Plasma Technology Plasma etching process
US7517804B2 (en) * 2006-08-31 2009-04-14 Micron Technologies, Inc. Selective etch chemistries for forming high aspect ratio features and associated structures
US8747684B2 (en) * 2009-08-20 2014-06-10 Applied Materials, Inc. Multi-film stack etching with polymer passivation of an overlying etched layer
US9793126B2 (en) * 2010-08-04 2017-10-17 Lam Research Corporation Ion to neutral control for wafer processing with dual plasma source reactor
JP5995729B2 (ja) * 2011-02-17 2016-09-21 古河電気工業株式会社 光コネクタ用フェルール
US9018103B2 (en) * 2013-09-26 2015-04-28 Lam Research Corporation High aspect ratio etch with combination mask

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101131927A (zh) * 2006-08-22 2008-02-27 兰姆研究有限公司 增强等离子体蚀刻性能的方法
CN104364886A (zh) * 2012-07-10 2015-02-18 东京毅力科创株式会社 等离子体处理方法和等离子体处理装置
US8815685B2 (en) * 2013-01-31 2014-08-26 GlobalFoundries, Inc. Methods for fabricating integrated circuits having confined epitaxial growth regions
US9076735B2 (en) * 2013-11-27 2015-07-07 Globalfoundries Singapore Pte. Ltd. Methods for fabricating integrated circuits using chemical mechanical polishing

Also Published As

Publication number Publication date
KR20180022572A (ko) 2018-03-06
US10658194B2 (en) 2020-05-19
TW201820388A (zh) 2018-06-01
US20180061659A1 (en) 2018-03-01

Similar Documents

Publication Publication Date Title
CN107768233A (zh) 用于半导体处理的硅基沉积
KR102447088B1 (ko) 반도체 디바이스 제작에서의 주석 옥사이드 막들
JP7210538B2 (ja) 周期的な不動態化およびエッチングを使用する高アスペクト比の選択的横方向エッチング
US9865472B2 (en) Fabrication of a silicon structure and deep silicon etch with profile control
US10615169B2 (en) Selective deposition of SiN on horizontal surfaces
JP7320085B2 (ja) 交互のエッチングプロセスおよび不動態化プロセス
JP2016139792A (ja) 異方性タングステンエッチングのための方法および装置
TW201801184A (zh) 蝕刻介電層中之特徵部的方法
CN107919264A (zh) 有关有机掩模的用于选择性地蚀刻氧化硅的方法
CN104576355B (zh) 等离子体处理方法
TWI745447B (zh) 具有降低的深寬比依存性之選擇性蝕刻方法
KR20220166316A (ko) 준금속 (metalloid) 또는 금속 함유 하드마스크의 증착을 사용한 선택적인 에칭
CN105321816A (zh) 蚀刻含钨层的方法
TWI576909B (zh) 絕緣層上矽蝕刻
CN113892168A (zh) 蚀刻停止层
JP2022538595A (ja) 選択的不動態化のために標的蒸着を用いてフィーチャをエッチングするための方法
TWI838003B (zh) 半導體裝置製造中之氧化錫膜
KR102675485B1 (ko) 수평 표면들 상에 SiN의 선택적인 증착
CN110520964A (zh) 用于半导体处理的基于硅的沉积

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20180306