TWI758404B - 氫活化原子層蝕刻 - Google Patents
氫活化原子層蝕刻 Download PDFInfo
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- TWI758404B TWI758404B TW107103919A TW107103919A TWI758404B TW I758404 B TWI758404 B TW I758404B TW 107103919 A TW107103919 A TW 107103919A TW 107103919 A TW107103919 A TW 107103919A TW I758404 B TWI758404 B TW I758404B
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- 238000005530 etching Methods 0.000 title claims abstract description 45
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 title description 2
- 229910052739 hydrogen Inorganic materials 0.000 title description 2
- 239000001257 hydrogen Substances 0.000 title description 2
- 229920002313 fluoropolymer Polymers 0.000 claims abstract description 65
- 230000008021 deposition Effects 0.000 claims abstract description 44
- 230000004913 activation Effects 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 32
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 16
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 11
- 239000011737 fluorine Substances 0.000 claims abstract description 11
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims abstract description 6
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims abstract 5
- 238000000151 deposition Methods 0.000 claims description 41
- 238000012545 processing Methods 0.000 claims description 28
- 230000003213 activating effect Effects 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 239000007789 gas Substances 0.000 description 58
- 238000001994 activation Methods 0.000 description 28
- 238000010586 diagram Methods 0.000 description 12
- 238000004891 communication Methods 0.000 description 11
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 10
- 239000000758 substrate Substances 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 125000004122 cyclic group Chemical group 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- -1 silicon nitrides Chemical class 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000002085 persistent effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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Abstract
提供相對於一結構中的SiGe或Si而選擇性蝕刻SiO與SiN的方法。提供原子層蝕刻的複數循環,其中各循環包含氟化聚合物沉積階段與活化階段。氟化聚合物沉積階段包含:使氟化聚合物沉積氣體流動,該氟化聚合物沉積氣體包含氟碳化物氣體;使氟化聚合物沉積氣體形成為電漿,其在該結構上沉積氟碳化物聚合物層;及使氟化聚合物沉積氣體的流動停止。活化階段包含:使活化氣體流動,該活化氣體包含惰性轟擊氣體與H2
;使活化氣體形成為電漿,其中惰性轟擊氣體活化氟化聚合物中的氟,該氟連同來自H2
的電漿成分一起造成SiO與SiN相對於SiGe與Si而受到選擇性蝕刻;及使活化氣體的流動停止。
Description
本揭露內容關於在半導體晶圓上形成半導體元件的方法。更具體而言,本揭露內容關於在形成半導體元件過程中蝕刻矽氧化物與矽氮化物。
在形成半導體元件的過程中,特徵部可受到蝕刻,其中矽氧化物與矽氮化物係受到蝕刻。
為達成先前所述以及根據本揭露內容之目的,提供在電漿處理腔室中相對於一結構中的SiGe與Si而選擇性蝕刻SiO與SiN的方法。提供原子層蝕刻的複數循環,其中各循環包含氟化聚合物沉積階段與活化階段。氟化聚合物沉積階段包含:使氟化聚合物沉積氣體流入電漿處理腔室內,該氟化聚合物沉積氣體包含氟碳化物氣體;使氟化聚合物沉積氣體形成為電漿,其在該結構上沉積氟碳化物聚合物層;及使氟化聚合物沉積氣體停止流入電漿處理腔室內。活化階段包含:使活化氣體流入電漿處理腔室中,該活化氣體包含惰性轟擊氣體與H2
;使活化氣體形成為電漿,其中惰性轟擊氣體活化在氟化聚合物中的氟,該氟連同來自H2
的電漿成分一起造成SiO與SiN相對於SiGe與Si而受到選擇性蝕刻;及使活化氣體停止流入電漿處理腔室內。沉積與活化階段可包含其中條件改變的若干步驟。藉由將H2
取代為例如像是NH3
之含有氫的氣體,可獲得類似的結果。
本揭露內容之此等及其他特徵將於以下「實施方式」中、並結合下列圖示而加以詳述。
本揭露內容現將參照如隨附圖式中所說明的幾個較佳實施例詳細描述。在以下說明中,為了提供本揭露內容的透徹理解,說明許多具體細節。然而,顯然地,對於熟習本項技術之人士而言,本揭露內容可不具有某些或全部這些具體細節而實施。另一方面,為了不要不必要地模糊本揭露內容,未詳細說明眾所周知的製程步驟及/或結構。
圖1為實施例的高階流程圖。在此實施例中,將具有一結構(例如堆疊)的基板置放在電漿處理腔室中(步驟104)。提供循環的原子層蝕刻(步驟108)。原子層蝕刻製程的各循環包含氟化聚合物沉積階段(步驟112)與活化階段(步驟116)。將具有該結構的基板從電漿處理腔室移除(步驟120)。圖2為氟化聚合物沉積階段(步驟112)的更詳細的流程圖。使氟化聚合物沉積氣體流入電漿處理腔室內(步驟204)。使氟化聚合物沉積氣體形成為電漿,其將氟碳化物聚合物沉積在該結構上(步驟208)。停止氟化聚合物沉積氣體流入(步驟212)。圖3為活化階段(步驟116)的更詳細的流程圖。使活化氣體流入電漿處理腔室內,其中活化氣體包含惰性轟擊氣體與H2
(步驟304)。使活化氣體形成為電漿,其活化氟化聚合物中的氟,該氟連同來自H2
的電漿成分一起造成SiO與SiN相對於SiGe與Si而受到選擇性蝕刻(步驟308)。在說明書與申請項中,SiGe與Si包括摻雜的與未摻雜的SiGe與Si。停止活化氣體流入(步驟312)。範例
在範例中,將帶有一結構的基板置放在電漿處理腔室中(步驟104)。圖4A為例如堆疊之結構400的示意橫剖面圖,該結構400具有在矽層408之下的矽基板404,以及接觸部結構412及閘極結構418。閘極結構418為金屬的閘極結構。SiN之塗覆的蝕刻停止層(CESL)420已經保形地沉積在閘極結構418與接觸部結構412之上。SiO之介電層424係在CESL 420上方。硬遮罩428係形成在介電層424之上。
圖5為可使用於實施例中之電漿處理腔室的示意圖。在一或更多實施例中,電漿處理系統500包含包含設置氣體入口之氣體散佈板506與靜電卡盤(ESC)508,氣體散佈板506與ESC 508係在由腔室牆550圍起的處理腔室549之內。在處理腔室549內,基板404定位在ESC 508的頂部。ESC 508可提供來自ESC源548的偏壓。氣體源510經由散佈板506連接至電漿處理腔室549。在此實施例中,氣體源510包含H2
氣體源512、惰性轟擊氣體源516及沉積氣體源518。氣體源510可具有額外的氣體源。各氣體源可包含複數氣體源。ESC溫度控制器551連接至ESC 508且提供ESC 508的溫度控制。在此範例中,第一連接件513提供功率至內部加熱器511以加熱ESC 508的內部區域,且第二連接件514提供功率至外部加熱器515以加熱ESC 508的外部區域。RF源530提供RF功率至下電極534與上電極,在此實施例中該上電極為氣體散佈板506。在較佳的實施例中,2 MHz、60 MHz及可選的27 MHz功率源構成RF源530與ESC源548。在此實施例中,一產生器提供各頻率。在其他實施例中,該等產生器可在分開的RF源中,或分開的RF產生器可連接至不同的電極。例如,上電極可具有連接至不同RF源之內部與外部電極。RF源與電極的其他配置可用在其他實施例中,例如在另一實施例中,上電極可接地。控制器535可控制地連接至RF源530、ESC源548、排氣泵浦520與蝕刻氣體源510。如此電漿處理腔室的範例為Fremont, CA的Lam Research Corporation 所製造的Exelan FlexTM蝕刻系統。製程腔室可為CCP(電容耦合電漿)反應器或ICP(電感耦合電漿)反應器。
圖6為顯示電腦系統600的高階方塊圖,其合適於實施在實施例中使用的控制器535。電腦系統可具有許多實體形式,其範圍從積體電路、印刷電路板與小型手持裝置上至大型超級電腦。電腦系統600包括一或更多處理器602且進一步可包括電子顯示裝置604(用於顯示圖形、文字與其他數據)、主記憶體606(例如,隨機存取記憶體(RAM))、儲存裝置608(例如,硬碟裝置)、可移除式儲存裝置610(例如,光碟機)、使用者介面裝置612(例如,鍵盤、觸控螢幕、小鍵盤、滑鼠或其他指向裝置等等)、及通訊介面614(例如,無線網路介面)。通訊介面614容許軟體與數據在電腦系統600與外部裝置之間經由連線來轉移。系統亦可包括前述裝置/模組連接至其上的通訊基礎結構616(例如,通訊匯流排、縱橫條(cross-over bar)、或網路)。
經由通訊介面614傳輸的資訊可為訊號之形式,例如能夠經由通訊連結而被通訊介面614接收的電子、電磁、光學、或其他訊號,該通訊連結攜帶訊號且可藉由使用導線或纜線、光纖、電話線、行動電話連結、射頻連結、及/或其他通訊通道加以實現。在使用此種通訊介面之情況下,吾人預期該一或更多處理器602可於執行上述方法步驟期間內從網路接收資訊、或可將資訊輸出至網路。此外,方法實施例可僅在該等處理器上執行,或可透過網路(例如,網際網路)而結合遠端處理器(其分擔一部分的處理)執行。
術語「非暫態電腦可讀媒體」通常係用以意指媒體,例如主記憶體、輔助記憶體、可移除式儲存裝置及儲存裝置(例如硬碟)、快閃記憶體、磁碟機記憶體、CD-ROM、及其他形式的持續性記憶體,且不應被理解為涵蓋暫時性標的(例如,載波或訊號)。電腦碼之範例包含機器碼(例如藉由編譯器產生者)、及含有較高階碼的檔案,該較高階的碼係藉由使用解譯器的電腦而執行。電腦可讀媒體亦可為藉由電腦數據訊號而傳輸的電腦碼,該電腦數據訊號係包含在載波中且代表了可由處理器執行之指令的序列。
在具有基板404的結構400已經被置放進電漿處理腔室549之後,提供循環的原子層蝕刻(步驟108)。原子層蝕刻製程的各循環包含氟化聚合物沉積階段(步驟112)與活化階段(步驟116)。圖2為氟化聚合物沉積階段(步驟112)的更詳細的流程圖。使氟化聚合物沉積氣體流入電漿處理腔室內(步驟204)。在此實施例中,使氟化聚合物沉積氣體流動的步驟使C4
F6
在2至20 sccm之間流動、使O2
在2至20 sccm之間流動、使CO在10至200 sccm之間流動以及使Ar在100至1000 sccm之間流動。使氟化聚合物沉積氣體形成為電漿,其將氟碳化物聚合物沉積在該結構上(步驟208)。在此實施例中,在27 MHz下提供30-200瓦特的RF功率,並在60 MHz下提供30-200瓦特的RF功率。提供範圍從-30至-200伏特的偏壓以加速至結構400的電漿成分以提供沉積。在2至20秒之後,停止氟化聚合物沉積氣體流入(步驟212)。
圖4B為在氟化聚合物沉積階段完成之後結構400的示意橫剖面圖。氟化聚合物的薄保形層或塗層432係沉積在結構400上。氟化聚合物的塗層432未依比例描繪,而是描繪得更厚以較好地促進理解。在此實施例中,在一些情況下,可在沉積階段的期間觀察到基板的蝕刻,但此階段的主要目的並非蝕刻,而是沉積氟化聚合物的塗層432。
圖3為活化階段(步驟116)的更詳細的流程圖。使活化氣體流入電漿處理腔室內,其中活化氣體包含一或更多惰性轟擊氣體與H2
(步驟304)。在此範例中,活化氣體為100-800 sccm Ar與10-200 sccm H2
。使活化氣體形成為電漿,其活化在氟化聚合物中的氟,該氟連同來自H2
的電漿成分一起造成SiO與SiN相對於SiGe或Si或摻雜的Si而受到選擇性蝕刻(步驟308)。在此實施例中,在27 MHz下提供50-200瓦特的RF功率,並在60 MHz下提供60-200瓦特的RF功率。提供-200伏特的偏壓以加速電漿成分至結構400以造成活化。在3至8秒之後,停止活化氣體流入(步驟312)。
圖4C為在活化階段完成之後,結構400的示意橫剖面圖。由惰性轟擊氣體產生的電漿活化在氟化聚合物中的氟,該氟連同來自H2
的電漿成分一起造成部分的介電層424受到蝕刻。顯示蝕刻去除介電層424的一層。
循環的製程係重複許多次。在此範例中,製程係重複從10至20次。圖4D為在原子層蝕刻已經執行超過10個循環之後,結構400的示意橫剖面圖。原子層蝕刻相對於閘極結構418、矽層408及SiGe或Si接觸部結構412而選擇性蝕刻SiO與SiN層。在此範例中,餘留下形成於中央的閘極結構418上方的一層SiN 420。這是因為SiN的原子層蝕刻為深寬比相依—在具有較低高度對寬度深寬比之SiN的區域中蝕刻SiN較慢,且也因為氟化聚合物在金屬閘極結構418上沉積得較厚。這導致在具有較高深寬比之接觸部結構412上方的SiN的蝕刻較快。
在其他實施例中,氟化聚合物沉積氣體可為C4
F8
、CF4
、C5
F8
或CH3
F。除了氟碳化物之外,氟化聚合物沉積氣體可更包含CO、O2
、CO2
及/或像是Ar的惰性氣體。CO在具有低深寬比的區域的頂部上提供比具有高深寬比的區域更多的碳沉積,其進一步減慢在低深寬比區域中SiN的蝕刻。在其他實施例中,惰性轟擊氣體可為例如He之另一鈍氣,而非Ar。然而,惰性轟擊氣體僅限於鈍氣。較佳是,惰性轟擊氣體的體積流量相對於H2
的體積流量的比率係在2:1至20:1的範圍中。更佳是,惰性轟擊氣體的體積流量相對於H2
的體積流量的比率係在8:1至15:1的範圍中。較佳是,活化氣體為無氟的。較佳是,在氟化聚合物沉積階段與活化階段期間之偏壓電壓具有在30至500伏特之間的大小。更佳是,在氟化聚合物沉積階段與活化階段期間之偏壓電壓具有在100至250伏特之間的大小。這意謂偏壓電壓的絕對值係在30至500伏特之間,且更佳是在100至250伏特之間。不同的實施例提供SiN的深寬比相依的蝕刻,其相較於在較低的深寬比下的SiN,選擇性蝕刻在較高的深度對寬度深寬比下的SiN。
在氟化聚合物中的氟係受到活化以蝕刻SiO2
。在活化期間亦需要H2
的存在以蝕刻SiN。在沒有H2
的情況下,SiN將蝕刻緩慢或將不受到蝕刻。在其他實施例中,NH3
可用以取代H2
,儘管H2
係較佳的。氟化聚合物的量或厚度提供活化階段期間蝕刻量的自限制性。在說明書與申請專利範圍中,原子層蝕刻定義為自限制的蝕刻製程,例如,由於氟化聚合物的有限存在而導致的活化製程的的自限制性。
吾人出人意料地發現,不同的實施例能夠提供小的臨界尺寸蝕刻包繞(etch wrap around),其容許在結構周圍進行蝕刻然後繞過該結構。較佳是,以至少5:1的比率,相對於SiGe與Si而選擇性蝕刻SiO。更佳是,以至少10:1的比率,相對於SiGe與Si而選擇性蝕刻SiO。較佳是,以至少5:1的比率,相對於SiGe與Si而選擇性蝕刻SiN。更佳是,以至少10:1的比率,相對於SiGe與Si而選擇性蝕刻SiN。在不同的實施例中,摻雜的Si可為摻雜碳的矽或P摻雜的Si,且摻雜的SiGe可摻雜硼。
雖然本揭露內容已由幾個較佳的實施例加以描述,但仍存在變更、修改、置換、及各種替代等同物,其皆落入本揭露內容的範疇之內。亦應注意有許多替代的方式實施本揭露內容的方法及設備。因此,下列隨附申請專利範圍意欲被解釋為包含落入本揭露內容的真實精神及範圍內的所有這些變更、修改、置換及各種替代等同物。
104‧‧‧步驟108‧‧‧步驟112‧‧‧步驟116‧‧‧步驟120‧‧‧步驟204‧‧‧步驟208‧‧‧步驟212‧‧‧步驟304‧‧‧步驟308‧‧‧步驟312‧‧‧步驟400‧‧‧結構404‧‧‧基板408‧‧‧矽層412‧‧‧接觸部結構418‧‧‧閘極結構420‧‧‧蝕刻停止層(CESL)424‧‧‧介電層428‧‧‧硬遮罩432‧‧‧氟化聚合物的塗層500‧‧‧電漿處理系統506‧‧‧氣體散佈板508‧‧‧靜電卡盤(ESC)510‧‧‧氣體源511‧‧‧內部加熱器512‧‧‧H2
氣體源515‧‧‧外部加熱器513‧‧‧第一連接件514‧‧‧第二連接件516‧‧‧惰性轟擊氣體源518‧‧‧沉積氣體源520‧‧‧排氣泵浦530‧‧‧RF源534‧‧‧下電極535‧‧‧控制器548‧‧‧ESC源549‧‧‧處理腔室550‧‧‧腔室牆551‧‧‧ESC溫度控制器600‧‧‧電腦系統602‧‧‧處理器604‧‧‧顯示裝置606‧‧‧記憶體608‧‧‧儲存裝置610‧‧‧可移除式儲存裝置612‧‧‧使用者介面裝置614‧‧‧通訊介面616‧‧‧通訊基礎結構
在隨附圖式的圖中,本揭露內容係以示例為目的而不是以限制為目的加以說明,且其中類似的參考數字係關於相似的元件,且其中:
圖1為實施例的高階流程圖。
圖2為氟化聚合物沉積階段的更詳細的流程圖。
圖3為活化階段的更詳細的流程圖。
圖4A-D為根據實施例處理的結構的示意橫剖面圖。
圖5為可使用於實施例中之電漿處理腔室的示意圖。
圖6為可使用於實施一實施例之電腦系統的示意圖。
104‧‧‧步驟
108‧‧‧步驟
112‧‧‧步驟
116‧‧‧步驟
120‧‧‧步驟
Claims (18)
- 一種蝕刻方法,用以在一電漿處理腔室中相對於一結構中的SiGe或Si而選擇性蝕刻SiO與SiN,該方法包含提供原子層蝕刻的複數循環,其中各循環包含:氟化聚合物沉積階段,包含:使氟化聚合物沉積氣體流入該電漿處理腔室內,該氟化聚合物沉積氣體包含氟碳化物氣體;使該氟化聚合物沉積氣體形成為電漿,其在該結構上沉積一氟化聚合物的一氟化聚合物層;及使該氟化聚合物沉積氣體停止流入該電漿處理腔室內;及活化階段,包含:使一活化氣體流入該電漿處理腔室中,該活化氣體包含NH3或H2任一者及一惰性轟擊氣體;使該活化氣體形成為電漿,其中該惰性轟擊氣體活化在該氟化聚合物中的氟,該氟連同來自NH3或H2的電漿成分一起造成SiO與SiN相對於SiGe與Si而受到選擇性蝕刻;及使該活化氣體停止流入該電漿處理腔室內。
- 如申請專利範圍第1項之蝕刻方法,其中該活化氣體包含一惰性轟擊氣體與H2。
- 如申請專利範圍第2項之蝕刻方法,其中該活化氣體為無氟的。
- 如申請專利範圍第3項之蝕刻方法,其中該氟化聚合物沉積階段提供在30至500伏特之間的一偏壓電壓,且該活化階段提供在30至500伏特之間的一偏壓電壓。
- 如申請專利範圍第4項之蝕刻方法,其中該氟化聚合物沉積氣體更包含CO。
- 如申請專利範圍第5項之蝕刻方法,其中該氟碳化物氣體為C4F6氣體。
- 如申請專利範圍第6項之蝕刻方法,其中該惰性轟擊氣體為Ar。
- 如申請專利範圍第7項之蝕刻方法,其中在該活化階段期間來自該氟化聚合物的氟係用於蝕刻而使得該活化階段係相依於所沉積的該氟化聚合物的厚度而為自限制性。
- 如申請專利範圍第8項之蝕刻方法,其中該結構更包含閘極結構,其中該原子層蝕刻相對於該閘極結構而選擇性蝕刻SiO與SiN。
- 如申請專利範圍第9項之蝕刻方法,其中該閘極結構包含金屬且其中該氟化聚合物相對於SiO與SiN而優先地沉積在該閘極結構上。
- 如申請專利範圍第10項之蝕刻方法,其中該氟化聚合物相對於高度對深度深寬比較高的特徵部而優先地沉積在高度對寬度深寬比較低的特徵部上。
- 如申請專利範圍第1項之蝕刻方法,其中該氟化聚合物沉積階段提供在30至500伏特之間的一偏壓電壓,且該活化階段提供在30至500伏特之間的一偏壓電壓。
- 如申請專利範圍第1項之蝕刻方法,其中該氟化聚合物沉積氣體更包含CO。
- 如申請專利範圍第1項之蝕刻方法,其中該氟碳化物氣體為C4F6氣體。
- 如申請專利範圍第1項之蝕刻方法,其中該惰性轟擊氣體為Ar。
- 如申請專利範圍第1項之蝕刻方法,其中在該活化階段期間來自該氟化聚合物的氟係用於蝕刻而使得該活化階段係相依於所沉積的該氟化聚合物的厚度而為自限制性。
- 如申請專利範圍第1項之蝕刻方法,其中該結構更包含閘極結構,其中該閘極結構包含金屬,且其中該氟化聚合物相對於SiO與SiN而優先地沉積在該閘極結構上。
- 如申請專利範圍第1項之蝕刻方法,其中該氟化聚合物相對於高度對深度深寬比較高的特徵部而優先地沉積在高度對寬度深寬比較低的特徵部上。
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Families Citing this family (78)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10283321B2 (en) | 2011-01-18 | 2019-05-07 | Applied Materials, Inc. | Semiconductor processing system and methods using capacitively coupled plasma |
US9132436B2 (en) | 2012-09-21 | 2015-09-15 | Applied Materials, Inc. | Chemical control features in wafer process equipment |
US10256079B2 (en) | 2013-02-08 | 2019-04-09 | Applied Materials, Inc. | Semiconductor processing systems having multiple plasma configurations |
US9362130B2 (en) | 2013-03-01 | 2016-06-07 | Applied Materials, Inc. | Enhanced etching processes using remote plasma sources |
US9309598B2 (en) | 2014-05-28 | 2016-04-12 | Applied Materials, Inc. | Oxide and metal removal |
US9966240B2 (en) | 2014-10-14 | 2018-05-08 | Applied Materials, Inc. | Systems and methods for internal surface conditioning assessment in plasma processing equipment |
US9355922B2 (en) | 2014-10-14 | 2016-05-31 | Applied Materials, Inc. | Systems and methods for internal surface conditioning in plasma processing equipment |
US11637002B2 (en) | 2014-11-26 | 2023-04-25 | Applied Materials, Inc. | Methods and systems to enhance process uniformity |
US10224210B2 (en) | 2014-12-09 | 2019-03-05 | Applied Materials, Inc. | Plasma processing system with direct outlet toroidal plasma source |
US10573496B2 (en) | 2014-12-09 | 2020-02-25 | Applied Materials, Inc. | Direct outlet toroidal plasma source |
US11257693B2 (en) | 2015-01-09 | 2022-02-22 | Applied Materials, Inc. | Methods and systems to improve pedestal temperature control |
US9728437B2 (en) | 2015-02-03 | 2017-08-08 | Applied Materials, Inc. | High temperature chuck for plasma processing systems |
US20160225652A1 (en) | 2015-02-03 | 2016-08-04 | Applied Materials, Inc. | Low temperature chuck for plasma processing systems |
US9691645B2 (en) | 2015-08-06 | 2017-06-27 | Applied Materials, Inc. | Bolted wafer chuck thermal management systems and methods for wafer processing systems |
US9741593B2 (en) | 2015-08-06 | 2017-08-22 | Applied Materials, Inc. | Thermal management systems and methods for wafer processing systems |
US9349605B1 (en) | 2015-08-07 | 2016-05-24 | Applied Materials, Inc. | Oxide etch selectivity systems and methods |
US10504700B2 (en) | 2015-08-27 | 2019-12-10 | Applied Materials, Inc. | Plasma etching systems and methods with secondary plasma injection |
US10504754B2 (en) | 2016-05-19 | 2019-12-10 | Applied Materials, Inc. | Systems and methods for improved semiconductor etching and component protection |
US10522371B2 (en) | 2016-05-19 | 2019-12-31 | Applied Materials, Inc. | Systems and methods for improved semiconductor etching and component protection |
US10629473B2 (en) | 2016-09-09 | 2020-04-21 | Applied Materials, Inc. | Footing removal for nitride spacer |
US9934942B1 (en) | 2016-10-04 | 2018-04-03 | Applied Materials, Inc. | Chamber with flow-through source |
US10546729B2 (en) | 2016-10-04 | 2020-01-28 | Applied Materials, Inc. | Dual-channel showerhead with improved profile |
US10062579B2 (en) | 2016-10-07 | 2018-08-28 | Applied Materials, Inc. | Selective SiN lateral recess |
US10163696B2 (en) | 2016-11-11 | 2018-12-25 | Applied Materials, Inc. | Selective cobalt removal for bottom up gapfill |
US9768034B1 (en) | 2016-11-11 | 2017-09-19 | Applied Materials, Inc. | Removal methods for high aspect ratio structures |
US10026621B2 (en) | 2016-11-14 | 2018-07-17 | Applied Materials, Inc. | SiN spacer profile patterning |
US10242908B2 (en) | 2016-11-14 | 2019-03-26 | Applied Materials, Inc. | Airgap formation with damage-free copper |
US10566206B2 (en) | 2016-12-27 | 2020-02-18 | Applied Materials, Inc. | Systems and methods for anisotropic material breakthrough |
US10431429B2 (en) | 2017-02-03 | 2019-10-01 | Applied Materials, Inc. | Systems and methods for radial and azimuthal control of plasma uniformity |
US10403507B2 (en) | 2017-02-03 | 2019-09-03 | Applied Materials, Inc. | Shaped etch profile with oxidation |
US10319739B2 (en) | 2017-02-08 | 2019-06-11 | Applied Materials, Inc. | Accommodating imperfectly aligned memory holes |
US10943834B2 (en) | 2017-03-13 | 2021-03-09 | Applied Materials, Inc. | Replacement contact process |
US10079154B1 (en) * | 2017-03-20 | 2018-09-18 | Lam Research Corporation | Atomic layer etching of silicon nitride |
US10319649B2 (en) | 2017-04-11 | 2019-06-11 | Applied Materials, Inc. | Optical emission spectroscopy (OES) for remote plasma monitoring |
US11276590B2 (en) | 2017-05-17 | 2022-03-15 | Applied Materials, Inc. | Multi-zone semiconductor substrate supports |
US11276559B2 (en) | 2017-05-17 | 2022-03-15 | Applied Materials, Inc. | Semiconductor processing chamber for multiple precursor flow |
US10361091B2 (en) * | 2017-05-31 | 2019-07-23 | Lam Research Corporation | Porous low-k dielectric etch |
US10497579B2 (en) | 2017-05-31 | 2019-12-03 | Applied Materials, Inc. | Water-free etching methods |
US10920320B2 (en) | 2017-06-16 | 2021-02-16 | Applied Materials, Inc. | Plasma health determination in semiconductor substrate processing reactors |
US10541246B2 (en) | 2017-06-26 | 2020-01-21 | Applied Materials, Inc. | 3D flash memory cells which discourage cross-cell electrical tunneling |
US10727080B2 (en) | 2017-07-07 | 2020-07-28 | Applied Materials, Inc. | Tantalum-containing material removal |
US10541184B2 (en) | 2017-07-11 | 2020-01-21 | Applied Materials, Inc. | Optical emission spectroscopic techniques for monitoring etching |
US10354889B2 (en) | 2017-07-17 | 2019-07-16 | Applied Materials, Inc. | Non-halogen etching of silicon-containing materials |
US10043674B1 (en) | 2017-08-04 | 2018-08-07 | Applied Materials, Inc. | Germanium etching systems and methods |
US10170336B1 (en) | 2017-08-04 | 2019-01-01 | Applied Materials, Inc. | Methods for anisotropic control of selective silicon removal |
US10297458B2 (en) | 2017-08-07 | 2019-05-21 | Applied Materials, Inc. | Process window widening using coated parts in plasma etch processes |
US10283324B1 (en) | 2017-10-24 | 2019-05-07 | Applied Materials, Inc. | Oxygen treatment for nitride etching |
US10424487B2 (en) | 2017-10-24 | 2019-09-24 | Applied Materials, Inc. | Atomic layer etching processes |
US10128086B1 (en) | 2017-10-24 | 2018-11-13 | Applied Materials, Inc. | Silicon pretreatment for nitride removal |
US10256112B1 (en) | 2017-12-08 | 2019-04-09 | Applied Materials, Inc. | Selective tungsten removal |
US10903054B2 (en) | 2017-12-19 | 2021-01-26 | Applied Materials, Inc. | Multi-zone gas distribution systems and methods |
US11328909B2 (en) | 2017-12-22 | 2022-05-10 | Applied Materials, Inc. | Chamber conditioning and removal processes |
US10854426B2 (en) | 2018-01-08 | 2020-12-01 | Applied Materials, Inc. | Metal recess for semiconductor structures |
US10679870B2 (en) | 2018-02-15 | 2020-06-09 | Applied Materials, Inc. | Semiconductor processing chamber multistage mixing apparatus |
US10964512B2 (en) | 2018-02-15 | 2021-03-30 | Applied Materials, Inc. | Semiconductor processing chamber multistage mixing apparatus and methods |
TWI716818B (zh) | 2018-02-28 | 2021-01-21 | 美商應用材料股份有限公司 | 形成氣隙的系統及方法 |
US10593560B2 (en) | 2018-03-01 | 2020-03-17 | Applied Materials, Inc. | Magnetic induction plasma source for semiconductor processes and equipment |
US10319600B1 (en) | 2018-03-12 | 2019-06-11 | Applied Materials, Inc. | Thermal silicon etch |
US10497573B2 (en) | 2018-03-13 | 2019-12-03 | Applied Materials, Inc. | Selective atomic layer etching of semiconductor materials |
US10573527B2 (en) | 2018-04-06 | 2020-02-25 | Applied Materials, Inc. | Gas-phase selective etching systems and methods |
US10490406B2 (en) | 2018-04-10 | 2019-11-26 | Appled Materials, Inc. | Systems and methods for material breakthrough |
US10699879B2 (en) | 2018-04-17 | 2020-06-30 | Applied Materials, Inc. | Two piece electrode assembly with gap for plasma control |
US10886137B2 (en) | 2018-04-30 | 2021-01-05 | Applied Materials, Inc. | Selective nitride removal |
US10770305B2 (en) * | 2018-05-11 | 2020-09-08 | Tokyo Electron Limited | Method of atomic layer etching of oxide |
US10755941B2 (en) | 2018-07-06 | 2020-08-25 | Applied Materials, Inc. | Self-limiting selective etching systems and methods |
US10872778B2 (en) | 2018-07-06 | 2020-12-22 | Applied Materials, Inc. | Systems and methods utilizing solid-phase etchants |
US10672642B2 (en) | 2018-07-24 | 2020-06-02 | Applied Materials, Inc. | Systems and methods for pedestal configuration |
US11049755B2 (en) | 2018-09-14 | 2021-06-29 | Applied Materials, Inc. | Semiconductor substrate supports with embedded RF shield |
US10892198B2 (en) | 2018-09-14 | 2021-01-12 | Applied Materials, Inc. | Systems and methods for improved performance in semiconductor processing |
US11062887B2 (en) | 2018-09-17 | 2021-07-13 | Applied Materials, Inc. | High temperature RF heater pedestals |
US11417534B2 (en) | 2018-09-21 | 2022-08-16 | Applied Materials, Inc. | Selective material removal |
US11682560B2 (en) | 2018-10-11 | 2023-06-20 | Applied Materials, Inc. | Systems and methods for hafnium-containing film removal |
US11121002B2 (en) | 2018-10-24 | 2021-09-14 | Applied Materials, Inc. | Systems and methods for etching metals and metal derivatives |
US11437242B2 (en) | 2018-11-27 | 2022-09-06 | Applied Materials, Inc. | Selective removal of silicon-containing materials |
US11177177B2 (en) * | 2018-11-30 | 2021-11-16 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and method of manufacture |
US11721527B2 (en) | 2019-01-07 | 2023-08-08 | Applied Materials, Inc. | Processing chamber mixing systems |
US10920319B2 (en) | 2019-01-11 | 2021-02-16 | Applied Materials, Inc. | Ceramic showerheads with conductive electrodes |
CN110379712A (zh) * | 2019-08-05 | 2019-10-25 | 德淮半导体有限公司 | 一种刻蚀方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150325479A1 (en) * | 2013-12-12 | 2015-11-12 | Lam Research Corporation | Method for forming self-aligned contacts/vias with high corner selectivity |
US20160196984A1 (en) * | 2015-01-05 | 2016-07-07 | Lam Research Corporation | Isotropic atomic layer etch for silicon and germanium oxides |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8262920B2 (en) * | 2007-06-18 | 2012-09-11 | Lam Research Corporation | Minimization of mask undercut on deep silicon etch |
US8691701B2 (en) * | 2009-05-08 | 2014-04-08 | Lam Research Corporation | Strip with reduced low-K dielectric damage |
US20140273365A1 (en) * | 2013-03-13 | 2014-09-18 | Globalfoundries Inc. | Methods of forming contacts to source/drain regions of finfet devices by forming a region that includes a schottky barrier lowering material |
US9257300B2 (en) * | 2013-07-09 | 2016-02-09 | Lam Research Corporation | Fluorocarbon based aspect-ratio independent etching |
US9773683B2 (en) * | 2014-06-09 | 2017-09-26 | American Air Liquide, Inc. | Atomic layer or cyclic plasma etching chemistries and processes |
US9318343B2 (en) * | 2014-06-11 | 2016-04-19 | Tokyo Electron Limited | Method to improve etch selectivity during silicon nitride spacer etch |
US9396961B2 (en) * | 2014-12-22 | 2016-07-19 | Lam Research Corporation | Integrated etch/clean for dielectric etch applications |
US9396956B1 (en) * | 2015-01-16 | 2016-07-19 | Asm Ip Holding B.V. | Method of plasma-enhanced atomic layer etching |
US9911620B2 (en) * | 2015-02-23 | 2018-03-06 | Lam Research Corporation | Method for achieving ultra-high selectivity while etching silicon nitride |
US9881807B2 (en) * | 2015-03-30 | 2018-01-30 | Tokyo Electron Limited | Method for atomic layer etching |
KR102487054B1 (ko) * | 2017-11-28 | 2023-01-13 | 삼성전자주식회사 | 식각 방법 및 반도체 장치의 제조 방법 |
-
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150325479A1 (en) * | 2013-12-12 | 2015-11-12 | Lam Research Corporation | Method for forming self-aligned contacts/vias with high corner selectivity |
US20160196984A1 (en) * | 2015-01-05 | 2016-07-07 | Lam Research Corporation | Isotropic atomic layer etch for silicon and germanium oxides |
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