TW201739025A - 接合裝置 - Google Patents

接合裝置 Download PDF

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Publication number
TW201739025A
TW201739025A TW106109851A TW106109851A TW201739025A TW 201739025 A TW201739025 A TW 201739025A TW 106109851 A TW106109851 A TW 106109851A TW 106109851 A TW106109851 A TW 106109851A TW 201739025 A TW201739025 A TW 201739025A
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Taiwan
Prior art keywords
bonding
region
bonding tool
substrate
peripheral
Prior art date
Application number
TW106109851A
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English (en)
Other versions
TWI662671B (zh
Inventor
Kohei Seyama
Yuji Eguchi
Shoji Wada
Original Assignee
Shinkawa Kk
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Publication date
Application filed by Shinkawa Kk filed Critical Shinkawa Kk
Publication of TW201739025A publication Critical patent/TW201739025A/zh
Application granted granted Critical
Publication of TWI662671B publication Critical patent/TWI662671B/zh

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Abstract

本發明提供一種能夠將接合構件之中央部加熱至低於周緣部之溫度之接合裝置。本發明之接合裝置，具備：加熱器11；及接合工具20，具有：下表面24，其吸附記憶體晶片60；及上表面22，其安裝於加熱器11；下表面24之第1周緣區域A將記憶體晶片60之周緣部60a按壓至焊錫球41，第1中央區域B將記憶體晶片60之中央部60b按壓至耐熱溫度較焊錫球41低之DAF44；自第1中央區域B傳遞至記憶體晶片60之中央部60b之熱量，小於自第1周緣區域A傳遞至記憶體晶片60之周緣部60a之熱量。

Description

接合裝置
本發明係關於一種接合裝置，尤其是關於一種用於接合裝置之接合工具及平台之構造。
近年來，為了應對半導體裝置之小型化及高度化之要求，而趨於使用積層有複數個半導體晶片之三維安裝構造。作為三維安裝構造，例如，提出有如下構造：於基板之上形成2個間隔片，於2個間隔片之間安裝控制晶片，於2個間隔片之上隔著附模組膠膜(Die Attach Film，以下稱為DAF)等接著層而以橫跨控制晶片之上之方式安裝第一段之記憶體晶片，且於第一段記憶體晶片之上隔著接著層而積層複數個記憶體晶片(例如，參照專利文獻1)。DAF為熱硬化性樹脂之膜。
又，提出有如下三維安裝構造：構成於中央具有開口之第2基板之上表面隔著DAF積層多段半導體晶片且於基板之下表面形成焊錫球而成之上部半導體模組、及於構成上部半導體模組之第2基板之開口所對應之位置之第1基板之上積層小於開口之大小之半導體晶片而成之下部半導體模組，對積層於下部半導體模組之半導體晶片之上表面塗佈接著劑，使上部半導體模組與下部半導體模組對準且藉由回焊使焊錫球熔融並且使 接著劑硬化而將上部半導體模組與下部半導體模組接合(例如，參照專利文獻2)。
另一方面，作為半導體晶片與基板或半導體晶片彼此之接合方法，較多使用如下倒裝晶片接合：可於半導體晶片形成焊錫凸塊或金凸塊，於形成有凸塊之半導體晶片之面黏貼膜狀之絕緣樹脂之後，使半導體晶片反轉，其後藉由接合工具將半導體晶片熱壓接於基板之上，使焊錫凸塊或金凸塊熔融而進行基板與半導體晶片之接合並且進行半導體晶片與基板之間之密封樹脂之硬化。於倒裝晶片接合中，若半導體晶片內之焊錫凸塊或金凸塊之熔融狀態存在不均，則有溫度較低之部分之焊錫凸塊或金凸塊成為未熔融之狀態而引起接合不良之可能性，故而提出有以能夠對半導體晶片均勻地加熱之方式使與半導體晶片之接觸密度疏密地分佈之吸嘴(collet)(接合工具)(例如，參照專利文獻3)。
[先前技術文獻]
[專利文獻]
[專利文獻1]日本特開2015-176906號公報
[專利文獻2]日本特開2008-166527號公報
[專利文獻3]日本特開2012-199358號公報
且說，作為更有效率地製造如專利文獻1所記載之三維構造之半導體裝置之方法，研究有如下接合方法：利用DAF等熱硬化性樹脂之 膜將記憶體晶片之中央部分接著於控制晶片之上表面，並且利用藉由焊錫球等之熱熔融後之硬化而進行金屬構件間之連接之連接用金屬將記憶體晶片之周緣部分連接於基板。該接合方法係應用專利文獻3所記載之倒裝晶片接合方法者，且將由加熱器加熱後之記憶體晶片按壓至控制晶片之上，使DAF熱硬化而將記憶體晶片之中央部分接著固定於控制晶片，同時，將記憶體晶片之周緣部分按壓至接合用金屬之上並使接合用金屬熔融而進行記憶體晶片與基板之電性接合。
然而，存在如下問題：由於DAF之耐熱溫度低於焊錫球等接合用金屬之熔融溫度，故而若將記憶體晶片加熱至接合用金屬之熔融溫度，則DAF會劣化。相反，於將記憶體晶片僅加熱至DAF之耐熱溫度為止之情形時，接合用金屬不會充分地熔融，而存在無法良好地進行記憶體晶片與基板之電性接合之問題。因此，此種接合方法無法利用如專利文獻3所記載之將半導體晶片均勻地加熱之接合裝置執行，而迫切期望能夠以使記憶體晶片(接合構件)之中央部分之溫度低於周緣部分之溫度之方式對記憶體晶片(接合構件)進行加熱之接合裝置。
因此，本發明之目的在於提供一種能夠將接合構件之中央部加熱至低於周緣部之溫度的接合裝置。
本發明之接合裝置，其特徵在於具備：加熱器；以及接合工具，具有：第1面，其吸附接合構件；及第2面，其與上述第1面為相反側且安裝於加熱器；第1面之第1周緣區域將接合構件之周緣部按壓至第1構件，第1面之第1中央區域將接合構件之中央部按壓至耐熱溫度較第1 構件低之第2構件；自接合工具之第1中央區域傳遞至接合構件之中央部之接合構件之每單位面積的熱量，小於自接合工具之第1周緣區域傳遞至接合構件之周緣部之接合構件之每單位面積的熱量。
於本發明之接合裝置中，較佳為，接合工具之第1中央區域相較於接合工具之第1周緣區域而言與接合構件之接觸面積較小。
於本發明之接合裝置中，較佳為，於接合工具之第1中央區域呈格子狀配置有複數個凹部。
於本發明之接合裝置中，較佳為，接合工具之第1中央區域具有供冷卻空氣流通之冷卻流路。
於本發明之接合裝置中，較佳為，接合工具之第1中央區域由熱導率低於接合工具之第1周緣區域之材料構成。
於本發明之接合裝置中，較佳為，接合工具之第2面具有與第1中央區域對應之第2中央區域及第2中央區域之外周側之第2周緣區域，且自加熱器之中央部傳遞至接合工具之第2中央區域之加熱器之每單位面積的熱量，小於自加熱器之周緣部傳遞至接合工具之第2周緣區域之加熱器之每單位面積的熱量。
於本發明之接合裝置中，較佳為，接合工具之第2中央區域相較於接合工具之第2周緣區域而言與加熱器之接觸面積較小。
於本發明之接合裝置中，較佳為，於接合工具之第2中央區域呈格子狀配置有複數個凹部。
於本發明之接合裝置中，較佳為，接合工具之第2中央區域具有供冷卻空氣流通之冷卻流路。
於本發明之接合裝置中，較佳為，接合工具之第2中央區域由熱導率低於接合工具之第2周緣區域之材料構成。
於本發明之接合裝置中，較佳為，具備吸附固定基板之平台，第2構件載置於接合於基板之電子零件之上，第1構件形成於電子零件之周圍之基板之上，自接合有電子零件之基板之第1區域傳遞至與基板之第1區域對向之平台之第1部分的基板之每單位面積之熱量，大於自配置有第1構件之基板之第2區域傳遞至與基板之第2區域對向之平台之第2部分的基板之每單位面積之熱量。
於本發明之接合裝置中，較佳為，平台係於第1部分設置有供冷卻空氣流通之冷卻流路。
於本發明之接合裝置中，較佳為，平台係於第2部分之表面設置有凹部。
本發明可提供一種能夠將接合構件之中央部加熱至低於周緣部之溫度的接合裝置。
10‧‧‧接合頭
11‧‧‧加熱器
12、13、30、55‧‧‧真空孔
14、15、29、35、54‧‧‧空氣孔
20‧‧‧接合工具
21‧‧‧基底
21a、50a‧‧‧表面
22‧‧‧上表面
23‧‧‧島部
23a、25、32、33、34、51、56‧‧‧凹部
24‧‧‧下表面
25a‧‧‧肋
26、52‧‧‧間隔壁
27、53‧‧‧突起
28、58‧‧‧冷卻流路
28a‧‧‧外周冷卻流路
28b‧‧‧內周冷卻流路
31、39‧‧‧隔熱材料
34a、59‧‧‧台座
40‧‧‧基板
41‧‧‧焊錫球
42‧‧‧控制晶片
43‧‧‧樹脂
50‧‧‧平台
50b‧‧‧第1部分
50c‧‧‧第2部分
60‧‧‧記憶體晶片
60a‧‧‧周緣部
60b‧‧‧中央部
100、200、300、400、500、600、700、800‧‧‧接合裝置
A‧‧‧第1周緣區域
B‧‧‧第1中央區域
C‧‧‧第2周緣區域
D‧‧‧第2中央區域
E‧‧‧第1區域
F‧‧‧第2區域
圖1係本發明之第1實施形態之接合裝置之剖面圖。
圖2係自下側觀察安裝於圖1所示之接合裝置之接合工具的立體圖。
圖3係表示藉由圖1所示之接合裝置將由加熱器加熱後之記憶體晶片之中央部按壓至控制晶片上之DAF，並且將記憶體晶片之周緣部按壓至形成於基板之上之焊錫球之上之狀態的說明圖。
圖4係本發明之第2實施形態之接合裝置之剖面圖。
圖5係自下側觀察安裝於圖4所示之接合裝置之接合工具的立體圖。
圖6係表示藉由圖4所示之接合裝置將由加熱器加熱後之記憶體晶片之中央部按壓至控制晶片上之DAF，並且將記憶體晶片之周緣部按壓至形成於基板之上之焊錫球之上之狀態的說明圖。
圖7係本發明之第3實施形態之接合裝置之剖面圖。
圖8係本發明之第4實施形態之接合裝置之剖面圖。
圖9係自上側觀察安裝於圖8所示之接合裝置之接合工具的立體圖。
圖10係表示藉由圖8所示之接合裝置將由加熱器加熱後之記憶體晶片之中央部按壓至控制晶片上之DAF，並且將記憶體晶片之周緣部按壓至形成於基板之上之焊錫球之上之狀態的說明圖。
圖11係本發明之第5實施形態之接合裝置之剖面圖。
圖12係自上側觀察安裝於圖11所示之接合裝置之接合工具的立體圖。
圖13係表示藉由圖11所示之接合裝置將由加熱器加熱後之記憶體晶片之中央部按壓至控制晶片上之DAF，並且將記憶體晶片之周緣部按壓至形成於基板之上之焊錫球之上之狀態的說明圖。
圖14係本發明之第6實施形態之接合裝置之剖面圖。
圖15係本發明之第7實施形態之接合裝置之剖面圖。
圖16係本發明之第8實施形態之接合裝置之剖面圖。
圖17係表示圖16所示之接合裝置之平台之立體圖。
<第1實施形態>
以下，一面參照圖式一面對本發明之第1實施形態進行說明。如圖1所示，本實施形態之接合裝置100包含：平台50，其真空吸附基板40；接合頭10，其配置於平台50之上且由未圖示之驅動裝置於上下方向驅動；加熱器11，其安裝於接合頭10之下表面；及接合工具20，其安裝於加熱器11之下表面。再者，圖1所示之上、下之顯示表示垂直上方、垂直下方。於其他圖中亦相同。
如圖1、2所示，接合工具20具備四方板狀之基底21、及自基底21之下側之表面21a呈四方台座狀突出之島部23。接合工具20之第1面即島部23之下表面24真空吸附接合構件即記憶體晶片60。圖1表示於接合工具20之下表面24真空吸附有記憶體晶片60之狀態。島部23較基底21小，且為與真空吸附於下表面24之記憶體晶片60大致相同之四方形狀。
如圖2所示，於接合工具20之下表面24之中央呈格子狀配置有由寬度狹窄之肋25a包圍周圍之複數個凹部25。肋25a之前端面以與記憶體晶片60之上表面相接之方式與下表面24成為同一面。於接合工具20之中心之肋25a之前端面設置有真空孔30。
下表面24之配置有複數個凹部25之範圍為接合工具20之第1中央區域B，於下表面24之第1中央區域B之外周側於圖2中標註影線之範圍為接合工具20之第1周緣區域A。又，與接合工具20之第1中央區域B對向之記憶體晶片60之範圍為記憶體晶片60之中央部60b(接合構件之中央部)，與接合工具20之第1周緣區域A對向之記憶體晶片60之範 圍為記憶體晶片60之周緣部60a(接合構件之周緣部)。
於接合頭10、加熱器11設置有未圖示之真空孔，接合工具20係藉由真空吸附而固定於加熱器11之下表面。因此，加熱器11能夠容易地更換。於本實施形態中，第1中央區域B為與下文中說明之安裝於基板40之上之控制晶片42之大小相同之大小，第1周緣區域A安裝有如覆蓋下文中說明之形成於基板40之上之焊錫球41之範圍的接合工具20。
加熱器11例如係於氮化鋁等陶瓷之內部嵌入由鉑或鎢等構成之熱敏電阻而成者。如圖1所示，加熱器11為四方板狀，其大小與接合工具20之基底21大致相同。於加熱器11之中心設置有與接合工具20之真空孔30連通之真空孔13。如圖1所示，於接合頭10設置有與加熱器11之真空孔13、接合工具20之真空孔30連通之真空孔12。連通之真空孔12、13、30連接於未圖示之真空裝置VAC，將記憶體晶片60真空吸附於接合工具20之下表面24。
如圖1所示，平台50係於表面50a真空吸附基板40者。接合頭10能夠於水平方向移動，圖1表示將接合頭10之水平方向之中心位置與控制晶片42之中心位置對準之狀態。
於圖1所示之基板40之中央接合控制晶片42，控制晶片42與基板40之間由樹脂43密封。於控制晶片42之上表面載置有第2構件即DAF44。於基板40之上表面之控制晶片42之周圍形成有第1構件即複數個焊錫球41。控制晶片42為小於記憶體晶片60或者接合工具20之島部23之大小且與接合工具20之第1中央區域B或者記憶體晶片60之中央部60b大致相同之大小。又，如圖1所示，若將接合頭10之水平方向之中心位置 與控制晶片42之中心位置對準，則焊錫球41位於與接合工具20之第1周緣區域A或者記憶體晶片60之周緣部60a對向之範圍。
如圖3所示，若接合裝置100之未圖示之控制部使接合頭10自圖1所示之狀態朝向平台50下降，則記憶體晶片60之中央部60b之下表面藉由經由接合工具20之肋25a而傳遞之向下之負載將載置於控制晶片42之上之DAF44向下按壓。記憶體晶片60之周緣部60a之下表面藉由經由接合工具20之第1周緣區域A而傳遞之向下之負載將焊錫球41向下按壓。又，若將加熱器11設為接通，則加熱器11之熱如箭頭91所示般，通過接合工具20之第1周緣區域A而將記憶體晶片60之周緣部60a加熱，記憶體晶片60之周緣部60a將焊錫球41加熱。又，加熱器11之熱如箭頭92所示般，通過接合工具20之第1中央區域B而將記憶體晶片60之中央部60b加熱，記憶體晶片60之中央部60b將載置於控制晶片42之上之DAF44加熱。
如圖2所示，於接合工具20之下表面24之第1中央區域B呈格子狀排列有複數個凹部25。若記憶體晶片60被真空吸附於接合工具20之下表面24，則凹部25內之空氣被真空裝置VAC自真空孔30吸出，從而凹部25成為真空之隔熱層。因此，來自加熱器11之熱不會通過凹部25到達至記憶體晶片60，而如圖3之箭頭92所示般，通過與記憶體晶片60之上表面相接之肋25a之前端面到達至記憶體晶片60。另一方面，接合工具20之第1周緣區域A為平面，與記憶體晶片60之上表面接觸。因此，來自加熱器11之熱如圖3之箭頭91所示般，自接合工具20之第1周緣區域A之整個面到達至記憶體晶片60。
此處，接合工具20之肋25a之前端面與記憶體晶片60之中央部60b之接觸面積小於接合工具20之第1周緣區域A與記憶體晶片60之周緣部60a之接觸面積。又，如上所述，藉由凹部25而形成之隔熱層幾乎不使加熱器11之熱通過。因此，自接合工具20之第1中央區域B傳遞至記憶體晶片60之中央部60b之記憶體晶片60之每單位面積的熱量小於自接合工具20之第1周緣區域A傳遞至記憶體晶片60之周緣部60a之記憶體晶片60之每單位面積的熱量。因此，於加熱器11將接合工具20之上表面22均等地加熱之情形時，記憶體晶片60之中央部60b之每單位面積之熱輸入小於記憶體晶片60之周緣部60a之每單位面積之熱輸入，從而記憶體晶片60之中央部60b之溫度低於記憶體晶片60之周緣部60a。
藉此，例如，即便於藉由加熱器11將與焊錫球41相接之記憶體晶片60之周緣部60a之溫度加熱至焊錫球熔融之230℃以上之情形時，亦能夠將與DAF44相接之記憶體晶片60之中央部60b之溫度抑制為未達DAF之耐熱溫度即200℃。若焊錫球41由記憶體晶片60之周緣部60a加熱至230℃以上，則熔融，而DAF44於未達200℃、例如180℃左右開始熱硬化，故而接合裝置100能夠使焊錫球41熔融，並且使耐熱溫度低於焊錫球41之熔融溫度之DAF44不發生劣化地熱硬化而將記憶體晶片60構裝於基板40、控制晶片42之上。
接合裝置100之未圖示之控制部於利用記憶體晶片60按壓、加熱焊錫球41與DAF44特定時間之後，將未圖示之真空孔12、13、30之真空解除，其後使接合頭10上升。此時，記憶體晶片60係隔著DAF44而固定於控制晶片42。而且，若接合頭上升而來自加熱器11之熱輸入消失， 則焊錫球41硬化，從而記憶體晶片60與基板40之電性接合完成。
如以上所說明般，本實施形態之接合裝置100係於吸附接合構件即記憶體晶片60之接合工具20之下表面24呈格子狀配置複數個凹部25，藉此，即便利用加熱器11將接合工具20均等地加熱，亦能夠使記憶體晶片60之中央部60b之每單位面積之熱輸入小於記憶體晶片60之周緣部60a之每單位面積之熱輸入，從而使記憶體晶片60之中央部60b之溫度低於記憶體晶片60之周緣部60a。藉此，能夠使焊錫球41熔融，並且使耐熱溫度低於焊錫球41之熔融溫度之DAF44不發生劣化地熱硬化而將記憶體晶片60安裝於基板40、控制晶片42之上。
又，接合工具20由於係藉由未圖示之真空吸附孔而吸附固定於加熱器11之下表面，故而能夠對照所接合之記憶體晶片60之大小容易地更換為島部23之大小不同之接合工具20。進而，能夠對照安裝於基板40之控制晶片42之大小、焊錫球41之形成位置而預先準備多種第1中央區域B與第1周緣區域A之範圍不同之接合工具20，藉由根據控制晶片42之大小、焊錫球41之位置更換接合工具20而應對多種多樣之基板40。如此，本實施形態之接合裝置100僅藉由根據接合構件即記憶體晶片60之大小、第1構件即焊錫球41之形成位置、供載置第2構件即DAF44之控制晶片42之大小來更換接合工具20，便能夠利用同一加熱器將較多種類之接合構件接合於多種多樣之基板。
於以上之說明中，設為將記憶體晶片60與基板40藉由焊錫球41而接合進行了說明，但代替焊錫球41而使用硬化起始溫度、耐熱溫度高於DAF44之耐熱溫度之導電性樹脂構件，亦能夠與上述同樣地使耐熱溫 度低於導電性樹脂構件之硬化起始溫度之DAF44不發生劣化地使導電性樹脂構件與DAF44之兩者熱硬化而將記憶體晶片60安裝於基板40、控制晶片42之上。又，於本實施形態中，設為接合構件為記憶體晶片60進行了說明，但接合構件亦可為其他電子零件，或亦可為樹脂基板等。
<第2實施形態>
其次，一面參照圖4至6一面對本發明之第2實施形態之接合裝置200進行說明。接合裝置200係於接合工具20之下表面24代替第1實施形態之接合裝置100之凹部25而具備如圖4、5所示之供冷卻空氣流通之冷卻流路28者。對與上文中參照圖1至圖3所說明之第1實施形態之接合裝置100相同之部分標註相同之符號並省略說明。
如圖5所示，於接合工具20之下表面24形成有界定第1中央區域B之凹部23a。凹部23a之外周側為第1周緣區域A。於圖5中，標註有影線之範圍為第1周緣區域A。於凹部23a之中，設置有大致U字型之間隔壁26、及配置於間隔壁26之內周側之複數個突起27。間隔壁26之與凹部23a之內周面對向之面於與凹部23a之內表面之間形成供冷卻空氣流通之外周冷卻流路28a。間隔壁26之內周側成為冷卻空氣於複數個突起27之間流通之內周冷卻流路28b。間隔壁26之前端面與突起27之前端面係以與記憶體晶片60之上表面相接之方式與下表面24成為同一面。外周冷卻流路28a與內周冷卻流路28b構成冷卻流路28。
如圖4、5所示，於接合工具20之中心設置有貫通內周冷卻流路28b與上表面22之間之真空孔30。又，於接合工具20之凹部23a之內周面附近設置有將外周冷卻流路28a與上表面22連通之空氣孔29。如圖4 所示，真空孔30與設置於加熱器11之真空孔13、設置於接合頭10之真空孔12連通，且與真空裝置VAC連通。又，空氣孔29與設置於加熱器11之空氣孔15、設置於接合頭10之空氣孔14連通。
如圖4之箭頭93所示，自空氣孔14、15通過空氣孔29而流入至外周冷卻流路28a之冷卻空氣係如圖5之箭頭95、96所示般沿著凹部23a之內周面流動之後，自與空氣孔29相反之側流入至內周冷卻流路28b，並通過突起27之間而自真空孔30、13、12如圖4之箭頭94般流向真空裝置VAC。雖於外周冷卻流路28a、內周冷卻流路28b流通有冷卻空氣，但壓力接近於真空，而真空吸附記憶體晶片60。
如圖6所示，與第1實施形態之接合裝置100相同，若接合裝置200之未圖示之控制部使接合頭10自圖4所示之狀態朝向平台50下降，則記憶體晶片60之中央部60b之下表面藉由經由接合工具20之間隔壁26及突起27而傳遞之向下之負載將載置於控制晶片42之上之DAF44向下按壓，記憶體晶片60之周緣部60a之下表面藉由經由接合工具20之第1周緣區域A而傳遞之向下之負載將焊錫球41向下按壓。又，加熱器11之熱係如圖6之箭頭91所示般通過接合工具20之第1周緣區域A將記憶體晶片60之周緣部60a加熱，記憶體晶片60之周緣部60a將焊錫球41加熱。又，加熱器11之熱係如圖6之箭頭92所示般，通過接合工具20之形成有外周冷卻流路28a、內周冷卻流路28b之第1中央區域B而將記憶體晶片60之中央部60b加熱，記憶體晶片60之中央部60b將載置於控制晶片42之上之DAF44加熱。
由於在第1中央區域B之外周冷卻流路28a、內周冷卻流路 28b流通有冷卻空氣，故而來自加熱器11之熱不會通過各冷卻流路28a、28b到達至記憶體晶片60，而如圖6之箭頭92所示般，通過與記憶體晶片60之上表面相接之間隔壁26之前端面與突起27之前端面而到達至記憶體晶片60。另一方面，接合工具20之第1周緣區域A為平面，且與記憶體晶片60之上表面接觸。因此，來自加熱器11之熱如圖6之箭頭91所示般，自接合工具20之第1周緣區域A之整個面到達至記憶體晶片60。
此處，間隔壁26之前端面及突起27之前端面與記憶體晶片60之中央部60b之接觸面積小於接合工具20之第1周緣區域A與記憶體晶片60之周緣部60a之接觸面積。又，由於在周圍流通有冷卻空氣，故而間隔壁26與突起27之溫度低於第1周緣區域A之溫度。進而，如上所述，第1中央區域B之形成有各冷卻流路28a、28b之區域幾乎不使加熱器11之熱通過。因此，與第1實施形態相同，自接合工具20之第1中央區域B傳遞至記憶體晶片60之中央部60b之記憶體晶片60之每單位面積的熱量小於自接合工具20之第1周緣區域A傳遞至記憶體晶片60之周緣部60a之記憶體晶片60之每單位面積的熱量。因此，於加熱器11將接合工具20之上表面22均等地加熱之情形時，記憶體晶片60之中央部60b之每單位面積之熱輸入小於記憶體晶片60之周緣部60a之每單位面積之熱輸入，從而記憶體晶片60之中央部60b之溫度低於記憶體晶片60之周緣部60a。
藉此，第2實施形態之接合裝置200亦與第1實施形態之接合裝置100相同，能夠使焊錫球41熔融，並且使耐熱溫度低於焊錫球41之熔融溫度之DAF44不發生劣化地熱硬化而將記憶體晶片60安裝於基板40、控制晶片42之上。
<第3實施形態>
其次，一面參照圖7一面對第3實施形態之接合裝置300進行說明。接合裝置300係如圖7所示般於接合工具20之下表面24之第1中央區域B安裝有熱導率低於第1周緣區域A之隔熱材料31者。對與上文中參照圖1至圖3所說明之第1實施形態之接合裝置100相同之部分標註相同之符號並省略說明。
本實施形態之接合裝置300由於在接合工具20之第1中央區域B安裝有熱導率低於第1周緣區域A之隔熱材料31，故而與上文中所說明之第1、第2實施形態之接合裝置100、200相同，自接合工具20之第1中央區域B傳遞至記憶體晶片60之中央部60b之記憶體晶片60之每單位面積的熱量小於自接合工具20之第1周緣區域A傳遞至記憶體晶片60之周緣部60a之記憶體晶片60之每單位面積的熱量。因此，於加熱器11將接合工具20之上表面22均等地加熱之情形時，記憶體晶片60之中央部60b之每單位面積之熱輸入小於記憶體晶片60之周緣部60a之每單位面積之熱輸入，從而記憶體晶片60之中央部60b之溫度低於記憶體晶片60之周緣部60a。
藉此，第3實施形態之接合裝置300亦與第1、第2實施形態之接合裝置100、200相同，能夠使焊錫球41熔融，並且使耐熱溫度低於焊錫球41之熔融溫度之DAF44不發生劣化地熱硬化而將記憶體晶片60安裝於基板40、控制晶片42之上。
<第4實施形態>
其次，一面參照圖8至10一面對第4實施形態之接合裝置400進行說 明。接合裝置400係於第1實施形態之接合裝置100之接合工具20之第2面即上表面22設置有凹部32者。於下表面24，與第1實施形態之接合裝置100相同，呈格子狀配置有複數個凹部25。對與上文中參照圖1至圖3所說明之第1實施形態之接合裝置100相同之部分標註相同之符號並省略說明。
如圖8、9所示，第2面即上表面22之凹部32係設置於與下表面24之第1中央區域B對應之範圍，且界定第2中央區域D。凹部32之外周側之上表面22為第2周緣區域C。於凹部32之中心設置有與下表面24連通之真空孔30。又，如圖7所示，設置於加熱器11之真空孔13與凹部32連通。若藉由未圖示之真空裝置VAC使與加熱器11之真空孔13連通之接合頭10之真空孔12為真空，則接合工具20之上表面22之凹部32與下表面24之複數個凹部25亦成為真空，分別形成真空隔熱層。
如圖10所示，若接合裝置400之未圖示之控制部使接合頭10自圖8所示之狀態朝向平台50下降，則記憶體晶片60之中央部60b之下表面藉由經由接合工具20之肋25a而傳遞之向下之負載而將載置於控制晶片42之上之DAF44向下按壓。記憶體晶片60之周緣部60a之下表面藉由經由接合工具20之第1周緣區域A而傳遞之向下之負載而將焊錫球41向下按壓。又，若將加熱器11設為接通，則加熱器11之熱係如箭頭91所示般，自接合工具20之第2周緣區域C通過第1周緣區域A之整個面將記憶體晶片60之周緣部60a加熱，記憶體晶片60之周緣部60a將焊錫球41加熱。又，加熱器11之熱係如箭頭88所示般，不通過成為隔熱層之凹部32，而自接合工具20之第2周緣區域C通過第1中央區域B之肋25a之前 端面將記憶體晶片60之中央部60b加熱，記憶體晶片60之中央部60b將載置於控制晶片42之上之DAF44加熱。
此處，接合工具20之肋25a之前端面與記憶體晶片60之中央部60b之接觸面積小於接合工具20之第1周緣區域A與記憶體晶片60之周緣部60a之接觸面積。又，流向肋25a之熱係自接合工具20之第2周緣區域C流過來之熱，其量小於自第2周緣區域C流至第1周緣區域A之熱量。又，如上所述，藉由凹部25而形成之隔熱層幾乎不使加熱器11之熱通過。因此，與上文中所說明之第1實施形態之情形相比，自接合工具20之第1中央區域B傳遞至記憶體晶片60之中央部60b之記憶體晶片60之每單位面積之熱量進一步變少，記憶體晶片60之中央部60b之每單位面積之熱輸入亦進一步變少。因此，記憶體晶片60之中央部60b之溫度亦進一步降低。
藉此，能夠使用耐熱溫度低於第1實施形態之接合裝置100之DAF44，使焊錫球41熔融，並且使耐熱溫度低於焊錫球41之熔融溫度之DAF44不發生劣化地熱硬化而將記憶體晶片60安裝於基板40、控制晶片42之上。
<第5實施形態>
其次，一面參照圖11至13一面對第5實施形態之接合裝置500進行說明。如圖11所示，第5實施形態之接合裝置500係於上文中所說明之第4實施形態之接合裝置400之接合工具20之下表面24設置參照圖4至6所說明之冷卻流路28，且於上表面22設置有凹部34、被間隔開之凹部33及將凹部33與冷卻流路28連通之空氣孔35者。對與參照圖4至6所說明之第 2實施形態之接合裝置200及參照圖8至10所說明之第4實施形態之接合裝置400相同之部位標註相同之符號並省略說明。
如圖11、12所示，第2面即上表面22之凹部34係設置於與下表面24之第1中央區域B對應之範圍，且界定第2中央區域D。凹部34之外周側之上表面22為第2周緣區域C。於凹部34之中心設置有與下表面之內周冷卻流路28b連通之真空孔30。又，如圖11所示，設置於加熱器11之真空孔13與凹部34連通。
如圖12所示，於凹部34之一邊形成有向凹部34之內周側突出且於其中設置有凹部33之台座34a。台座34a之表面與上表面22成為同一面。凹部33與凹部34係藉由台座34a之壁而區分，且以空氣不連通之方式構成。於凹部33設置有與外周冷卻流路28a連通之空氣孔35。又，如圖11所示，加熱器11之空氣孔15與凹部33連通。再者，第2周緣區域C包含台座34a。
如圖11之箭頭93所示，自接合頭10之空氣孔14流入至加熱器11之空氣孔15之冷卻空氣流入至接合工具20之上表面22之凹部33，且自凹部33通過空氣孔35而流入至外周冷卻流路28a。與上文中參照圖5所進行之說明相同，流入至外周冷卻流路28a之冷卻空氣係如圖5之箭頭95、96所示般沿著凹部23a之內周面流動之後，流入至內周冷卻流路28b，並通過突起27之間而自真空孔30流入至上表面22之凹部34。然後，流入至凹部34之空氣通過加熱器11、接合頭10之各真空孔13、12而如圖11之箭頭94般流向真空裝置VAC。雖於外周冷卻流路28a、內周冷卻流路28b、凹部34中流通有冷卻空氣，但壓力接近於真空。因此，接合工具20藉由凹 部34之真空而真空吸附於加熱器11，冷卻流路28之真空將記憶體晶片60真空吸附。
如圖13所示，若接合裝置500之未圖示之控制部使接合頭10自圖11所示之狀態朝向平台50下降，則記憶體晶片60之中央部60b之下表面藉由經由接合工具20之間隔壁26、突起27而傳遞之向下之負載而將載置於控制晶片42之上之DAF44向下按壓。記憶體晶片60之周緣部60a之下表面藉由經由接合工具20之第1周緣區域A而傳遞之向下之負載而將焊錫球41向下按壓。又，若打開加熱器11，則加熱器11之熱如箭頭91所示般，自接合工具20之第2周緣區域C通過第1周緣區域A之整個面將記憶體晶片60之周緣部60a加熱，記憶體晶片60之周緣部60a將焊錫球41加熱。又，加熱器11之熱如箭頭87所示般，不通過流通有冷卻空氣之凹部34，而自接合工具20之第2周緣區域C通過第1中央區域B之間隔壁26之前端面與突起27之前端面而將記憶體晶片60之中央部60b加熱，記憶體晶片60之中央部60b將載置於控制晶片42之上之DAF44加熱。
第5實施形態之接合裝置500之接合工具20係於上表面22之第2中央區域D之凹部34、下表面24之第1中央區域B之冷卻流路28均流通冷卻空氣，故而與上文中所說明之第4實施形態之接合裝置400相比，記憶體晶片60之中央部60b之每單位面積之熱輸入變小，從而記憶體晶片60之中央部60b之溫度亦進一步降低。
藉此，接合裝置500能夠使用耐熱溫度低於上文中所說明之第4實施形態之接合裝置400之DAF44，使焊錫球41熔融，並且使耐熱溫度低於焊錫球41之熔融溫度之DAF44不發生劣化地熱硬化而將記憶體晶片 60安裝於基板40、控制晶片42之上。
<第6實施形態>
其次，一面參照圖14一面對第6實施形態之接合裝置600進行說明。接合裝置600係於接合工具20之下表面24之第1中央區域B與上表面之第2中央區域D安裝有熱導率低於第1周緣區域A、第2周緣區域C之隔熱材料31、39者。對與上文中參照圖7所說明之第3實施形態之接合裝置300相同之部分標註相同之符號並省略說明。
本實施形態之接合裝置600由於在接合工具20之第1中央區域B、第2中央區域D安裝有熱導率低於第1周緣區域A、第2周緣區域C之隔熱材料31、39，故而與上文中所說明之第3實施形態之接合裝置300相比，自接合工具20之第1中央區域B傳遞至記憶體晶片60之中央部60b之記憶體晶片60之每單位面積之熱量較小，記憶體晶片60之中央部60b之每單位面積之熱輸入亦較小，從而記憶體晶片60之中央部60b之溫度較接合裝置300之情形時降低。
藉此，接合裝置600能夠使用耐熱溫度低於上文中所說明之第3實施形態之接合裝置300之DAF44，使焊錫球41熔融，並且使耐熱溫度低於焊錫球41之熔融溫度之DAF44不發生劣化地熱硬化而將記憶體晶片60安裝於基板40、控制晶片42之上。
<第7實施形態>
其次，一面參照圖15一面對第7實施形態之接合裝置700進行說明。接合裝置700係於第1實施形態之接合裝置100之平台50設置有冷卻流路58者。對與上文中參照圖1至3所說明之接合裝置100相同之部分標註相 同之符號並省略說明。
如圖15所示，接合裝置700係於與接合有控制晶片42之基板40之第1區域E對向之平台50之第1部分50b設置凹部51，且於該凹部51中與參照圖5所進行之說明同樣地設置大致U字型之間隔壁52，於間隔壁52之內周側設置突起53，而形成與參照圖5所說明者相同之冷卻流路58。於凹部51之一端設置有使冷卻空氣流入至冷卻流路58之空氣孔54，於凹部51之中央設置有使冷卻空氣與真空裝置VAC連通之真空孔55。自空氣孔54流入至冷卻流路58之空氣係於冷卻流路58之中流通後，自真空孔55排出。雖然冷卻空氣於冷卻流路58流通，但其壓力大致為真空，而真空吸附基板40。
基板40之安裝有控制晶片42之範圍之外側為基板40之第2區域F，基板40之第2區域F與平台50之表面50a接觸。於基板40之第2區域F形成有焊錫球41。與基板40之第2區域F對向之平台50之區域為平台50之第2部分50c。
如圖15所示，若接合裝置700之未圖示之控制部使接合頭10朝向平台50下降，則加熱器11之熱如圖15之箭頭97所示般通過接合工具20之第1周緣區域A將記憶體晶片60之周緣部60a加熱，記憶體晶片60之周緣部60a將焊錫球41加熱。焊錫球41之熱自基板40之第2區域F流向平台50之第2部分50c。又，加熱器11之熱如圖15之箭頭98所示般，通過接合工具20之第1中央區域B將記憶體晶片60之中央部60b加熱，記憶體晶片60之中央部60b將載置於控制晶片42之上之DAF44加熱。然後，將DAF44加熱後之熱通過控制晶片42、樹脂43而流向平台50之第1部分 50b。
由於在平台50之冷卻流路58流通有冷卻空氣，故而熱容易自基板40之第1區域E流至平台50之第1部分50b。另一方面，形成有焊錫球41之基板40之第2區域F雖與平台50之表面50a相接，但未形成冷卻流路58，故而與第1區域E相比自基板40流至平台50之第2部分50c之熱量變少。亦即，自基板40之第1區域E傳遞至平台50之第1部分50b之基板40之每單位面積的熱量大於自基板40之第2區域傳遞至平台50之第2部分之基板40之每單位面積的熱量。因此，基板40之中央之第1區域E之溫度低於周圍之基板40之第2區域F之溫度。藉此，安裝於基板40之第1區域E之控制晶片42之上所載置之DAF44之溫度低於形成於基板40之第2區域F之焊錫球41之溫度。
因此，於接合裝置700中，與上文中所說明之第1實施形態之接合裝置100相比DAF44之溫度變得更低，能夠使用耐熱溫度低於接合裝置100之DAF44，使焊錫球41熔融，並且使耐熱溫度低於焊錫球41之熔融溫度之DAF44不發生劣化地熱硬化而將記憶體晶片60安裝於基板40、控制晶片42之上。
再者，於接合裝置700中，使用熱導率較低之材料作為平台50之材料能夠使自基板40之第2區域F逃逸至平台50之第2部分50c之熱量變少，從而能夠將焊錫球41之溫度保持得較高。因此，若由陶瓷系之材料構成平台50，則可獲得更大之效果。
<第8實施形態>
其次，一面參照圖16一面對第8實施形態之接合裝置800進行說明。 接合裝置800係將平台50之第1部分50b設為平面構造且於第2部分50c設置有凹部56者。於以下之說明中，對與上文中參照圖1至3所說明之接合裝置100及參照圖15所說明之接合裝置700相同之部分標註相同之符號並省略說明。接合裝置800之平台50與上文中所說明之接合裝置700不同，由熱導率較高之例如銅或鐵等材料構成。
於平台50設置於第2部分50c之凹部56構成空氣之隔熱層，故而阻斷熱自基板40之第2區域F向平台50之第2部分50c之流動。另一方面，由於平台50由銅或鐵等熱導率較高之材料構成，故而自基板40之第1區域E向平台50之第1部分50b之熱阻低於自基板40之第2區域F向平台50之第2部分50c之熱阻。因此，自基板40之第1區域E傳遞至平台50之第1部分50b之基板40之每單位面積的熱量大於自基板40之第2區域傳遞至平台50之第2部分50c之基板40之每單位面積的熱量，從而基板40之中央之第1區域E之溫度低於周圍之基板40之第2區域F之溫度。藉此，與上文中所說明之接合裝置700相同，安裝於基板40之第1區域E之控制晶片42之上所載置的DAF44之溫度低於形成於基板40之第2區域F之焊錫球41之溫度。
因此，接合裝置800與接合裝置700相同，與上文中所說明之第1實施形態之接合裝置100相比DAF44之溫度變得更低，能夠使用耐熱溫度低於接合裝置100之DAF44，使焊錫球41熔融，並且使耐熱溫度低於焊錫球41之熔融溫度之DAF44不發生劣化地熱硬化而將記憶體晶片60安裝於基板40、控制晶片42之上。
作為於平台50之表面50a形成凹部56之構造，考慮各種各 樣之構造，但於在基板40安裝有複數個控制晶片42之情形時，如圖17所示，亦可於將基板40吸附固定於平台50之表面時將控制晶片42所處之部分、即相當於第1部分50b之部分設為表面平坦之台座59，且於位於台座59之周圍之相當於第2部分50c之部分設置凹部56。
再者，本發明並不限定於以上所說明之實施形態，而包含不脫離由申請專利範圍限定之本發明之技術性範圍或本質之所有變更及修正。
10‧‧‧接合頭
11‧‧‧加熱器
12、13、30‧‧‧真空孔
20‧‧‧接合工具
21‧‧‧基底
21a、50a‧‧‧表面
22‧‧‧上表面
23‧‧‧島部
24‧‧‧下表面
25‧‧‧凹部
25a‧‧‧肋
40‧‧‧基板
41‧‧‧焊錫球
42‧‧‧控制晶片
43‧‧‧樹脂
44‧‧‧DAF
50‧‧‧平台
60‧‧‧記憶體晶片
60a‧‧‧周緣部
60b‧‧‧中央部
100‧‧‧接合裝置
A‧‧‧第1周緣區域
B‧‧‧第1中央區域
VAC‧‧‧真空裝置

Claims (13)

  1. 一種接合裝置，其特徵在於，具備：加熱器；及接合工具，具有：第1面，其吸附接合構件；及第2面，其與上述第1面為相反側且安裝於上述加熱器；上述第1面之第1周緣區域將上述接合構件之周緣部按壓至第1構件，上述第1面之第1中央區域將上述接合構件之中央部按壓至耐熱溫度較上述第1構件低之第2構件；自上述接合工具之上述第1中央區域傳遞至上述接合構件之中央部之上述接合構件之每單位面積的熱量，小於自上述接合工具之上述第1周緣區域傳遞至上述接合構件之周緣部之上述接合構件之每單位面積的熱量。
  2. 如申請專利範圍第1項之接合裝置，其中，上述接合工具之上述第1中央區域相較於上述接合工具之上述第1周緣區域而言與上述接合構件之接觸面積較小。
  3. 如申請專利範圍第1或2項之接合裝置，其中，於上述接合工具之上述第1中央區域呈格子狀配置有複數個凹部。
  4. 如申請專利範圍第1或2項之接合裝置，其中，上述接合工具之上述第1中央區域具有供冷卻空氣流通之冷卻流路。
  5. 如申請專利範圍第1項之接合裝置，其中，上述接合工具之上述第1中央區域由熱導率低於上述接合工具之上述第1周緣區域之材料構成。
  6. 如申請專利範圍第1至5項中任一項之接合裝置，其中，上述接合工具之上述第2面具有與上述第1中央區域對應之第2中央 區域及上述第2中央區域之外周側之第2周緣區域，自上述加熱器之中央部傳遞至上述接合工具之上述第2中央區域之上述加熱器之每單位面積的熱量，小於自上述加熱器之周緣部傳遞至上述接合工具之上述第2周緣區域之上述加熱器之每單位面積的熱量。
  7. 如申請專利範圍第6項之接合裝置，其中，上述接合工具之上述第2中央區域相較於上述接合工具之上述第2周緣區域而言與上述加熱器之接觸面積較小。
  8. 如申請專利範圍第7項之接合裝置，其中，於上述接合工具之上述第2中央區域呈格子狀配置有複數個凹部。
  9. 如申請專利範圍第6或7項之接合裝置，其中，上述接合工具之上述第2中央區域具有供冷卻空氣流通之冷卻流路。
  10. 如申請專利範圍第6項之接合裝置，其中，上述接合工具之上述第2中央區域由熱導率低於上述接合工具之上述第2周緣區域之材料構成。
  11. 如申請專利範圍第1至10項中任一項之接合裝置，其具備吸附固定基板之平台，上述第2構件載置於接合於上述基板之電子零件之上，上述第1構件形成於上述電子零件之周圍之上述基板之上，自接合有上述電子零件之上述基板之第1區域傳遞至與上述基板之上述第1區域對向之上述平台之第1部分的上述基板之每單位面積之熱量，大於自配置有上述第1構件之上述基板之第2區域傳遞至與上述基板之上述第2區域對向之上述平台之第2部分的上述基板之每單位面積之熱量。
  12. 如申請專利範圍第11項之接合裝置，其中，上述平台係於上述第1部分設置有供冷卻空氣流通之冷卻流路。
  13. 如申請專利範圍第11項之接合裝置，其中，上述平台係於上述第2部分之表面設置有凹部。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI684525B (zh) * 2019-05-31 2020-02-11 頂瑞機械股份有限公司 真空壓合機
TWI759944B (zh) * 2019-11-22 2022-04-01 美商美光科技公司 半導體之熱壓結合中的污染物控制及相關系統和方法
TWI790118B (zh) * 2022-02-10 2023-01-11 友達光電股份有限公司 接合設備

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102471274B1 (ko) * 2018-02-13 2022-11-28 삼성전자주식회사 리플로우를 위한 스택 툴 및 이를 포함하는 리플로우 장치
JP6691197B1 (ja) * 2018-12-12 2020-04-28 エイチアンドセオン カンパニー リミテッドＨ＆ｃｅｏｎ ｃｏ．， ｌｔｄ． ヒーターアセンブリー
JP7368962B2 (ja) * 2019-07-09 2023-10-25 芝浦メカトロニクス株式会社 実装装置
TW202119533A (zh) * 2019-11-04 2021-05-16 台灣愛司帝科技股份有限公司 具有晶片吸附功能的晶片承載結構
KR20210157200A (ko) 2020-06-19 2021-12-28 삼성전자주식회사 칩 본딩 장치
TWI790747B (zh) * 2021-09-15 2023-01-21 日商新川股份有限公司 基板保持具以及接合系統和接合方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3509474B2 (ja) * 1997-06-05 2004-03-22 松下電器産業株式会社 バンプ付きワークのボンディング装置およびボンディング方法
JP3381565B2 (ja) * 1997-07-29 2003-03-04 松下電器産業株式会社 バンプ付きワークのボンディング方法
US6347734B1 (en) * 2000-03-27 2002-02-19 Emc Corporation Methods and apparatus for installing a module on a circuit board using heating and cooling techniques
JP3791501B2 (ja) * 2003-02-26 2006-06-28 セイコーエプソン株式会社 回路基板、半導体装置、半導体製造装置、回路基板の製造方法および半導体装置の製造方法
US6943423B2 (en) * 2003-10-01 2005-09-13 Optopac, Inc. Electronic package of photo-image sensors in cellular phone camera modules, and the fabrication and assembly thereof
JP2008166527A (ja) 2006-12-28 2008-07-17 Spansion Llc 半導体装置およびその製造方法
JP5044319B2 (ja) * 2007-07-20 2012-10-10 オンセミコンダクター・トレーディング・リミテッド 半導体装置
JP4808283B1 (ja) * 2010-06-30 2011-11-02 株式会社新川 電子部品実装装置及び電子部品実装方法
US8651359B2 (en) * 2010-08-23 2014-02-18 International Business Machines Corporation Flip chip bonder head for forming a uniform fillet
JP2012146947A (ja) * 2010-12-22 2012-08-02 Seiko Instruments Inc 光学デバイス
JP2012199358A (ja) 2011-03-22 2012-10-18 Nec Corp チップ加熱ヘッド
JP2013098264A (ja) * 2011-10-28 2013-05-20 Sekisui Chem Co Ltd フリップチップボンダー用アタッチメント
JP5793473B2 (ja) * 2012-07-20 2015-10-14 株式会社新川 ボンディング装置用ヒータ及びその冷却方法
JP2015176906A (ja) 2014-03-13 2015-10-05 株式会社東芝 半導体装置および半導体装置の製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI684525B (zh) * 2019-05-31 2020-02-11 頂瑞機械股份有限公司 真空壓合機
TWI759944B (zh) * 2019-11-22 2022-04-01 美商美光科技公司 半導體之熱壓結合中的污染物控制及相關系統和方法
US11410964B2 (en) 2019-11-22 2022-08-09 Micron Technology, Inc. Contaminant control in thermocompression bonding of semiconductors and associated systems and methods
US11908828B2 (en) 2019-11-22 2024-02-20 Micron Technology, Inc. Contaminant control in thermocompression bonding of semiconductors and associated systems and methods
TWI790118B (zh) * 2022-02-10 2023-01-11 友達光電股份有限公司 接合設備

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