TW201731019A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW201731019A
TW201731019A TW105121516A TW105121516A TW201731019A TW 201731019 A TW201731019 A TW 201731019A TW 105121516 A TW105121516 A TW 105121516A TW 105121516 A TW105121516 A TW 105121516A TW 201731019 A TW201731019 A TW 201731019A
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transistor
region
insulating layer
thickness
sti
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TW105121516A
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TWI624005B (zh
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李佳叡
吳國銘
林怡君
亞歷山大 克爾尼斯基
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台灣積體電路製造股份有限公司
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Abstract

在一些實施例中，一種半導體裝置包括一第一電晶體及一第二電晶體。該第一電晶體包括：一第一源極區域，其在具有一第一濃度之一第一主體區域中；及一第一閘極。該第二電晶體包括一第二源極區域，該第二源極區域在具有高於該第一濃度的一第二濃度之一第二主體區域中。該第二源極區域與該第一源極區域及該第一閘極連接。

Description

半導體裝置
本發明是有關於一種半導體裝置，特別係有關於一種應用於電源供應器之半導體裝置。
如今，歸因於微電子學之快速發展，設計電力系統較為複雜。存在兩種主要類型的穩壓式電源供應器可用，切換式電源供應器及線性式電源供應器。因為切換式電源供應器比線性式電源供應器更有效率，故切換式電源供應器已變為流行趨勢，且已廣泛地用於諸如個人電腦之電子裝置中。
一些實施例具有以下特徵及/或優勢中之一者或組合。在一些實施例中，一種半導體裝置包括第一電晶體及第二電晶體。第一電晶體包括在具有第一濃度之第一主體區域中的第一源極區域，及第一閘極。第二電晶體包括在具有高於第一濃度的第二濃度之第二主體區域中的第二源極區域。第二源極區域與第一源極區域及第一閘極連接。
在一些實施例中，一種半導體裝置包括第一電晶體及第二電晶體。第一電晶體包括在第一主體區域中之第一源極區域、具有第一厚度的第一絕緣層及在第一絕緣層上之第一閘極。第二電晶體包括在第二主體區域中之第二源極區域、具有大於第一厚度之第二厚度的第二絕緣層，及在第二絕緣層上之第二閘極。第二源極區域與第一源極區 域及第一閘極區域連接。
在一些實施例中，一種形成半導體裝置之方法包括：提供包括分別與第一電晶體及第二電晶體相關聯之第一裝置區域及第二裝置區域的基板；在基板中形成井；在第一裝置區域中形成第一經圖案化絕緣層，該第一經圖案化絕緣層具有第一厚度；在第二裝置區域中形成第二經圖案化絕緣層，該第二經圖案化絕緣層具有大於第一厚度的第二厚度；在第一經圖案化絕緣層上形成第一閘極；在井中在第一裝置區域及第二裝置區域中分別形成第一主體區域及第二主體區域；在第一主體區域及第二主體區域中分別形成第一源極區域及第二源極區域；及將第一源極區域、第一閘極及第二源極區域連接在一起。
10‧‧‧電路
11‧‧‧供電電路
12‧‧‧電感器
14‧‧‧電容器
16‧‧‧閘極驅動器
18‧‧‧本質二極體
19‧‧‧旁路單元
20‧‧‧半導體裝置
21‧‧‧第一電晶體
22‧‧‧第二電晶體
201‧‧‧基板
202‧‧‧井
204‧‧‧摻雜區域
206‧‧‧導電組件
207‧‧‧互連件
210‧‧‧第一主體區域
211‧‧‧第一源極區域
212‧‧‧第一通道
213‧‧‧第一絕緣層
214‧‧‧第一多晶層
220‧‧‧第二主體區域
221‧‧‧第二源極區域
222‧‧‧第二通道
223‧‧‧第二絕緣層
224‧‧‧第二多晶層
301‧‧‧基板
302‧‧‧井
303‧‧‧經圖案化絕緣層
304‧‧‧經圖案化絕緣層
305‧‧‧第一多晶層
306‧‧‧第二多晶層
307‧‧‧第一主體區域
308‧‧‧第二主體區域
309‧‧‧第一絕緣層
310‧‧‧第二絕緣層
311‧‧‧第一源極區域
312‧‧‧摻雜區域
313‧‧‧第二源極區域
314‧‧‧導電組件
315‧‧‧互連件
400A‧‧‧方法
400B‧‧‧方法
401‧‧‧操作
402‧‧‧操作
403‧‧‧操作
404‧‧‧操作
405‧‧‧操作
406‧‧‧操作
407‧‧‧操作
408‧‧‧操作
410‧‧‧操作
411‧‧‧操作
601‧‧‧曲線
602‧‧‧曲線
2031‧‧‧第一淺溝槽隔離(STI)
2032‧‧‧第二淺溝槽隔離(STI)
3031‧‧‧第一淺溝槽隔離(STI)
3032‧‧‧第二淺溝槽隔離(STI)
D‧‧‧第三電晶體Mb之汲極
D1‧‧‧第一源極區域211與摻雜區域204之間的中心至中心距離
D2‧‧‧第二源極區域221與摻雜區域204之間的中心至中心 距離
G‧‧‧第三電晶體Mb之閘極
GND‧‧‧參考
L1‧‧‧第一長度
L2‧‧‧第二長度
M1‧‧‧第一電晶體
M2‧‧‧第二電晶體
Mb‧‧‧第三電晶體
P1‧‧‧點
PA1‧‧‧第一路徑
PA2‧‧‧第二路徑
S‧‧‧第三電晶體Mb之源極
VDD‧‧‧電力供應
Vout‧‧‧電壓
W1‧‧‧第一厚度
W2‧‧‧第二厚度
當結合附圖閱讀時，自以下詳細描述最佳地理解本揭露之態樣。應注意，根據業界中之標準慣例，各種構件未按比例繪製。實際上，為論述清楚起見，可任意地增大或減小各種構件之尺寸。
圖1為根據一些實施例之電路的圖。
圖2為根據一些實施例之半導體裝置的剖面圖。
圖3A至圖3J為根據一些實施例之展示製造半導體裝置之方法的圖。
圖4A為根據一些實施例之說明形成半導體裝置之方法的流程圖。
圖4B為根據一些實施例之說明形成半導體裝置之另一方法的流程圖。
圖5為展示具有及不具有在圖1中說明之旁路單元的電路之模擬結果的示意圖。
以下揭示內容提供用於實施本發明之不同構件的許多不同實施 例或實例。下文描述組件及配置之特定實例以簡化本揭露。當然，此等組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一構件在第二構件上方或上之形成可包括第一構件與第二構件直接接觸地形成之實施例，且亦可包括額外構件可在第一構件與第二構件之間形成使得第一構件與第二構件可不直接接觸之實施例。另外，本揭露可在各種實例中重複參考數字及/或字母。此重複係出於簡化及清楚之目的，且本身並不指示所論述各種實施例及/或組態之間的關係。
圖1為根據一些實施例之一電路10的圖。參看圖1，電路10在界定於電源供應電壓VDD與參考電壓GND(例如，接地位準)之間的功率域中操作。電路10包括供電電路11及旁路單元19。供電電路11經組態以將電源供應電壓VDD轉換為輸出處之電壓Vout，且旁路單元19經組態以將電流導向輸出，如下文將詳細地描述。
供電電路11包括第一電晶體M1、第二電晶體M2、電感器12、電容器14及閘極驅動器16。閘極驅動器16用於將脈衝信號輸出至第一電晶體M1及第二電晶體M2中之每一者的閘極，以便切換第一電晶體M1及第二電晶體M2之導通狀態。電壓Vout之電壓位準可取決於脈衝信號之工作週期。
第一電晶體M1之閘極耦接至閘極驅動器16。第一電晶體M1之源極接收供電電壓VDD。第一電晶體M1之汲極耦接至電感器12之一個末端。在本實施例中，第一電晶體M1包括p型金屬氧化物半導體(p-type metal-oxide semiconductor，PMOS)電晶體。
第二電晶體M2之閘極耦接至閘極驅動器16。第二電晶體M2之汲極耦接至第一電晶體M1之汲極，且亦耦接至電感器12之該末端。第二電晶體M2之源極耦接至參考電壓GND。此外，第二電晶體M2包括本質二極體(intrinsic body diode)18，本質二極體18為p型井區域與 n型區域之間的PN接面二極體。本質二極體18具有耦接至第二電晶體M2之源極的陽極，及耦接至第二電晶體M2之汲極的陰極。在本實施例中，第二電晶體M2包括n型MOS(NMOS)電晶體。在一些實施例中，第二電晶體M2包括側向擴散MOS電晶體(laterally diffused MOS transistor，LDMOS)。
耦接在第二電晶體M2之汲極與參考電壓GND之間的旁路單元19經組態以旁通自參考電壓GND旁通至電感器12及電容器14的電流。旁路單元19包括第三電晶體Mb。第三電晶體Mb之汲極D耦接至第二電晶體M2之汲極。第三電晶體Mb之閘極G耦接至參考電壓GND。第三電晶體Mb之源極S耦接至參考電壓GND，且亦耦接至閘極G。結果，第三電晶體Mb為具有一連接二極體形式(diode-connected)之電晶體。因為第三電晶體Mb之閘極至源極電壓(VGS)大體上等於零且因此小於其臨界電壓，故第三電晶體Mb保持在不導通(非導電)狀態下。更具體言之，第三電晶體Mb在次臨限值區域中操作。在本實施例中，第三電晶體Mb包括NMOS電晶體。在一些實施例中，第三電晶體Mb包括側向擴散MOS電晶體(LDMOS)。
為了防止電源供應電壓VDD與參考電壓GND之間的短路，引入被稱作「停滯時間(dead time)」的時間段，使得第一電晶體M1及第二電晶體M2兩者維持在不導通狀態下。然而，在停滯時間期間，可能引發本質二極體反向復原問題，反向復原問題可能不利地影響電壓Vout。在操作中，因應於來自閘極驅動器16之脈衝信號，第一電晶體M1導通而第二電晶體M2不導通。來自電源供應電壓VDD之電流經過源極沿著第一路徑PA1朝向輸出流動至第一電晶體M1之汲極，為電感器12及電容器14充電。隨後，閘極驅動器16反轉第一電晶體M1及第二電晶體M2之導通狀態。在完全地反轉第一電晶體M1及第二電晶體M2之導通狀態之前，第一電晶體M1及第二電晶體M2在停滯時間中不 導通。來自參考電壓GND之電流沿著第二路徑PA2為電感器12及電容器14充電。在不含旁路機制之一些現有方法中，充電電流將流過本質二極體18，且引發不合需要的本質二極體反向復原。
為了緩解本質二極體反向復原，旁路單元19與本質二極體18並聯連接，以便使來自參考電壓GND的電流旁通。旁路單元19具有小於本質二極體18之臨界電壓的臨界電壓。舉例而言，旁路單元19之臨界電壓大致為0.3伏特(V)，且本質二極體18之臨界電壓大致為0.7V。因此，旁路單元19在本質二極體18導電之前導電。因為有了旁路單元19，來自參考電壓GND之電流的相當大部分在停滯時間期間經過電感器12及電容器14朝向輸出流動，藉此減小流過本質二極體18的電流。以此方式，本質二極體反向復原問題得以緩解。有效地，來自參考電壓GND之大體上全部電流流過旁路單元19且繞開本質二極體18，以使得本質二極體反向復原問題得以消除。
旁路單元19能與電晶體一起實現，因而具有相對低之面積成本。在一些現有方法中，係採用晶片外的旁路裝置或肖特基二極體(Schottky diode)來解決本質二極體反向復原之問題。然而，此類方法可能遭受相對高之面積成本。
旁路單元19具有之崩潰電壓(諸如12V、16V或20V)取決於旁路單元19之半導體結構，此將參看圖2加以詳細地描述。此外，旁路單元19之面積隨著旁路單元19之崩潰電壓減小而減小。因為所要崩潰電壓及因此旁路單元19之面積可預先判定，旁路單元19在電路設計中提供靈活性。
舉例而言，若在應用中需要電路10在相對高電源供應電壓VDD(諸如20V)下操作，則設計者根據電源供應電壓VDD之電壓位準(亦即，20V)來判定旁路單元19之崩潰電壓為20V。在操作中，當第一電晶體M1導通且第二電晶體M2不導通時，第二電晶體M2之汲極處的電 壓位準大致為20V。若旁路單元19之崩潰電壓為5V，則旁路單元19將不能夠耐受橫跨旁路單元19之電壓差(20V)，因此旁路單元19之崩潰將發生。若旁路單元19之崩潰產生，則電路10可能不正確地起作用。
另一方面，若在另一應用中需要電路10在相對低電源供應電壓VDD(諸如5V)下操作，則設計者根據5V之電源供應電壓VDD來判定旁路單元19之崩潰電壓為5V。因為旁路單元19之面積隨著旁路單元19之崩潰電壓減小而減小，故用於5V應用之旁路單元19可設計成具有比用於20V應用之旁路單元19小的面積。結果，可取決於應用來使旁路單元19之崩潰電壓及面積最佳化。
在將肖特基二極體用作旁路裝置的一些現有方法中，肖特基二極體之崩潰電壓由肖特基二極體之材料判定，材料可包括金屬及矽。在不改變材料的情況下，無法改變肖特基二極體之崩潰電壓。然而，改變材料使得半導體製造過程複雜。結果，肖特基二極體之崩潰電壓並不靈活，且無法針對不同應用來使肖特基二極體之面積最佳化。
圖2為根據一些實施例之半導體裝置20的剖面圖。參看圖2，半導體裝置20包括第一電晶體21及第二電晶體22。此外，參看圖1所描述且說明之第三電晶體Mb與第一電晶體21一起實施，且參看圖1所描述且說明之第二電晶體M2與第二電晶體22一起實施。為方便起見，在圖2中僅展示第二電晶體22(對應於圖1中之第二電晶體M2)及相關聯第一電晶體21(對應於在圖1中充當用於第二電晶體M2之旁路單元的第三電晶體Mb)，且並不說明圖1中之第一電晶體M1。
第一電晶體21包括在基板201上之第一絕緣層213、在第一絕緣層213上之第一多晶層214、第一源極區域211、第一汲極區域及基板201中之第一通道212。第一源極區域211在基板201之井202中形成於第一主體區域210中。第一汲極區域由井202及在井202中安置於淺溝槽隔離(STI)2031與STI 2032之間的摻雜區域204界定。第一通道212 界定於第一源極區域211與第一STI 2031之間的第一主體區域210中，且下伏於第一絕緣層213下方。第一主體區域210與第一多晶層214之一部分重疊。在一些實施例中，基板201包括p型基板，且井202包括高電壓n井(HVNW)。此外，摻雜區域204及第一源極區域211中之每一者包括n型雜質，而第一主體區域210包括p型雜質。結果，在第一多晶層214充當第一閘極的情況下，第一電晶體21包括NMOS電晶體結構。
在一些實施例中，第一絕緣層213包括氧化物層。第一絕緣層213具有第一厚度W1，第一厚度W1範圍介於約25埃至約60埃。第一厚度W1為判定第一電晶體21之臨界電壓的因素。
第一主體區域210充當第一電晶體21之本體(body)。此外，第一主體區域210具有第一濃度，第一濃度範圍介於約5×1015cm-3至1×1016cm-3。第一濃度亦為判定第一電晶體21之臨界電壓的因素。
在第一主體區域210與摻雜區域204之間的第一STI 2031在第一通道212延伸的方向上具有第一長度L1。在一些實施例中，第一源極區域211與摻雜區域204之間的中心至中心距離D1隨著第一長度L1增大而增大，且隨著第一長度L1減小而減小。此外，第一長度L1及與其有關的距離D1為判定第一電晶體21之崩潰電壓的因素。
類似地，第二電晶體22包括在基板201上之第二絕緣層223、在第二絕緣層223上之第二多晶層224，及第二源極區域221、第二汲極區域及基板201中之第二通道222。第二源極區域221在基板201之井202中形成於第二主體區域220中。類似於第一汲極區域，第二汲極區域亦由井202及在井202中安置於STI 2031與STI 2032之間的摻雜區域204界定。摻雜區域204用於充當第一電晶體21及第二電晶體22之汲極。第二通道222界定於第二源極區域221與第二STI 2032之間的第二主體區域220中，且下伏於第二絕緣層223下方。第二主體區域220與 第二多晶層224之一部分重疊。如先前論述，基板201包括p型基板，且井202包括高電壓n井(HVNW)。此外，摻雜區域204及第二源極區域221中之每一者包括n型雜質，而第二主體區域220包括p型雜質。結果，在第二多晶層224充當第二閘極的情況下，第二電晶體22包括NMOS電晶體結構。
在一些實施例中，第二絕緣層223包括氧化物層。第二絕緣層223具有第二厚度W2，第二厚度W2範圍介於約100埃至約350埃。第二厚度W2為判定第二電晶體22之臨界電壓的因素。
第二主體區域220充當第二電晶體22之本體。此外，第二主體區域220具有第二濃度，第二濃度範圍介於約1.5×1016cm-3至2×1017cm-3。第二濃度亦為判定第二電晶體22之臨界電壓的因素。
在第二主體區域220與摻雜區域204之間的第二STI 2032在第二通道222延伸的方向上具有第二長度L2。在一些實施例中，第二源極區域221與摻雜區域204之間的中心至中心距離D2隨著第二長度L2增大而增大，且隨著第二長度L2減小而減小。此外，第二長度L2及與其有關之距離D2為判定第二電晶體22之崩潰電壓的因素。
為了緩解本質二極體反向復原問題，第二電晶體22設計成具有比第一電晶體21大的臨界電壓。在一實施例中，第二濃度高於第一濃度，以使得第二電晶體22具有大於第一電晶體21之臨界電壓的臨界電壓。在另一實施例中，第二厚度W2大於第一厚度W1，從而導致較大之臨界電壓。在再一實施例中，第二厚度W2大於第一厚度W1，且第二濃度大於第一濃度。在又另一項實施例中，第二厚度W2大於第一厚度W1，而第二濃度等於第一濃度。在又一項實施例中，第二濃度高於第一濃度，而第二厚度W2等於第一厚度W1。有效地，本質二極體反向復原問題得以緩解或甚至消除，而無需犧牲肖特基二極體中原本所需要的面積成本。
此外，如上所述，設計者能夠根據電源供應電壓VDD來判定第一電晶體21及第二電晶體22中之每一者的所要崩潰電壓。因為第一電晶體21之崩潰電壓與第一長度L1(或距離D1)相關聯，且第二電晶體22之崩潰電壓與第二長度L2(或距離D2)相關聯，故藉由調整第一長度L1或第二長度L2或兩者，設計者可在製造半導體裝置20之前對其進行設計。以此方式，使由第一電晶體21及第二電晶體22消耗的面積最佳化。
導電組件206形成於第一源極區域211、第二源極區域221、第一多晶層214、第二多晶層224及摻雜區域204上，以充當用於電連接的接點(pick-up)。此外，亦參看圖1中之電晶體Mb及M2，第一源極區域211、第一多晶層214及第二源極區域221以電氣方式連接至互連件207。
圖3A至圖3J為根據一些實施例之展示製造半導體裝置之方法的圖式。參看圖3A，提供基板301。基板301包括第一裝置區域及第二裝置區域，其中分別將形成第一電晶體及第二電晶體。第一裝置區域及第二裝置區域分別與第一電晶體及第二電晶體相關聯。在一些實施例中，基板301包括p型基板。
參看圖3B，藉由按次序連續執行之(例如)沈積製程、蝕刻製程、拉回製程、退火製程及化學機械平坦化製程而在基板301中形成第一STI 3031及第二STI 3032。STI 3031及3032分別安置於第一裝置區域及第二裝置區域中。
參看圖3C，藉由(例如)離子佈植製程繼之以驅入製程而在基板301中形成井302。在一些實施例中，井302包括高電壓n井(HVNW)。
參看圖3D，藉由沈積製程繼之以蝕刻製程而在基板301上形成經圖案化絕緣層303，從而暴露在第一裝置區域中的井302。在一些實施例中，經圖案化絕緣層303包括氧化物層。
參看圖3E，在第一裝置區域中藉由(例如)沈積製程來在基板301上形成經圖案化絕緣層304。在一些實施例中，經圖案化絕緣層304包括氧化物層。如先前論述且如本實施例中所展示，作為緩解本質二極體反向復原問題的方法，經圖案化絕緣層303之厚度大於經圖案化絕緣層304之厚度。在其他實施例中，圖3D及圖3E中之形成具有不同厚度之絕緣層的製程由藉由(例如)沈積製程在基板301上形成單一絕緣層替換。在該情況下，絕緣層在第一裝置區域與第二裝置區域中具有均一厚度。為了緩解本質二極體反向復原問題，隨後將形成於第一裝置區域與第二裝置區域中的主體區域以不同濃度摻雜。
參看圖3F，藉由(例如)沈積製程繼之以蝕刻製程來在絕緣層303及304上形成經圖案化多晶層，從而導致在第一裝置區域中形成第一多晶層305，且在第二裝置區域中形成第二多晶層306。第一多晶層305與第一STI 3031之一部分重疊，且用於充當第一電晶體之第一閘極。與第一多晶層305分開之第二多晶層306與第二STI 3032之一部分重疊，且用於充當第二電晶體之第二閘極。
參看圖3G，藉由(例如)離子佈植製程，在井302中在第一裝置區域中界定第一主體區域307，且在井302中在第二裝置區域中界定第二主體區域308。如先前論述，作為緩解本質二極體反向復原問題的另一方法，第二主體區域308之濃度大於第一主體區域307之濃度。具體言之，藉由在井302中摻雜一雜質類型之雜質第一預定次數以便界定第一主體區域307且藉由在井302中摻雜該該雜質類型之雜質第二預定次數以便界定第二主體區域308而形成在井302中在第一裝置區域中的第一主體區域307及在井302中在第二裝置區域中的第二主體區域308。第二預定次數大於第一預定次數。
或者，藉由在第一主體區域307中摻雜第一雜質類型之具有第一濃度的雜質及第二雜質類型(與第一雜質類型相反)之具有小於第一濃 度之第二濃度的雜質且在第二主體區域308中摻雜第一雜質類型之雜質而形成在井302中在第一裝置區域中的第一主體區域307及在井302中在第二裝置區域中的第二主體區域308。因為在第一主體區域307中第一雜質類型之雜質的一部分與第二雜質類型之雜質失衡，因此僅第一雜質類型之雜質保持在第一主體區域307中。結果，第一主體區域307中之第一雜質類型之雜質的濃度小於第二主體區域308中之第二雜質類型之雜質的濃度。以此方式，第二濃度大於第一濃度。
參看圖3H，藉由(例如)蝕刻製程在基板301上形成第一絕緣層309及第二絕緣層310，從而暴露第一主體區域307之一部分、第二主體區域308之一部分及第一裝置區域與第二裝置區域之間的邊界。第一絕緣層309及第二絕緣層310分別用於充當第一電晶體及第二電晶體之閘極氧化物。
參看圖3I，藉由(例如)離子佈植製程而在第一主體區域307中界定第一源極區域311，在STI 3031與STI 3032之間在井302中界定摻雜區域312，且在第二主體區域308中界定第二源極區域313。
參看圖3J，藉由(例如)沈積製程繼之以蝕刻製程而在第一源極區域311、摻雜區域312、第二源極區域313、第一多晶層305及第二多晶層306上形成導電組件314。導電組件314充當用於電連接至互連件315的選取區域。此外，第一源極區域311、第一多晶層305及第二源極區域313一起連接至互連件315。
圖4A為根據一些實施例之說明形成半導體裝置之方法400A的流程圖。參看圖4A，在操作401中，提供基板。該基板包括第一裝置區域及第二裝置區域，其中分別將形成第一電晶體及第二電晶體。基板類似於分別參看圖2及圖3A描述且說明之基板201或基板301。
在操作402中，在基板中界定井。該井類似於分別參看圖2及圖3C描述且說明之井202或井302。在一實施例中，井包括HVNW。隨 後，在井中分別在第一裝置區域及第二裝置區域中形成第一STI及第二STI。
在操作403中，在基板上分別在第一裝置區域及第二裝置區域中形成第一經圖案化絕緣層及第二經圖案化絕緣層。第二經圖案化絕緣層具有大於第一經圖案化絕緣層之厚度的厚度。第一經圖案化絕緣層類似於參看圖3E描述且說明之經圖案化絕緣層304，且第二經圖案化絕緣層類似於參看圖3D描述且說明之經圖案化絕緣層303。在一實施例中，第一經圖案化絕緣層包括用於核心裝置的氧化物層，且第二經圖案化絕緣層包括用於I/O裝置的氧化物層。
在操作404中，在第一經圖案化絕緣層上形成第一多晶層，且在第二經圖案化絕緣層上形成第二經圖案化多晶層。第一多晶層充當第一電晶體之第一閘極，且第二多晶層充當第二電晶體之第二閘極。
在操作405中，在井中在第一裝置區域中界定第一主體區域，且在井中在第二裝置區域中界定第二主體區域。第一主體區域充當第一電晶體之本體，且第二主體區域充當第二電晶體之本體。在一些實施例中，第二主體區域具有大於第一主體區域之濃度的濃度。在一些實施例中，第二主體區域具有等於第一主體區域之濃度的濃度。第一主體區域及第二主體區域分別類似於參看圖3G描述且說明之第一主體區域307及第二主體區域308。
在操作406中，分別在第一主體區域、井及第二主體區域中界定第一源極區域、摻雜區域及第二源極區域。第一電晶體之第一汲極區域由井及摻雜區域界定，且第二電晶體之第二汲極區域亦由井及摻雜區域界定。
在操作407中，在第一源極區域、第二源極區域、摻雜區域、第一多晶層及第二多晶層上形成導電組件。導電組件充當用於電連接至互連件的選取區域。
在操作408中，第一源極區域、第一多晶層及第二源極區域一起連接至互連件。
圖4B為根據一些實施例之說明形成半導體裝置之另一方法400B的流程圖。參看圖4B，圖4B中展示之方法400B類似於圖4A中展示之方法400A，惟(例如)操作410替換操作403且操作411代替操作405除外。在操作410中，在基板上分別在第一裝置區域及第二裝置區域中形成第一經圖案化絕緣層及第二經圖案化絕緣層。在一些實施例中，第二經圖案化絕緣層具有大於第一經圖案化絕緣層之厚度的厚度。在其他實施例中，第二經圖案化絕緣層具有等於第一經圖案化絕緣層之厚度的厚度。
在操作411中，在井中在第一裝置區域中界定第一主體區域，且在井中在第二裝置區域中界定第二主體區域。第二主體區域具有大於第一主體區域之濃度的濃度。
圖5為展示具有及不具有第三電晶體Mb作為旁路單元的電路之模擬結果的示意圖。參看圖5，水平軸表示第二電晶體M2之源極至汲極電壓(VSD)，且垂直軸表示以微安(μA)計之電流的量值。曲線601表示當電路不具有第三電晶體Mb時流過本質二極體18的反向電流。曲線602表示當電路具備第三電晶體Mb時流過第三電晶體Mb的反向電流。
通常，反向電流之總量為流過本質二極體18之反向電流與流過第三電晶體Mb之反向電流的總和。因此，隨著流過第三電晶體Mb之反向電流的量增大，流過本質二極體18之反向電流的量減小。舉例而言，假設反向電流之總量為1安培(A)。當流過第三電晶體Mb之反向電流為0.6毫安(mA)時，流過本質二極體18的反向電流為0.4mA。此外，當流過第三電晶體Mb的反向電流增大至0.8mA時，流過本質二極體18的反向電流減小至0.2mA。結果，當流過本質二極體18之反向 電流的量減小時，本質二極體反向復原問題得以緩解。有效地，大體上全部的反向電流流過第三電晶體Mb且繞開本質二極體18，以使得本質二極體反向復原問題得以消除。
如圖5中所展示，如曲線602中所指示之流過第三電晶體Mb之反向電流的量值顯然大於如曲線601中所指示之流過本質二極體18之反向電流的量值。詳言之，在約0.6V之VSD下(0.6V為本質二極體18之導通電壓)，流過第三電晶體Mb之反向電流的量值在點P1處為流過本質二極體18的反向電流之量值的約1000倍。換言之，僅少量反向電流流過本質二極體18。因此，顯著地緩解了本質二極體反向復原問題。
前文概述若干實施例之特徵，使得熟習此項技術者可較佳地理解本揭露之態樣。熟習此項技術者應瞭解，其可易於使用本揭露作為設計或修改用於實現本文中所引入之實施例的相同目的及/或達成相同優勢的其他製程及結構的基礎。熟習此項技術者亦應認識到，此類等效構造並不脫離本揭露之精神及範疇，且其可在不脫離本揭露之精神及範疇的情況下在本文中進行各種改變、替代及更改。
20‧‧‧半導體裝置
21‧‧‧第一電晶體
22‧‧‧第二電晶體
201‧‧‧基板
202‧‧‧井
204‧‧‧摻雜區域
206‧‧‧導電組件
207‧‧‧互連件
210‧‧‧第一主體區域
211‧‧‧第一源極區域
212‧‧‧第一通道
213‧‧‧第一絕緣層
214‧‧‧第一多晶層
220‧‧‧第二主體區域
221‧‧‧第二源極區域
222‧‧‧第二通道
223‧‧‧第二絕緣層
224‧‧‧第二多晶層
2031‧‧‧第一淺溝槽隔離(STI)
2032‧‧‧第二淺溝槽隔離(STI)
D1‧‧‧第一源極區域211與摻雜區域204之間的中心至中心距離
D2‧‧‧第二源極區域221與摻雜區域204之間的中心至中心 距離
L1‧‧‧第一長度
L2‧‧‧第二長度
W1‧‧‧第一厚度
W2‧‧‧第二厚度

Claims (10)

  1. 一種半導體裝置，其包含：一第一電晶體，其包括：一第一源極區域，其在具有一第一濃度的一第一主體區域中；及一第一閘極；及一第二電晶體，其包括：一第二源極區域，其在具有高於該第一濃度的一第二濃度之一第二主體區域中，該第二源極區域與該第一源極區域及該第一閘極連接。
  2. 如請求項1之半導體裝置，其中該第一電晶體包括具有一第一厚度的一第一絕緣層，且該第二電晶體包括具有一第二厚度的一第二絕緣層，該第二厚度大於或等於該第一厚度。
  3. 如請求項1之半導體裝置，其進一步包含一第一淺溝槽隔離(STI)及一第二STI，及該第一STI與該第二STI之間的一摻雜區域。
  4. 如請求項3之半導體裝置，其中該摻雜區域用於充當該第一電晶體及該第二電晶體之一汲極。
  5. 一種半導體裝置，其包含：一第一電晶體，其包括：一第一源極區域，其在一第一主體區域中；一第一絕緣層，其具有一第一厚度；及一第一閘極，其在該第一絕緣層上；及一第二電晶體，其包括：一第二源極區域，其在一第二主體區域中，該第二源極區域與該第一源極區域及該第一閘極連接； 一第二絕緣層，其具有一第二厚度，該第二厚度大於該第一厚度；及一第二閘極，其在該第二絕緣層上。
  6. 如請求項5之半導體裝置，其中該第一主體區域具有一第一濃度，且該第二主體區域具有高於或等於該第一濃度的一第二濃度。
  7. 如請求項5之半導體裝置，其進一步包含一第一淺溝槽隔離(STI)及一第二STI，及該第一STI與該第二STI之間的一摻雜區域。
  8. 如請求項7之半導體裝置，其中該摻雜區域用於充當該第一電晶體及該第二電晶體之一汲極。
  9. 一種形成一半導體裝置之方法，該方法包含：提供一基板，該基板包括分別與一第一電晶體及一第二電晶體相關聯之一第一裝置區域及一第二裝置區域；在該基板中形成一井；在該第一裝置區域中形成一第一經圖案化絕緣層，該第一經圖案化絕緣層具有一第一厚度；在該第二裝置區域中形成一第二經圖案化絕緣層，該第二經圖案化絕緣層具有大於該第一厚度的一第二厚度；在該第一經圖案化絕緣層上形成一第一閘極；在該井中在該第一裝置區域及該第二裝置區域中分別形成一第一主體區域及一第二主體區域；在該第一主體區域及該第二主體區域中分別形成一第一源極區域及一第二源極區域；及將該第一源極區域、該第一閘極及該第二源極區域連接在一起。
  10. 如請求項9之方法，其進一步包含： 在該基板中形成一第一淺溝槽隔離(STI)及一第二STI；及在該井中在該第一STI與該第二STI之間形成一摻雜區域。
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