TW201719771A - 場效應電晶體及其製造方法 - Google Patents

場效應電晶體及其製造方法 Download PDF

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TW201719771A
TW201719771A TW105137216A TW105137216A TW201719771A TW 201719771 A TW201719771 A TW 201719771A TW 105137216 A TW105137216 A TW 105137216A TW 105137216 A TW105137216 A TW 105137216A TW 201719771 A TW201719771 A TW 201719771A
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Taiwan
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substrate
drain regions
gate structure
strained source
strained
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TW105137216A
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English (en)
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許育銓
游靖
邱達燕
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台灣積體電路製造股份有限公司
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    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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Abstract

本發明實施例提供一種場效應電晶體及其製造方法。場效應電晶體包括基底、至少一個閘極結構、間隔件和應變型源極和汲極區。至少一個閘極結構設置在基底上且位於凹槽和隔離結構之間。間隔件設置在至少一個閘極結構的側壁上。應變型源極和汲極區設置在凹槽中且位於至少一個閘極結構的兩相對邊，並且應變型源極和汲極區的頂部邊緣被間隔件覆蓋和位於間隔件下方。

Description

場效應電晶體及其製造方法
本發明實施例是關於場效應電晶體及其製造方法。
隨著半導體元件線寬的持續縮減，平面互補式金氧半場效電晶體相容(CMOS-compatible)的半導體元件(例如金氧半導場效應電晶體)之閘極寬度和通道長度亦不斷縮小。可利用應變矽技術(strained-silicon technology)改變通道中的電子或電洞的遷移率，進而提高電晶體的運行速度。
根據本發明的一些實施例，提供了一種場效應電晶體，包括：基底、至少一個閘極結構、間隔件以及應變型源極和汲極區。所述基底具有隔離結構和凹槽，所述至少一個閘極結構設置在所述基底上且在所述凹槽和所述隔離結構之間。所述間隔件設置在所述至少一個閘極結構的側壁上。所述應變型源極和汲極區設置在所述凹槽中和位於所述至少一個閘極結構的相對側壁上。所述應變型源極和汲極區的頂部邊緣延伸超過所述間隔件且延伸至所述間隔件下方，並且位於所述至少一個閘極結構的側壁旁邊。
為讓本揭露的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例，且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外，本揭露在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「在…上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地作出解釋。
本發明的實施例描述了金氧半場效應電晶體(MOSFET)的例示性製造過程以及經由該製程所製造的MOSFET。在本發明的特定實施例中，MOSFET可以形成在單晶半導體基底上，例如大塊矽(bulk silicon)基底上。在一些實施例中，MOSFET可以形成在絕緣體上有矽(SOI)基底上或者也可以是絕緣體上有鍺(GOI)基底上。此外，根據實施例，矽基底可以包括其他導電層、摻雜區域或其他半導體元件，例如電晶體、二極體等。實施例僅為例示並非用以限制本案整體內容。
圖1繪示根據本發明的一些實施例的例示性MOSFET的剖面圖。圖2A至圖2E繪示根據本發明的一些實施例的用於形成MOSFET的製造方法的各個階段所製得的MOSFET。在圖1中，MOSFET 100包括形成在基底102上的至少一個閘極結構110、形成在閘極結構110的相對側壁112上的間隔件120、位於間隔件120之間的通道區104和形成在基底102的凹槽106內的應變型源極區和汲極區140。應變型源極區和汲極區140位於閘極結構110的相對兩側處。在一些實施例中，MOSFET 100是P-通道MOSFET。在一些實施例中，MOSFET 100是n-通道MOSFET電晶體。
在圖2A，提供基底102。例如，基底102為單晶半導體基底或SOI基底。在一些實施例中，該基底102是矽基底。基底102包括用於電性隔離的隔離結構105，而MOSFET 100乃預定位於隔離結構105之間。在一些實施例中，隔離結構105是溝渠隔離結構。例如，溝渠隔離結構呈現條狀並且彼此平行配置。溝渠隔離結構中填充有以本領域任意已知方法所形成的介電材料(例如氧化矽或旋塗材料)。
參考圖2A，閘極結構110形成在基底102上和隔離結構105之間。在一些實施例中，閘極結構110是平行配置的條狀結構。在圖2B中，繪示出了兩個閘極結構110，但閘極結構110的數量僅用於說明的目的並非為了限制本發明的結構。在一些實施例中，閘極結構110包括閘極介電條114、位於閘極介電條114上的閘電極條116和位於閘電極條116上的硬罩幕條118。另外，間隔件120位於閘電極條116和硬罩幕條118的相對邊。在一些實施例中，閘極結構110透過以下步驟形成：形成閘極介電層(未圖示)、沉積閘電極材料層(未圖示)、在閘電極材料層上方形成硬罩幕層(未圖示)，然後圖案化硬罩幕層、閘電極材料層和閘極介電層以形成閘極介電條114、閘電極條116和硬罩幕條118。在一些實施例中，該閘極結構110是多晶矽閘結構或替換金屬閘極結構。閘電極條116的材料包括摻雜或未摻雜的多晶矽或含金屬導電材料。含金屬導電材料包括鋁（Al）、銅（Cu）、鎢（W）、鈷（Co）、鈦（Ti）、鉭（Ta）、釕（Ru）、TiN、TiAl、TiAlN、TaN、TaC、NiSi、CoSi或其組合。在一些實施例中，閘極介電條114的材料包括氧化矽、氮氧化矽、氮化矽或其組合。在一些實施例中，閘極介電條114材料包括高介電係數（high-k）介電材料，並且高介電係數介電材料所具有之k值大於7.0並且包括金屬氧化物或金屬矽酸鹽例如鉿（Hf）、Al、鋯（Zr）、鑭（La）、鎂（Mg）、鋇（Ba）、Ti、鉛（Pb）及其組合之矽酸鹽。端視MOSFET 100是P通道MOSFET還是n通道MOSFET，且根據產品要求來選擇閘極介電條114和/或閘電極條116的材料。在一個實施例中，例如，硬罩幕條118是由氮化矽、氧化矽或其組合材料所形成的。在一些實施例中，間隔件120是由氮化矽或其他絕緣材料所形成的。間隔件120可以是單層或多層結構。在一些實施例中，透過沉積介電材料的毯覆層（未圖示）以及執行非等向性蝕刻製程而在閘極結構110的兩側壁上形成間隔件120。
在圖2B中，在預定為源極和汲極區的位置移除部分基底102並且以閘極結構110和間隔件120作為蝕刻罩幕，而在閘極結構110和間隔件120旁邊的基底102內形成凹槽106。透過執行一或多個蝕刻製程來形成凹槽106，包括非等向性蝕刻、等向性蝕刻或其組合。在一些實施例中，該凹槽106的形成包括執行主要蝕刻製程，主要蝕刻製程包括溝渠蝕刻製程和橫向蝕刻製程。利用溝渠蝕刻製程向下蝕刻基底102至深度D（從基底102的頂面102a來計算）並利用橫向蝕刻製程進一步橫向蝕刻凹陷至寬度W（從凹槽106的最寬部分測量而得）而形成凹槽106。在一些實施例中，凹槽106的寬度W實質上等於或小於兩個最相鄰的閘極結構110之間的間距P。例如，深度D大於60奈米且約在70奈米到80奈米的範圍內。在一些實施例中，利用溝渠蝕刻製程來蝕刻凹槽106以形成U形或V形蝕刻輪廓，然後透過橫向蝕刻製程而形成鑽石形（diamond-shaped）或菱形凹槽輪廓。溝渠蝕刻製程或橫向蝕刻製程包括一或多個非等向性蝕刻製程、等向性蝕刻製程、反應離子蝕刻（RIE）製程或其組合。該些製程可選擇性地更包括執行以離子（例如，碳氟化合物、氧、氯、氮、氬、氦等）來轟擊基底102以摻雜或非晶形化部分基底102。
如圖2C所示，在一些實施例中，在主要蝕刻製程之後，凹槽106的形成進一步包括側面蝕刻製程以拓寬凹槽106的上邊緣。控制側面蝕刻製程以橫向地移除間隔件120下方的基底102，從而使得凹槽106的上邊緣107向著閘極結構110下方的通道區域延伸並且在間隔件120下方擴張開來。在一些實施例中，如圖2C所示，斗形（bucket-shaped）凹槽106具有鄰近通道區域104（圖2D）的上側邊108，並且該上側邊108實質上垂直於（正交於）基底102的頂面102a。也就是說，拓寬的凹槽106的頂部尺寸Wt（於上邊緣107之間測量）實質上等於凹槽106的寬度W。在其他實施例中，斗形凹槽106具有鄰近通道區104的上側邊108，並且上側邊108以一角度（非垂直）與基底102的頂面102a成夾角。不過，凹槽106的上側邊108至多與閘極結構110的側壁112對齊。也就是說，拓寬的凹槽106的頂部尺寸Wt（於上邊緣107之間測量）小於寬度W，並且寬度W實質上等於或小於兩個最鄰近的閘極結構110之間的間隔P。在對凹槽106進行側面蝕刻製程之後，圖2B中的凹槽106的鑽石形或菱形凹槽輪廓改變成為如圖2C中所示的凹槽106的斗形或桶形凹槽輪廓。側面蝕刻製程包括一或多個非等向性蝕刻製程、等向性蝕刻製程或其組合。在一些實施例中，可透過使用包括氯化氫（HCl）、氫化鍺（GeH4 ）、其他合適的蝕刻氣體或其組合之蝕刻氣體來進行側面蝕刻製程。可以調整側面蝕刻製程所用的蝕刻氣體流速、壓力和/或蝕刻溫度以控制基底的蝕刻不會延伸超過閘極結構。這種蝕刻製程可以移除部分基底102，包括移除靠近間隔件120角落的錯位(dislocations)。
如圖2D所示，在一些實施例中，在基底102內形成圖2C的凹槽106後，透過在凹槽106內沉積應變材料（strained material）填入凹槽106來形成應變型源極區和汲極區140。在一些實施例中，一些應變型源極區和汲極區140與基底102的頂面102a實質上共平面或者從基底102的頂面102a稍微突出來(凸起)。此外，覆蓋層142形成在應變型源極和汲極區140上作為接觸端。在一些實施例中，例如，覆蓋層142的材料包括摻雜硼的含矽材料。可根據元件的電性性能的要求來調整覆蓋層142的厚度。在一些實施例中，利用矽化製程而可選擇性地形成矽化物層(未圖示)於應變型源極區和汲極區140。
在特定實施例中，應變材料是例如矽鍺（SiGe）的含鍺材料，或例如碳化矽（SiC）的含碳材料。沉積在凹槽106（源極區和汲極區）內的應變材料是應力誘導材料，其引起通道區的單軸壓縮應變。利用例如SiGe的應變材料可以使P-通道MOSFET的電洞遷移率增強。為提高在更高節點（例如節點28及以下）發展的P-通道MOSFET的載子遷移率，可以將SiGe中的Ge含量調整在特定範圍內。類似地，利用例如SiC的應變材料可以使n-通道MOSFET的電子遷移率增強。在一些實施例中，透過磊晶成長形成應變型源極和汲極區域140。在一些實施例中，磊晶成長技術包括低壓CVD（LPCVD）、原子層CVD（ALCVD）、超高真空CVD（UHVCVD）、減壓CVD（PRCVD）、分子束磊晶（MBE）、金屬有機氣相磊晶（MOVPE）或其組合。可選擇地，磊晶成長技術利用循環沉積蝕刻（CDE）磊晶成長製程或選擇性磊晶成長（SEG）製程以形成高晶體品質的應變材料。在一實施例中，該應變型源極和汲極區140的材料包括透過利用原位摻雜的選擇性磊晶成長所形成的硼摻雜的SiGe。在一實施例中，覆蓋層142之形成可視為填充到凹槽106內的應變材料之磊晶成長過程的一部分，但是所形成的覆蓋層142具有與應變材料不同的材料組成。
由於應變型源極和汲極區140位於通道區104的相對側，並且應變材料的晶格常數與基底102的材料的晶格常數不同，因此，通道區140被應變或施加應力，進而增加元件的載子遷移率和提高元件性能。
在圖2D中，多個應變型源極和汲極區140相應地填充在具有斗形輪廓的凹槽106內。應變型源極和汲極區140的頂部邊緣144被間隔件120覆蓋並且位於間隔件120下方和閘極結構110下方的通道區104旁邊。應變型源極和汲極區140的頂部邊緣144至多與閘極結構110的側壁112對齊。也就是說，應變型源極和汲極區140的頂部尺寸Wt實質上等於或小於兩個最鄰近的閘極結構110之間的間隔P。剖面圖2D中的應變型源極和汲極區140具有斗形輪廓，在底部較窄而在中間和頂部較寬。對於應變型源極和汲極區140來說，其寬度W（從其最寬部分測量）實質上等於頂部尺寸Wt並且實質上等於或小於閘極結構110的間隔P。
在一些實施例中，在基底102內形成斗形凹槽106之後，如圖2E所示，以應變材料填充凹槽106來形成應變型源極和汲極區140。圖2D和圖2E的主要區別在於凹槽106的形狀不同並且所產生的應變型源極和汲極區140的形狀是不同的。在一些實施例中，斗形凹槽106的上側邊相對於基底102的頂面102a並非是垂直的而是以一角度相對於基底102的頂面102a呈現夾角。也就是，拓寬的凹槽106的頂部尺寸Wt小於凹槽106的寬度W。相應地，應變型源極和汲極區140的頂部尺寸Wt小於應變型源極和汲極區140的寬度W，並且寬度W實質上等於或小於閘極結構110的間隔P。在一些實施例中，一些應變型源極和汲極區140與基底102的頂面102a實質上共平面或從基底102的頂面102a稍微突出來(凸起)。在一些實施例中，覆蓋層142形成在應變型源極和汲極區140上作為接觸端。同時，透過矽化製程可選擇性地形成矽化物層（未圖示）於應變型源極和汲極區140。
在上述實施例中，凹槽106的蝕刻輪廓被很好的控制，使得凹槽106的上部邊緣向通道區域104延伸，並延伸到間隔件120的下面。凹槽106的上部邊緣107至多與閘極結構110的側壁對齊，但不與閘極結構110或通道區104接觸。由於凹槽的蝕刻輪廓能被良好地控制，可精確調整且優化凹槽的形狀來加強應力。精確良好地控制凹槽的輪廓以確保後續填充的應變材料的形狀增強通道區中所欲的應力。對於具有較窄間隔的元件而言，可以增加應變材料部分的寬度而不影響其鄰近輪廓（proximity profile）是可能的。因此，根據本發明上述實施例所形成的應變型源極和汲極區可允許最大通道應變（channel strain）和增強元件的性能。此外，根據本發明的上述實施例的應變型源極和汲極區的鄰近輪廓保持不變。
因此，在凹槽106內形成的應變型源極和汲極區140具有斗形側壁輪廓，從而使得寬度W（從其最寬部分測量）實質上等於或稍大於應變型源極和汲極區140的頂部尺寸Wt並且實質上等於或小於閘極結構110的間隔P。應變型源極和汲極區140的頂部邊緣144位於間隔件120下方並且位於閘極結構110下方的通道區104旁邊。應變型源極和汲極區140的頂部邊緣144至多與閘極結構110的側壁112對齊。由於應變型源極和汲極區140的頂部邊緣144延伸超過間隔件並且延伸至間隔件下方，更多的應力可以施加到通道區上以調整MOSFET的載子遷移率和提高元件的性能。
圖3是根據本發明的一些實施例用於形成MOSFET的製造方法的製程步驟的例示性流程圖。
雖然該方法的步驟被顯示和描述為一系列的動作和事件，但是應當理解，這些動作和事件的所示出的順序不應解釋為限制意義。此外，並非所有顯示的製程或步驟皆為實施本發明的一個或多個實施例的必須步驟。
在步驟300中，提供具有一個或多個隔離結構的基底和具有側壁間隔件的至少一個閘極結構。基底是矽基底或絕緣體上矽（SOI）基底。在步驟302中，對基底進行主要蝕刻製程以產生具有菱形蝕刻輪廓的一或多個凹槽。在一些實施例中，主要蝕刻製程包括一或多個非等向性蝕刻製程、等向性蝕刻製程、RIE製程或其組合。在步驟304中，對基底進行側面蝕刻製程以產生具有斗形蝕刻輪廓的一個或多個凹槽。側面蝕刻製程包括一或多個非等向性蝕刻製程、等向性蝕刻製程或其組合。在步驟306中，透過填充應變材料來填充凹槽而形成應變型源極和汲極區。應變材料包括含鍺材料或含碳材料。應變型源極和汲極區（從其最寬部分測量）的寬度W實質上等於應變型源極和汲極區的頂部尺寸Wt並且實質上等於或小於閘極結構的間隔P。
在上述實施例中，透過主要蝕刻製程和側面蝕刻製程可以很好地控制凹槽的蝕刻輪廓。對於具有緊密間距或間距的閘極結構的元件而言，包括凹槽的的蝕刻側壁輪廓（菱形輪廓或斗形輪廓）適合增強應力而不影響鄰近輪廓。由於凹槽輪廓能夠被精準良好地調整，使得應變型源極和汲極區的輪廓可以對通道區施加更多的應力並且提高元件的性能。
在本發明的一些實施例中，描述了一種場效應電晶體。場效應電晶體包括具有隔離結構和凹槽的基底、至少一個閘極結構、間隔件和應變型源極和汲極區。至少一個閘極結構設置在基底上且位於凹槽和隔離結構之間。間隔件設置在至少一個閘極結構的側壁上。應變型源極和汲極區設置在凹槽中並位於至少一個閘極結構的相對側邊。應變型源極和汲極區的頂部邊緣延伸超過間隔件且延伸於間隔件下方而且位於閘極結構側壁的旁邊。
在本發明的一些實施例中，上述電晶體還包括位於所述應變型源極和汲極區上的覆蓋層。在本發明的一些實施例中，所述應變型源極和汲極區的材料包括硼摻雜的矽鍺，而所述覆蓋層的材料包括摻雜有硼的含矽材料。在本發明的一些實施例中，至少一個所述應變型源極和汲極區具有斗形輪廓，並且至少一個所述應變型源極和汲極區的頂部尺寸小於至少一個所述應變型源極和汲極區的寬度。在本發明的一些實施例中，至少一個所述應變型源極和汲極區具有斗形輪廓，並且至少一個所述應變型源極和汲極區的頂部尺寸等於至少一個所述應變型源極和汲極區的寬度。在本發明的一些實施例中，所述至少一個閘極結構是多晶矽閘極結構或替換金屬閘極結構。
在本發明的一些實施例中，描述了一種場效應電晶體。場效應電晶體包括：具有隔離結構的基底、閘極結構、間隔件、應變型源極和汲極區和覆蓋層。閘極結構設置在基底上以及隔離結構之間，間隔件設置在閘極結構的側壁上。應變型源極和汲極區設置在基底的凹槽內且位於閘極結構的相對側邊。間隔件覆蓋位於間隔件下方的應變型源極和汲極區的頂部邊緣。覆蓋層位於應變型源極和汲極區上。
在本發明的一些實施例中，至少一個所述應變型源極和汲極區具有斗形輪廓，並且至少一個所述應變型源極和汲極區的頂部尺寸小於至少一個所述應變型源極和汲極區的寬度，並且至少一個所述應變型源極和汲極區的寬度等於或小於所述閘極結構的間隔。在本發明的一些實施例中，至少一個所述應變型源極和汲極區具有斗形輪廓，並且至少一個所述應變型源極和汲極區的頂部尺寸等於至少一個所述應變型源極和汲極區的寬度，並且至少一個所述應變型源極和汲極區的寬度等於或小於所述閘極結構的間隔。在本發明的一些實施例中，所述應變型源極和汲極區的材料包括硼摻雜的矽鍺，而所述覆蓋層的材料包括摻雜有硼的矽。在本發明的一些實施例中，所述閘極結構包括：設置在所述基底上的閘極介電條；設置在所述閘極介電條上的閘電極條；以及設置在所述閘電極條上的硬罩幕條。
在本發明的一些實施例中，描述了一種用於形成場效應電晶體的方法。提供具有隔離結構、閘極結構以及位於閘極結構側壁上的間隔件之基底。對基底進行第一蝕刻製程，以產生具有鑽石形蝕刻輪廓的一或多個凹槽。對基底進行第二蝕刻製程，以移除間隔件下方的基底，從而產生具有斗形蝕刻輪廓的一或多個凹槽。然後形成填充在具有斗形蝕刻輪廓的一或多個凹槽中的應變型源極和汲極區。
在本發明的一些實施例中，在上述方法中，對所述基底進行第二蝕刻製程包括對具有鑽石形蝕刻輪廓的一或多個凹槽進行所述第二蝕刻製程以橫向地移除所述間隔件下方的所述基底，從而產生具有斗形蝕刻輪廓的一或多個凹槽，並且具有斗形蝕刻輪廓的一或多個凹槽的上部邊緣在所述間隔件下方展開。在本發明的一些實施例中，具有斗形蝕刻輪廓的一或多個凹槽的頂部尺寸小於具有斗形蝕刻輪廓的一或多個凹槽的寬度，並且具有斗形蝕刻輪廓的一或多個凹槽的寬度等於或小於所述閘極結構之間的間隔。在本發明的一些實施例中，具有斗形蝕刻輪廓的一或多個凹槽的頂部尺寸等於具有斗形蝕刻輪廓的一或多個凹槽的寬度，並且具有斗形蝕刻輪廓的一或多個凹槽的寬度等於或小於所述閘極結構之間的間隔。在本發明的一些實施例中，填充在具有斗形蝕刻輪廓的一或多個凹槽中的所述應變型源極和汲極區的頂部邊緣被所述間隔件覆蓋。在本發明的一些實施例中，在上述方法中，形成所述應變型源極和汲極區包括：透過利用原位摻雜的選擇性磊晶成長，將摻雜硼的矽鍺（SiGe）填充到具有斗形蝕刻輪廓的一個或多個凹槽內。在本發明的一些實施例中，所述第一蝕刻製程包括溝渠蝕刻製程和橫向蝕刻製程。在本發明的一些實施例中，具有鑽石形蝕刻輪廓的一或多個凹槽的寬度等於或小於所述閘極結構之間的間隔。在本發明的一些實施例中，上述方法還包括在所述應變型源極和汲極區上形成覆蓋層。
以上概述了多個實施例的特徵，使本領域具有通常知識者可更佳了解本揭露的態樣。本領域具有通常知識者應理解，其可輕易地使用本揭露作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本揭露的精神與範疇，且本領域具有通常知識者在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
100‧‧‧MOSFET
102‧‧‧基底
102a‧‧‧頂面
104‧‧‧通道區
105‧‧‧隔離結構
106‧‧‧凹槽
107‧‧‧上邊緣
108‧‧‧上側邊
110‧‧‧閘極結構
112‧‧‧側壁
114‧‧‧閘極介電條
116‧‧‧閘電極條
118‧‧‧硬罩幕條
120‧‧‧間隔件
140‧‧‧應變型源極和汲極區
142‧‧‧覆蓋層
144‧‧‧頂部邊緣
D‧‧‧深度
W‧‧‧寬度
Wt‧‧‧頂部尺寸
圖1繪示根據本發明的一些實施例的例示性MOSFET的剖面圖。 圖2A至圖2E繪示根據本發明的一些實施例的用於形成MOSFET的製造方法的各個階段所製得MOSFET的剖面圖。 圖3是根據本發明的一些實施例用於形成MOSFET製造方法的製程步驟的例示性流程圖。
100‧‧‧MOSFET
102‧‧‧基底
102a‧‧‧頂面
104‧‧‧通道區
105‧‧‧隔離結構
110‧‧‧閘極結構
112‧‧‧側壁
114‧‧‧閘極介電條
116‧‧‧閘電極條
118‧‧‧硬罩幕條
120‧‧‧間隔件
140‧‧‧應變型源極區和汲極區
142‧‧‧覆蓋層

Claims (1)

  1. 一種場效應電晶體，包括： 基底，所述基底具有隔離結構和凹槽； 至少一個閘極結構，設置在所述基底上且位於所述凹槽和所述隔離結構之間； 間隔件，設置在所述至少一個閘極結構的側壁上；以及 應變型源極和汲極區，設置在所述凹槽中且位於所述至少一個閘極結構的相對邊，其中，所述應變型源極和汲極區的頂部邊緣延伸超過所述間隔件且位於所述間隔件下方，並且位於所述至少一個閘極結構的所述側壁旁邊。
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