TW201604925A - 貼合式soi晶圓的製造方法 - Google Patents

貼合式soi晶圓的製造方法 Download PDF

Info

Publication number
TW201604925A
TW201604925A TW104107391A TW104107391A TW201604925A TW 201604925 A TW201604925 A TW 201604925A TW 104107391 A TW104107391 A TW 104107391A TW 104107391 A TW104107391 A TW 104107391A TW 201604925 A TW201604925 A TW 201604925A
Authority
TW
Taiwan
Prior art keywords
wafer
layer
bonded
temperature
polycrystalline germanium
Prior art date
Application number
TW104107391A
Other languages
English (en)
Other versions
TWI590298B (zh
Inventor
Hiroshi Wakabayashi
Kenji Meguro
Masatake Nakano
Shinichiro Yagi
Tomosuke Yoshida
Original Assignee
Shinetsu Handotai Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinetsu Handotai Kk filed Critical Shinetsu Handotai Kk
Publication of TW201604925A publication Critical patent/TW201604925A/zh
Application granted granted Critical
Publication of TWI590298B publication Critical patent/TWI590298B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02307Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a liquid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/02428Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02488Insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02551Group 12/16 materials
    • H01L21/02554Oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02595Microstructure polycrystalline
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02598Microstructure monocrystalline
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185Joining of semiconductor bodies for junction formation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02043Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052Wet cleaning only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

本發明係關於一種貼合式SOI晶圓的製造方法,係關於將皆由數個單晶矽所構成的貼合晶圓及基底晶圓透過絕緣膜貼合的貼合式SOI晶圓的製造方法,其中包含:將基底晶圓的貼合面側堆積多晶矽的步驟,研磨多晶矽層的表面的步驟,於貼合晶圓的貼合面形成絕緣膜的步驟,透過絕緣膜將基底晶圓的多晶矽層的研磨面與貼合晶圓貼合的步驟,以及將經貼合的貼合晶圓薄膜化而形成SOI層的步驟;使用電阻率100Ω‧cm以上的單晶矽晶圓,堆積多晶矽層的步驟進一步包含於貼合晶圓的堆積多晶矽層的表面預先形成氧化膜的階段,多晶矽層的堆積分為二個階段進行,包含以1010℃以下的第一溫度進行的第一成長,及以較第一溫度更高溫的第二溫度進行較第一成長更厚的堆積的第二成長。藉此,即使在用以作為載子捕陷層而運作的多晶層的厚度已堆積至充分的厚度時,亦能抑制基底晶圓的翹曲的擴大,同時防止多晶矽的單晶化。

Description

貼合式SOI晶圓的製造方法
本發明係關於一種貼合式SOI晶圓的製造方法。
作為對應高頻率(Radio Frequency, RF)裝置的SOI晶圓,一直是以將基底晶圓予以高電阻率以解決。但是,為對應進一步的高速化,而逐漸有對應更高的頻率的必要,僅使用已知的高電阻晶圓已經逐漸無法解決。
在此,作為對應策提出有於SOI晶圓的埋入氧化膜層(BOX層)正下方,加入具有使產生的載子消滅的層(載體捕陷層),逐漸有必要將用以使高電阻晶圓中所產生的載子再結合的多晶矽層形成於基底晶圓上。
專利文獻1中,記載有於BOX層及基底晶圓的境界面形成作為載子捕陷層的多晶矽層或非晶矽層。               另一方面,專利文獻2中,亦記載有於BOX層及基底晶圓的境界面形成作為載子捕陷層的多晶矽層,進一步限制多晶矽層形成後的熱處理溫度以防止多晶矽層的再結晶化。               又專利文獻3中,雖未記載有形成作為載子捕陷層的多晶矽層或非晶矽層,但記載有透過將與貼合晶圓貼合的一側的基底晶圓表面的表面粗糙度放大,能夠得到與載子捕陷層同樣的效果。 〔先前技術文獻〕
專利文獻1:日本特表2007-507093號公報               專利文獻2:日本特表2013-513234號公報               專利文獻3:日本特開2010-278160號公報
[發明所欲解決之問題]
如同前述,為了製造對應更高頻率的裝置,逐漸有必要於SOI晶圓的BOX層下形成載子捕陷層。       進一步而言,用以使其作為載子捕陷層而運作的多晶矽層的厚度,由於為相對較厚,例如0.5μm以上,因此以盡可能以高速而僅於單面成長為佳。但是,經本案發明人研討的結果,得知若僅於單面堆積較厚的多晶矽層,則隨著厚度增加晶圓的翹曲亦會變大,而成為貼合不良的原因。       另一方面,得知雖然為了盡可能以高速堆積多晶矽層而有提高成長溫度的必要,但若成長溫度提高,將會有基底晶圓表面的自然氧化膜的一部分消失,該部分將不成長多晶矽而單晶化的問題。
鑑於前述問題,本發明的目的在於提出一種貼合式SOI晶圓的製造方法,即使在用以作為載子捕陷層而運作的多晶層的厚度已堆積至充分的厚度時,亦能抑制基底晶圓的翹曲的擴大,同時防止多晶矽的單晶化。 [解決問題之技術手段]
為達成前述目的,本發明提供一種貼合式SOI晶圓的製造方法,係關於將皆由數個單晶矽所構成的貼合晶圓及基底晶圓透過絕緣膜貼合的貼合式SOI晶圓的製造方法,其中包含: 將該基底晶圓的貼合面側堆積多晶矽的步驟, 研磨該多晶矽層的表面的步驟, 於該貼合晶圓的貼合面形成該絕緣膜的步驟, 透過該絕緣膜將該基底晶圓的該多晶矽層的研磨面與該貼合晶圓貼合的步驟,以及 將經貼合的該貼合晶圓薄膜化而形成SOI層的步驟; 使用電阻率100Ω‧cm以上的單晶矽晶圓,該堆積多晶矽層的步驟進一步包含於貼合晶圓的堆積該多晶矽層的表面預先形成氧化膜的階段,該多晶矽層的堆積分為二個階段進行,包含以1010℃以下的第一溫度進行的第一成長,及以較第一溫度更高溫的第二溫度進行較第一成長更厚的堆積的第二成長。
如此,預先於基底晶圓的單晶矽表面形成氧化膜,透過使多晶矽層的堆積溫度為1010℃以下,能夠防止基底晶圓表面的氧化膜的一部份消失,藉此能夠防止多晶層的單晶化,而能夠維持其作為載子捕陷層的效果。               進一步以1010℃以下的低溫堆積多晶層後,以較其更高溫,且堆積更厚的多晶矽層,能夠高速而有效率的堆積充分厚度的多晶矽層,並能夠抑制晶圓的翹曲。
此時,該氧化膜以透過濕洗形成為佳。               由於使氧化膜存在基底晶圓及多晶矽層之間可能影響RF裝置的特性,因此所形成的氧化膜厚度以較薄為佳,例如以10nm以下的厚度為佳。作為形成如此厚度的氧化膜的方法,能夠舉出濕洗為最簡易的方法。
此時,以該第一溫度為900℃以上,該第二溫度為1100℃以上為佳。               若使第一溫度為900℃以上,則能夠防止堆積速度太慢而使生產性低落。               又若使第二溫度為1100℃以上,則在得到充分快速的堆積速度而生產性上升的同時,亦能充分抑制多晶矽層堆積後的晶圓翹曲。               進一步而言,即使SOI晶圓的製造步驟的熱處理步驟或裝置製造步驟的熱處理為相對高溫(例如,1000至1200℃度),由於係以與其同等的溫度進行多晶矽層的堆積,因此能夠充分抑制多晶矽層的晶界成長,維持作為載子捕陷層的效果。
此時,以該多晶矽層貼合時的厚度在2μm以上為佳。               藉由使多晶矽層的貼合時厚度在2μm以上雖然會由於晶圓的翹曲的影響而提高貼合不良的機率,但即使多晶矽層的貼合時的厚度在2μm以上,若是多晶矽層的堆積中以較第一成長時更高的高溫進行第二成長,則能夠降低晶圓的翹曲,因此能夠提高作為載子捕陷層的效果,同時追求貼合不良的減低。 [對照先前技術之功效]
如同前述,依照本發明,透過預先於基底晶圓的單晶矽的表面形成氧化膜,並使多晶矽層的堆積溫度為1010℃以下,能夠防止基底晶圓表面的氧化膜的一部分消失,防止多晶矽層的單晶化的發生,並維持作為載子捕陷的效果。               進一步而言,以1010℃以下的低溫堆積多晶矽層後,以較其更高溫,且堆積更厚的多晶矽層,能夠高速而有效率的堆積充分厚度的多晶矽層,並能夠抑制晶圓的翹曲。
以下關於本發明,雖作為實施例之一參照圖式進行說明,但本發明並非限定於此。       如同前述,雖然為了製作對應更高頻率的裝置而逐漸有必要於SOI晶圓的BOX層下形成載子捕陷層,但由於用以作為載子捕陷層運作的多晶矽層要求有較厚的膜厚度,以盡可能高速僅於單面成長較為適合。但是,若僅於單面堆積較厚的多晶矽層,則會有隨著厚度增加晶圓的翹曲亦會變大,而成為貼合不良的原因的問題。進一步而言,為了盡可能以高速堆積多晶矽層而有提高成長溫度的必要,但若成長溫度提高,將會有基底晶圓表面的自然氧化膜的一部分消失,該部分將不成長多晶矽而單晶化的問題。
在此,本案發明人研究一種貼合式SOI晶圓的製造方法,該貼合式SOI晶圓的製造方法即使在用以作為載子捕陷層而運作的多晶層的厚度已堆積至充分的厚度時,亦能抑制基底晶圓的翹曲的擴大,同時防止多晶矽的單晶化。               結果,本案發明人發現預先於基底晶圓的單晶矽表面形成氧化膜,之後透過使多晶矽層的堆積溫度為1010℃以下,能夠防止基底晶圓表面的氧化膜的一部份消失,藉此能夠防止多晶層的單晶化,而能夠維持其作為載子捕陷層的效果,進一步,以1010℃以下的低溫堆積多晶層後,以較其更高溫,且堆積更厚的多晶矽層,能夠高速而有效率的堆積充分厚度的多晶矽層,並能夠抑制晶圓的翹曲,而完成本發明。
以下,參照第1至2圖,說明本發明的貼合式SOI晶圓的製造方法的實施例之一。               首先,準備由單晶矽所構成的貼合晶圓10(參照第1圖的步驟S11及第2圖步驟(a))。
接著,透過例如熱氧化或化學氣相沉積等,於貼合晶圓10,使成為埋入氧化膜層(BOX層)16的絕緣膜(例如氧化膜)13成長(參照第1圖的步驟S12及第2圖的步驟(b))。
接著,於該絕緣膜13的上方以離子注入機注入氫離子及墮性氣體離子中的至少一種,於貼合晶圓10內形成離子注入層17(參照第1圖的步驟S13及第2圖的步驟(c))。此時,選擇離子注入加速電壓以得到目標的SOI層15的厚度。。
接著進行貼合前洗淨(參照第1圖的步驟S14),以除去貼合晶圓10的貼合面的微粒子。
另一方面,除了前述之外,準備由單晶矽所構成的基底晶圓11(參照第1圖的步驟S21及第2圖的步驟(d))。
接著,於基底晶圓11上形成氧化膜(基底氧化膜)20(參照第1圖的步驟S22及第2圖的步驟(e))。氧化膜20的厚度雖無特別限定,但使氧化膜存在基底晶圓及多晶矽層之間可能影響RF裝置的特性,因此所形成的氧化膜厚度以較薄為佳,例如以0.3nm以上,10nm以下的厚度為佳。       作為形成如此厚度的氧化膜的方法,能夠舉出濕洗為最簡易的方法。具體而言,能夠透過使用SC1(NH4 OH與H2 O2 的混合水溶液)、SC2(HCl與H2 O2 的混合水溶液)、SPM(H2 SO4 與H2 O2 的混合水溶液)及臭氧水等的洗淨,或是進行將此些組合的洗淨,以形成厚度在0.5至3nm的均勻的氧化膜。
接著,使多晶矽層12堆積於氧化膜(基底氧化膜)20上(參照第1圖的步驟S23及第2圖的步驟(f))。此處,多晶矽層12的堆積,分為以1010℃以下的第一溫度所進行的第一成長,及以較第一溫度高的第二溫度以進行較第一成長厚的堆積的第二成長(於第一成長後進行)的二個階段。               基底晶圓的單晶矽的表面與堆積的多晶矽層之間,預先形成氧化膜,透過使之後所進行的第一成長時的堆積溫度為1010℃以下,能夠防止基底晶圓表面的氧化膜的一部份消失。進一步,以1010℃以下的低溫堆積預定的膜厚度(0.5μm左右)後,於第二成長中以較第一成長更高溫,且堆積更厚的多晶矽層,能夠高速而有效率的堆積充分厚度的多晶矽層,同時能夠抑制晶圓的翹曲。               另外,此二個階段的成長可以連續進行,亦可暫時自成長爐取出,之後進行第二成長。
接著,將於基底晶圓11所堆積的多晶矽層12的表面透過研磨而平坦化(參照第1圖的步驟S24及第2圖的步驟(g))。由於以高溫堆積的多晶矽層12的表面粗糙度較大,會難以直接貼合,因此有必要將多晶矽層12的表面透過研磨而平坦化。
接著,進行貼合前洗淨(參照第1圖的步驟S25)以去除經研磨後的多晶矽層12的表面的微粒子。               另外,第1圖的步驟S11至S14,與第1圖的步驟S1至S25可為並行進展。
接著,將形成有多晶矽層12的基底晶圓11與形成有絕緣膜13的貼合晶圓10密著而貼合,以使基底晶圓11形成有的多晶矽層12的面與貼合晶圓10的注入面相接(參照第1圖的步驟S31及第2圖的步驟(h))。
接著,對貼合的晶圓施以使離子注入層17產生微小氣泡層的熱處理(剝離熱處理),於所發生的微小氣泡層剝離,而製作基底晶圓11上形成有埋入氧化膜層16及SOI層15的貼合晶圓式14(參照第1圖的步驟S32及第2圖的步驟(i))。另外,於此時派生有具有剝離面19的剝離晶圓18。
接著對貼合式晶圓14施以結合熱處理,以使貼合介面的結合強度增加(參照第1圖的步驟S33)。               如同前述而能夠製造貼合式SOI晶圓。
前述所說明的本發明的貼合式SOI晶圓的製造方法中,多晶矽層12的堆積的第一成長時的第一溫度以900℃以上為佳。若使第一溫度為900℃以上,則能夠防止堆積速度過於緩慢而使生產性低落。               又多晶矽層12的堆積的第二成長時的第二溫度以1100℃以上為佳。若使第二溫度為1100℃以上,則在得到充分快速的堆積速度而使生產性提升的同時,亦能充分抑制多晶矽層堆積後的晶圓的翹曲。進一步而言,SOI晶圓製造步驟的熱處理步驟或裝置製造步驟的熱處理即使為相對高溫(例如1000至1200℃左右),由於以與其同等的溫度進行多晶矽的堆積,多晶矽層的晶界成長受到充分抑制,能夠維持其作為載子捕陷層的效果。               另外第二溫度的上限雖無特別限定,但沒有必要高於SOI晶圓製造步驟或裝置製造步驟的最高溫度(過高則容易發生滑移錯位或金屬汙染),因此以最高溫度以下,例如1200℃以下為佳。
又前述所說明的本發明的貼合式晶圓的製造方法中,多晶矽層12的貼合時的厚度以為2μm以上為佳。               藉由使多晶矽層的貼合時厚度在2μm以上雖然會由於晶圓的翹曲的影響而提高貼合不良的機率,但即使多晶矽層的貼合時的厚度在2μm以上,若是多晶矽層的堆積中以較第一成長時更高的高溫進行第二成長,則能夠降低晶圓的翹曲,因此能夠提高作為載子捕陷層的效果,同時追求貼合不良的減低。               另外,多晶矽層的貼合時厚度以10μm以下為佳。               又基底晶圓11的電阻率只要為100Ω‧cm以上便適合用於高頻率裝置製造,為1000Ω‧cm以上則更佳,3000Ω‧cm以上則特佳。電阻率的上限雖無特別限定,但可為例如50000Ω‧cm。
以下雖顯示實施例及比較例以更具體的說明本發明,但本發明並不限定於此。
(實施例1)               使用於第1至2圖所說明的製造方法製作貼合式SOI晶圓。但是,作為基底晶圓,使用直徑200mm、晶體方位<100>、電阻率700Ω‧cm、p型的單晶矽,形成基底氧化膜、堆積多晶矽(使用三氯氫矽做為原料氣體)、BOX氧化、注入氫離子、剝離熱處理、結合熱處理係以以下的條件進行。 又測量多晶矽層研磨後的晶圓的翹曲,調查結合熱處理後的多晶矽層的單晶化狀況(以剖面SEM觀察而確認)。顯示其結果於表1。
(實施例2)               與實施例1同樣製作貼合式SOI晶圓。但是多晶矽的堆積,以950℃、常壓、膜厚度0.3μm + 1130℃、常壓、膜厚度2.7μm(研磨後的總厚度2.2μm)的條件以進行。               與實施例1同樣測量多晶矽層研磨後的晶圓的翹曲,調查結合熱處理後的多晶矽層的單晶化狀況。顯示其結果於表1。
(實施例3)               與實施例1同樣製作貼合式SOI晶圓。但是多晶矽的堆積,以1010℃、常壓、膜厚度0.3μm + 1130℃、常壓、膜厚度2.7μm(研磨後的總厚度2.2μm)的條件以進行。               與實施例1同樣測量多晶矽層研磨後的晶圓的翹曲,調查結合熱處理後的多晶矽層的單晶化狀況。顯示其結果於表1。
(實施例4)               與實施例1同樣製作貼合式SOI晶圓。但是基底氧化膜的形成,以800℃、dryO2 氧化、氧化膜厚度30nm的條件以進行,多晶矽層的堆積,以980℃、常壓、膜厚度0.3μm + 1100℃、常壓、膜厚度2.7μm(研磨後的總厚度2.2μm)的條件以進行。               與實施例1同樣測量多晶矽層研磨後的晶圓的翹曲,調查結合熱處理後的多晶矽層的單晶化狀況。顯示其結果於表1。
(比較例1)               與實施例1同樣製作貼合式SOI晶圓。但是多晶矽的堆積不分為第一成長及第二成長的二個階段,以1000℃,常壓、膜厚度3μm(研磨後的總厚度2.2μm)的一個階段的條件以進行。               與實施例1同樣測量多晶矽層研磨後的晶圓的翹曲,調查結合熱處理後的多晶矽層的單晶化狀況。顯示其結果於表1。
(比較例2)               與實施例1同樣製作貼合式SOI晶圓。但是多晶矽的堆積不分為第一成長及第二成長的二個階段,以1020℃,常壓、膜厚度3μm的一個階段的條件以進行。               另外於比較例2中,以多晶矽層堆積後的SEM觀察確認到單晶的堆積,由於沒有堆積為多晶矽層,因此不實施之後的步驟。
【表1】
自表一可得知,將多晶矽層的堆積,分為以1010℃以下進行的第一成長及以較第一成長時的溫度高的溫度而進行較第一成長厚的堆積的第二成長以進行的實施例1至4,能夠抑制晶圓的翹曲,同時防止多晶矽的單晶化。特別是將第二成長以1100℃以上進行的實施例1、3至4,與將第二成長以1100℃以下進行的實施例2相比,能夠更加縮小晶圓的翹曲。               另一方面,不將多晶矽層的堆積分為第一成長及第二成長而於1000℃以進行的比較例1,雖然能夠防止多晶矽的單晶化,但與實施例1至4相比晶圓的翹曲變得較大。               進一步來說,不將多晶矽層的堆積分為第一成長及第二成長而於1020℃以進行的比較例2,在多晶矽層堆積結束時發生了多晶矽的單晶化。
另外,本發明並不為前述實施例所限制。前述實施例為例示,具有與本發明的申請專利範圍所記載的技術思想為實質相同的構成,且達成同樣作用效果者,皆包含於本發明的技術範圍。
10‧‧‧貼合晶圓
11‧‧‧基底晶圓
12‧‧‧多晶矽層
13‧‧‧絕緣膜
14‧‧‧貼合式晶圓
15‧‧‧SOI層
16‧‧‧氧化膜層
17‧‧‧離子注入層
18‧‧‧剝離晶圓
19‧‧‧剝離面
20‧‧‧氧化膜
第1圖係顯示本發明的貼合式SOI晶圓的製造方法的實施例之一的製造流程圖。 第2圖係顯示本發明的貼合式SOI晶圓的製造方法的實施例之一的步驟剖面示意圖。

Claims (5)

  1. 一種貼合式SOI晶圓的製造方法,係關於將皆由數個單晶矽所構成的貼合晶圓及基底晶圓透過絕緣膜貼合的貼合式SOI晶圓的製造方法,其中包含: 將該基底晶圓的貼合面側堆積多晶矽的步驟, 研磨該多晶矽層的表面的步驟, 於該貼合晶圓的貼合面形成該絕緣膜的步驟, 透過該絕緣膜將該基底晶圓的該多晶矽層的研磨面與該貼合晶圓貼合的步驟,以及 將經貼合的該貼合晶圓薄膜化而形成SOI層的步驟; 使用電阻率100Ω‧cm以上的單晶矽晶圓,該堆積多晶矽層的步驟進一步包含於貼合晶圓的堆積該多晶矽層的表面預先形成氧化膜的階段,該多晶矽層的堆積分為二個階段進行,包含以1010℃以下的第一溫度進行的第一成長,及以較第一溫度更高溫的第二溫度進行較第一成長更厚的堆積的第二成長。
  2. 如請求項1所述的貼合式SOI晶圓的製造方法,該氧化膜係由濕洗所形成。
  3. 如請求項1所述的貼合式SOI晶圓的製造方法,該第一溫度為900℃以上,該第二溫度為1100℃以上。
  4. 如請求項2所述的貼合式SOI晶圓的製造方法,該第一溫度為900℃以上,該第二溫度為1100℃以上。
  5. 如請求項1至4中任一項所述的貼合式SOI晶圓的製造方法,該多晶矽層貼合時的厚度在2μm以上。
TW104107391A 2014-04-24 2015-03-09 Method of manufacturing a bonded SOI wafer TWI590298B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014090012A JP6100200B2 (ja) 2014-04-24 2014-04-24 貼り合わせsoiウェーハの製造方法

Publications (2)

Publication Number Publication Date
TW201604925A true TW201604925A (zh) 2016-02-01
TWI590298B TWI590298B (zh) 2017-07-01

Family

ID=54332022

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104107391A TWI590298B (zh) 2014-04-24 2015-03-09 Method of manufacturing a bonded SOI wafer

Country Status (8)

Country Link
US (1) US10460983B2 (zh)
EP (1) EP3136421B1 (zh)
JP (1) JP6100200B2 (zh)
KR (1) KR102312812B1 (zh)
CN (1) CN106233425B (zh)
SG (1) SG11201608562RA (zh)
TW (1) TWI590298B (zh)
WO (1) WO2015162839A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109643670A (zh) * 2016-09-07 2019-04-16 信越半导体株式会社 贴合用基板的表面缺陷的评价方法
TWI717504B (zh) * 2016-06-06 2021-02-01 日商信越半導體股份有限公司 貼合式soi晶圓的製造方法

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6498635B2 (ja) * 2016-06-23 2019-04-10 信越半導体株式会社 貼り合わせsoiウェーハの製造方法
EP3549162B1 (en) * 2016-12-05 2022-02-02 GlobalWafers Co., Ltd. High resistivity silicon-on-insulator structure and method of manufacture thereof
FR3064398B1 (fr) * 2017-03-21 2019-06-07 Soitec Structure de type semi-conducteur sur isolant, notamment pour un capteur d'image de type face avant, et procede de fabrication d'une telle structure
JP2018164006A (ja) * 2017-03-27 2018-10-18 信越半導体株式会社 貼り合わせウェーハの製造方法及び貼り合わせウェーハ
JP6919579B2 (ja) * 2018-01-17 2021-08-18 株式会社Sumco 貼り合わせウェーハの製造方法、貼り合わせウェーハ
JP6827442B2 (ja) * 2018-06-14 2021-02-10 信越半導体株式会社 貼り合わせsoiウェーハの製造方法及び貼り合わせsoiウェーハ
US20220130866A1 (en) * 2019-03-04 2022-04-28 Board Of Regents, The University Of Texas System Silicon-On-Oxide-On-Silicon
JP2021190660A (ja) 2020-06-04 2021-12-13 株式会社Sumco 貼り合わせウェーハ用の支持基板
US20220115226A1 (en) * 2020-10-08 2022-04-14 Okmetic Oy Manufacture method of a high-resistivity silicon handle wafer for a hybrid substrate structure
CN112670170B (zh) * 2020-12-30 2024-02-02 长春长光圆辰微电子技术有限公司 一种提高硅片键合力的方法
CN113223952B (zh) * 2021-04-28 2022-10-28 华虹半导体(无锡)有限公司 包含sgt结构的器件的制作方法
FR3129028B1 (fr) 2021-11-09 2023-11-10 Soitec Silicon On Insulator Procede de preparation d’un substrat support muni d’une couche de piegeage de charges
FR3129029B1 (fr) 2021-11-09 2023-09-29 Soitec Silicon On Insulator Procede de preparation d’un substrat support muni d’une couche de piegeage de charges
WO2024018149A1 (fr) * 2022-07-19 2024-01-25 Soitec Procédé de fabrication d'un substrat support pour application radiofréquences
FR3138239B1 (fr) * 2022-07-19 2024-06-21 Soitec Silicon On Insulator Procédé de fabrication d’un substrat support pour application radiofréquences

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4631804A (en) * 1984-12-10 1986-12-30 At&T Bell Laboratories Technique for reducing substrate warpage springback using a polysilicon subsurface strained layer
US4742020A (en) 1985-02-01 1988-05-03 American Telephone And Telegraph Company, At&T Bell Laboratories Multilayering process for stress accommodation in deposited polysilicon
US4897360A (en) 1987-12-09 1990-01-30 Wisconsin Alumni Research Foundation Polysilicon thin film process
JPH0719839B2 (ja) 1989-10-18 1995-03-06 株式会社東芝 半導体基板の製造方法
JP2766417B2 (ja) 1992-02-10 1998-06-18 三菱マテリアル株式会社 貼り合わせ誘電体分離ウェーハの製造方法
JP2967398B2 (ja) * 1995-09-18 1999-10-25 信越半導体株式会社 シリコンウエーハ内部の不純物分析方法
JP3391184B2 (ja) * 1996-03-28 2003-03-31 信越半導体株式会社 シリコンウエーハおよびその製造方法
KR100218347B1 (ko) * 1996-12-24 1999-09-01 구본준 반도체기판 및 그 제조방법
US6479166B1 (en) 1998-10-06 2002-11-12 Case Western Reserve University Large area polysilicon films with predetermined stress characteristics and method for producing same
JP3601763B2 (ja) * 1998-12-17 2004-12-15 三菱住友シリコン株式会社 誘電体分離ウェーハおよびその製造方法
US6815774B1 (en) * 1998-10-29 2004-11-09 Mitsubishi Materials Silicon Corporation Dielectrically separated wafer and method of the same
US6500717B2 (en) * 2000-12-01 2002-12-31 Agere Systems Inc. Method for making an integrated circuit device with dielectrically isolated tubs and related circuit
US6770966B2 (en) * 2001-07-31 2004-08-03 Intel Corporation Electronic assembly including a die having an integrated circuit and a layer of diamond to transfer heat
US6991999B2 (en) * 2001-09-07 2006-01-31 Applied Materials, Inc. Bi-layer silicon film and method of fabrication
US6964880B2 (en) * 2003-06-27 2005-11-15 Intel Corporation Methods for the control of flatness and electron mobility of diamond coated silicon and structures formed thereby
US20070032040A1 (en) 2003-09-26 2007-02-08 Dimitri Lederer Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses
FR2860341B1 (fr) * 2003-09-26 2005-12-30 Soitec Silicon On Insulator Procede de fabrication de structure multicouche a pertes diminuees
US6902977B1 (en) * 2003-10-03 2005-06-07 Advanced Micro Devices, Inc. Method for forming polysilicon gate on high-k dielectric and related structure
JP4730581B2 (ja) * 2004-06-17 2011-07-20 信越半導体株式会社 貼り合わせウェーハの製造方法
EP1835533B1 (en) * 2006-03-14 2020-06-03 Soitec Method for manufacturing compound material wafers and method for recycling a used donor substrate
CN101432849B (zh) * 2006-04-27 2011-03-16 信越半导体股份有限公司 Soi晶片的制造方法
KR100841994B1 (ko) * 2006-12-20 2008-06-27 주식회사 실트론 실리콘 웨이퍼의 산화막 제조 방법
JP2009238902A (ja) * 2008-03-26 2009-10-15 Toshiba Corp 半導体発光素子
FR2943458B1 (fr) * 2009-03-18 2011-06-10 Soitec Silicon On Insulator Procede de finition d'un substrat de type "silicium sur isolant" soi
JP5356872B2 (ja) * 2009-03-18 2013-12-04 パナソニック株式会社 個体撮像装置の製造方法
JP5532680B2 (ja) 2009-05-27 2014-06-25 信越半導体株式会社 Soiウェーハの製造方法およびsoiウェーハ
JP5209592B2 (ja) * 2009-11-25 2013-06-12 独立行政法人科学技術振興機構 受光素子の作製方法
FR2953640B1 (fr) 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
US8815641B2 (en) * 2010-01-29 2014-08-26 Soitec Diamond SOI with thin silicon nitride layer and related methods
US8895435B2 (en) * 2011-01-31 2014-11-25 United Microelectronics Corp. Polysilicon layer and method of forming the same
JP5673170B2 (ja) * 2011-02-09 2015-02-18 信越半導体株式会社 貼り合わせ基板、貼り合わせ基板の製造方法、半導体デバイス、及び半導体デバイスの製造方法
JP2012174884A (ja) * 2011-02-22 2012-09-10 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
JP5051862B1 (ja) * 2011-03-18 2012-10-17 株式会社ソディック 直管型発光ダイオード式照明灯
FR2973158B1 (fr) 2011-03-22 2014-02-28 Soitec Silicon On Insulator Procédé de fabrication d'un substrat de type semi-conducteur sur isolant pour applications radiofréquences
US9356171B2 (en) * 2012-01-25 2016-05-31 The Trustees Of Dartmouth College Method of forming single-crystal semiconductor layers and photovaltaic cell thereon
US9337395B2 (en) * 2012-04-30 2016-05-10 Tubitak Methods for producing new silicon light source and devices
JP6070487B2 (ja) * 2013-09-04 2017-02-01 信越半導体株式会社 Soiウェーハの製造方法、soiウェーハ、及び半導体デバイス

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI717504B (zh) * 2016-06-06 2021-02-01 日商信越半導體股份有限公司 貼合式soi晶圓的製造方法
CN109643670A (zh) * 2016-09-07 2019-04-16 信越半导体株式会社 贴合用基板的表面缺陷的评价方法
CN109643670B (zh) * 2016-09-07 2022-10-11 信越半导体株式会社 贴合用基板的表面缺陷的评价方法

Also Published As

Publication number Publication date
US10460983B2 (en) 2019-10-29
US20170040210A1 (en) 2017-02-09
KR20160145600A (ko) 2016-12-20
KR102312812B1 (ko) 2021-10-15
SG11201608562RA (en) 2016-11-29
TWI590298B (zh) 2017-07-01
EP3136421B1 (en) 2020-12-02
WO2015162839A1 (ja) 2015-10-29
JP2015211061A (ja) 2015-11-24
JP6100200B2 (ja) 2017-03-22
CN106233425A (zh) 2016-12-14
EP3136421A4 (en) 2017-12-13
CN106233425B (zh) 2019-07-12
EP3136421A1 (en) 2017-03-01

Similar Documents

Publication Publication Date Title
TWI590298B (zh) Method of manufacturing a bonded SOI wafer
TWI610335B (zh) 貼合式soi晶圓的製造方法及貼合式soi晶圓
TWI692001B (zh) 貼合式soi晶圓的製造方法
TWI709197B (zh) 製造具有電荷捕捉層之高電阻率絕緣體上半導體晶圓之方法
JP2015228432A (ja) Soiウェーハの製造方法及び貼り合わせsoiウェーハ
WO2017212812A1 (ja) 貼り合わせsoiウェーハの製造方法
JP5942948B2 (ja) Soiウェーハの製造方法及び貼り合わせsoiウェーハ
CN109075028B (zh) 贴合式soi晶圆的制造方法
TWI804626B (zh) 貼合式soi晶圓的製造方法及貼合式soi晶圓
TWI709999B (zh) 貼合式soi晶圓的製造方法
JP2018137278A (ja) 貼り合わせsoiウェーハの製造方法