TW201539652A - 整合式金屬間隔墊及氣隙互連 - Google Patents

整合式金屬間隔墊及氣隙互連 Download PDF

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TW201539652A
TW201539652A TW104109215A TW104109215A TW201539652A TW 201539652 A TW201539652 A TW 201539652A TW 104109215 A TW104109215 A TW 104109215A TW 104109215 A TW104109215 A TW 104109215A TW 201539652 A TW201539652 A TW 201539652A
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TWI603429B (zh
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He Ren
Mehul B Naik
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Applied Materials Inc
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Abstract

本文所述之實施例關於形成氣隙互連的方法。將金屬間隔墊層共形地沉積於上方形成有心軸結構的基板上。蝕刻金屬間隔墊層以形成間隔墊特徵並自基板移除心軸結構。可執行多種其他介電質沉積、圖案化與蝕刻步驟以如期望般圖案化基板上存在的材料。最終，在相鄰間隔墊特徵之間形成溝槽並在溝槽上沉積蓋層以在相鄰間隔墊特徵之間形成氣隙。為了封裝，互連介層洞可設以接觸相鄰氣隙之間隔墊特徵的至少一者。

Description

整合式金屬間隔墊及氣隙互連
本文所述之實施例大致關於形成具有氣隙之半導體元件的方法。更明確地，本文所述之實施例關於整合式金屬間隔墊與氣隙互連。
對於先進節點技術而言，互連RC延遲(轉換性能)與歸因於電容的功率阻尼是元件性能的重要閥值。由於傳統低k材料在降低介電常數(k值)的縮放性能限制(這是因為會損害機械強度與電流洩漏性能)，一個可用於電容縮放的有希望候選者包括在金屬線路之間採用氣隙。氣隙具有接近1.0的k值，這有助於降低元件中的整體有效k值至可接受水平。然而，氣隙整合需要額外的製程步驟，包括排除遮罩微影術、介電質凹部、襯裡沉積、介電質沉積、介電質化學機械研磨(CMP)等等。這些額外的步驟提高整合氣隙的成本並降低氣隙技術的優點與接受性。
此外，通常使用雙圖案化而非單印刷圖案化來形成氣隙。雙圖案化的某些實例包括微影-蝕刻-微影-蝕刻(LELE)與間隔墊對齊雙圖案化(SADP)。這些雙圖案化技術不僅需要額外的暴露與蝕刻製程，且亦需要遮罩以界定連接器與接線 端點。雙圖案化製程傳送期望設計至最終產物，但卻是以增加的成本與降低的效率來執行。
因此，需要的是形成氣隙互連結構的改善方法。
在一個實施例中，提供形成半導體元件的方法。方法包括共形地沉積金屬間隔墊層於心軸結構上，並蝕刻金屬間隔墊層的至少一部分以形成一或多個間隔墊特徵。移除心軸結構，將介電層沉積在間隔墊特徵上，並圖案化且在相鄰間隔墊特徵之間蝕刻介電層。接著非共形地沉積蓋層在間隔墊特徵上以在相鄰間隔墊特徵之間形成氣隙。
在另一個實施例中，提供形成半導體元件的方法。方法包括共形地沉積金屬間隔墊層於心軸結構上，並蝕刻金屬間隔墊層的至少一部分以形成一或多個間隔墊特徵。移除心軸結構，將可流動介電層沉積在金屬間隔墊層上，並圖案化可流動介電層的第一區域。接著蝕刻間隔墊特徵的至少一者與可流動介電層以形成第一溝槽，且將可流動介電層重新沉積於第一溝槽中。圖案化並在相鄰間隔墊特徵之間蝕刻可流動介電層的第二區域以形成第二溝槽。將蓋層非共形地沉積在間隔墊特徵、第二溝槽與可流動介電層上以在第二溝槽中形成氣隙。最終，平面化蓋層的至少一部分與可流動介電層。
在又另一個實施例中，提供形成半導體元件的方法。方法包括提供上方形成有氧化物心軸結構的基板並共形地沉積金屬間隔墊層於氧化物心軸結構上。蝕刻金屬間隔墊 層的至少一部分以形成一或多個間隔墊特徵。蝕刻心軸結構，沉積可流動介電層在金屬間隔墊層上，並圖案化可流動介電層的第一區域。蝕刻第一區域中間隔墊特徵的至少一者與可流動介電層以形成第一溝槽，並將可流動介電層重新沉積於第一溝槽中。圖案化可流動介電層的第二區域，並蝕刻第二區域中相鄰間隔墊特徵之間的可流動介電層以形成第二溝槽。將含矽蓋層沉積在間隔墊特徵、第二溝槽與可流動介電層上以在第二溝槽中形成氣隙。研磨蓋層的至少一部分與可流動介電層以形成平坦化表面，且互連形成通過基板到達相鄰氣隙之間隔墊特徵的至少一者。
100‧‧‧元件結構
102‧‧‧基板
104‧‧‧心軸結構
106‧‧‧金屬間隔墊層
107‧‧‧間隔墊特徵
108‧‧‧頂面
110‧‧‧表面
112‧‧‧介電層
114‧‧‧第一遮罩
116‧‧‧第一區域
117‧‧‧第一溝槽
118‧‧‧第二遮罩
120‧‧‧第二區域
121‧‧‧第二溝槽
122‧‧‧暴露表面
123‧‧‧氣隙
124‧‧‧蓋層
126‧‧‧互連
200‧‧‧設備
202‧‧‧基板搬運部分
204‧‧‧基板製程部分
206‧‧‧負載平台
208‧‧‧傳送平台
210‧‧‧介面平台
212‧‧‧入口負載鎖定腔室
214‧‧‧出口負載鎖定腔室
216‧‧‧基板製程腔室
218‧‧‧傳送機器人
220‧‧‧傳送腔室
為了詳細理解本揭露內容上述之特徵，可參照某些實施例來理解簡短概述於上的本揭露內容的更明確描述，該等實施例中之一些實施例圖示於附圖中。然而，需注意附圖僅描繪本揭露內容之典型實施例而因此附圖不被視為本揭露內容之範圍的限制因素，因為本揭露內容可接納其他等效實施例。
第1-15圖是描繪根據本文揭露之一個實施例形成氣隙互連之順序的基板示意性橫剖面圖。
第16圖是可用於執行本文所述之多種製程之設備的示意性平面圖。
為了促進理解，已經盡可能應用相同的元件符號來標示圖式中共有的相同元件。預期一個實施例揭露的元件可有利地用於其他實施例而不需特別詳述。
本文所述之實施例關於形成氣隙互連的方法。將金屬間隔墊層共形地沉積在上方形成有心軸結構之基板上。蝕刻金屬間隔墊層以形成間隔墊特徵並自基板移除心軸結構。可執行多種其他介電質沉積、圖案化與蝕刻步驟以如期望般圖案化基板上存在的材料。由於製程順序之故，在相鄰間隔墊特徵之間形成溝槽並在溝槽上沉積蓋層以在相鄰間隔墊特徵之間形成氣隙。為了封裝，互連介層洞可設以接觸相鄰氣隙之間隔墊特徵的至少一者。
下方詳細描述之形成順序描繪半導體元件在不同製造階段的部分圖示。除了形成氣隙互連之外，預期下方描述之方法可用以形成互連技術以外應用的氣隙。下方描述之順序提供形成氣隙互連的一個實施例，然而應當理解可在順序上重新排列、刪除、重複或以上述之任何組合來執行形成順序的不同操作。
第1圖描繪元件結構100的示意性橫剖面圖。元件結構100包括基板102與一或多個形成在基板102上之心軸結構104。在一個實施例中，基板102包括蝕刻終止層且可由不同材料所形成，諸如SiN、SiCN、SiOC、SiON、Si、C、O、N、金屬氮化物(例如，AlN)與上述之組合。心軸結構104彼此間隔以界定後續沉積材料的模板。心軸結構104由氧化物或含矽材料所形成。舉例而言，心軸結構104可由二氧化矽或聚矽所形成。
第2圖是描繪金屬沉積製程結果之元件結構100的 示意性橫剖面圖。將金屬間隔墊層106共形地沉積在基板102與心軸結構104上。金屬間隔墊層106使用之材料的實例包括金屬有機化學氣相沉積(MOCVD)的鎢、物理氣相沉積(PVD)的金屬矽化物與化學氣相沉積(CVD)的金屬矽化物。適當金屬矽化物材料的實例包括矽化鈷、矽化鈦、矽化鎳與上述之組合。
金屬間隔墊層材料可經選擇以致金屬間隔墊層106與心軸結構104材料反應以形成元件結構100的最終金屬線路。在已經沉積金屬間隔墊層106之後，可執行沉積後矽化製程以助長金屬間隔墊層106/心軸結構104反應。得到的心軸結構104維持介電質性質，而將金屬間隔墊層106形成為低電阻率導體。
適當的心軸結構材料與金屬間隔墊層材料組合之實例包括氧化物/MOCVD鎢、聚矽/MOCVD鎢與氧化物或矽/矽化物。金屬間隔墊層材料亦可包括鎳、鈷、鎢等等。共形地沉積在心軸結構104上之金屬間隔墊層106形成金屬互連線路，因此降低或排除傳統氣隙互連技術中傳統金屬縫隙填充的必要性。再者，直接在最終金屬線路(金屬間隔墊層106)上執行更詳細描述於下方之圖案化製程，這降低或排除氣隙互連形成之圖案轉移蝕刻步驟的必要性。
第3圖是描繪蝕刻製程結果之元件結構100的示意性橫剖面圖。非等向性地蝕刻金屬間隔墊層106以移除金屬間隔墊層106的數個部分。在一個實例中，可應用非等向性乾電漿蝕刻製程。若金屬間隔墊層106包括鎢，可應用CF4 乾電漿來蝕刻金屬間隔墊層106。在此實例中，在具有約10mT與約50mT間之壓力的環境中以約50sccm至約200sccm間之速率流動CF4前驅物氣體。可用約200W與約400W間之RF功率與約100W與約500W間之偏壓將CF4激發成電漿。可用於執行所述之蝕刻製程的製程腔室之一個實例是自Applied Material,Inc.(Santa Clara,CA)取得的MESATM蝕刻腔室。然而，預期來自其他製造商的其他相似設置的腔室亦可執行所述之製程。
由於蝕刻製程之故，移除金屬間隔墊層106的至少一部分以暴露心軸結構104的頂面108與基板102的表面110。金屬間隔墊層106的蝕刻可為時間依賴式或終點控制式以使得金屬間隔墊層106的剩餘部分與心軸結構104的頂面108共面。在蝕刻金屬間隔墊層106之後，先前連續的金屬間隔墊層106現今包括分離的不連續結構。這些結構可被稱為間隔墊特徵106。本文後續使用之詞彙間隔墊特徵107與金屬間隔墊層106指的是相同材料，然而間隔墊特徵107是金屬間隔墊層106的蝕刻後形式。
第4圖是描繪蝕刻製程結果之元件結構100的示意性橫剖面圖。利用與間隔墊特徵107之金屬材料不反應的選擇性蝕刻製程來蝕刻心軸結構104。在一個實施例中，利用稀釋HF溶液之濕蝕刻製程被用來蝕刻心軸結構104。濕蝕刻製程可進行一段足以自基板102完全移除心軸結構104的時間。在另一個實施例中，利用NF3與NH3的非等向性乾蝕刻製程可被用來移除心軸結構104。在此實例中，可在具有約 200mT與約3000mT間之壓力的環境中，以約10sccm與約200sccm間之速率流動NF3前驅物氣體並以約100sccm與約1000sccm間之速率流動NH3前驅物氣體。可用約200W與約2000W間之RF功率將NF3與NH3激發成電漿。得到的元件結構100包括彼此藉由基板102之暴露表面110而分隔的間隔墊特徵107。第1圖至第4圖中所述之製程完成金屬間隔墊層106的圖案化。
第5圖是描繪可流動CVD沉積製程結果之元件結構100的示意性橫剖面圖。如圖所示，藉由可流動或類流動CVD製程將介電層112沉積在元件結構100上並覆蓋基板102與間隔墊特徵107。以毯覆方式沉積介電層112，以致介電層112填充相鄰間隔墊特徵107間之空間並接觸基板102。由於可流動介電層112的特徵，最小化或排除介電層112中的空隙且介電層112的頂面是實質上平坦的。用設以延伸超過間隔墊特徵107的厚度來沉積介電層112。
在可流動CVD製程的一個實例中，在約100℃或更低的溫度下反應有機矽前驅物與氧前驅物以形成介電層112。適當的有機矽前驅物具有低於約8的碳原子與矽原子比例。適當的有機矽化合物亦可具有約0至約6的氧與矽原子比例，且可包括Si-O-Si連接，Si-O-Si連接促進形成具有來自碳與經基基團之污染物降低的SiOx膜。適當的氧前驅物可包括氧分子(O2)、臭氧(O3)、氮-氧化合物(諸如，NO、NO2或N2O)、氫-氧化合物(諸如，水或過氧化物)、碳-氧化合物(諸如，一氧化碳或二氧化碳)與其他含氧前驅物。在一個實施例 中，介電層112包括SiOCH且具有約2.0與約3.0間之k值。
亦可與有機矽與氧前驅物一起提供載氣(例如，惰性氣體)。可在引導至腔室之前激發氧前驅物，例如利用遠端電漿產生器，遠端電漿產生器可包括熱解離、紫外光解離、RF、DC與/或微波解離。在一個實施例中，可將4-6kW的RF功率耦接至900-1,800sccm的氬與600-1,200sccm的氧分子流動。可與氧前驅物分隔地提供有機矽前驅物至腔室以避免腔室外部的反應。可引導有機矽前驅物成為在約800mgm至約1,600mgm的液體-當量流動速率下至腔室之氣體。可包括在約600sccm至約2,400sccm的流動速率下之氦作為載氣。可引導在約3sLm與約20sLm間之流動速率下的激發氧前驅物至腔室。
前驅物反應以沉積可流動氧化物層或介電層112於基板102上。上述之CVD製程可實施於自Applied Materials,Inc.(Santa Clara,California)取得之PRODUCER® ETERNATM FCVD系統上。然而，預期來自其他製造商的其他相似設置的腔室亦可執行所述之製程。
第6圖是描繪遮罩形成與圖案化製程結果之元件結構100的示意性橫剖面圖。將第一遮罩114(例如，光阻劑材料)沉積於介電層112上並接著加以圖案化。第一遮罩114可為毯覆沉積於介電層112上之感光性聚合物材料。圖案化第一遮罩114以形成暴露的第一區域116。在一個實施例中，利用193nm浸潤式微影術製程來圖案化第一遮罩114並暴露第一區域116。移除第一區域116中之第一遮罩114並暴露介電 層112。在一個實施例中，間隔墊特徵107的至少一者被包括於第一區域116中的下方。在一實例中，第一區域116界定後續將自元件結構100移除之接線端點。
第7圖是描繪接線端點移除製程結果之元件結構100的示意性橫剖面圖。可應用非等向性蝕刻製程以移除第一區域116(參見第6圖)中之材料好形成第一溝槽117。可應用多種蝕刻技術，包括濕蝕刻與乾電漿蝕刻技術。在此實例中，應用一或多個蝕刻劑以移除第一區域116中之介電層112與間隔墊特徵107好形成第一溝槽117。舉例而言，可應用可移除第一區域116中之介電層112與間隔墊特徵106兩者之單一蝕刻劑或對介電層112或間隔墊特徵107任一者具選擇性的多個蝕刻劑來形成第一溝槽117。第一溝槽117的底部由基板102的表面110所界定，而第一溝槽117的側壁由介電層112所界定。藉由移除第一區域116中之間隔墊特徵107而形成元件結構100的接線端點以產生期望的線路結構，並可進行進一步製程。
第8圖是描繪遮罩移除製程結果之元件結構100的示意性橫剖面圖。如圖所示，已經移除第一遮罩114以暴露介電層112。可藉由多種方法(包括灰化或蝕刻第一遮罩114)來移除第一遮罩114。舉例而言，藉由對介電層112之材料具選擇性的濕清潔製程來移除第一遮罩114。
第9圖是描繪可流動介電質沉積製程結果之元件結構100的示意性橫剖面圖。根據詳細參照第5圖所示之製程以可流動介電層112填充第一溝槽117。得到的介電層112 具有相似於最初沉積之介電層112的特徵。
第10圖是描繪遮罩形成與圖案化製程結果之元件結構100的示意性橫剖面圖。將第二遮罩118(可以相似於第一遮罩114之方式加以形成)沉積於介電層112上並經圖案化以暴露第二區域120。第二遮罩118可保護先前暴露的第一區域116與填充第一溝槽117之後續沉積的介電層112。以相似於第一遮罩114之圖案化的方式來執行第二遮罩118的圖案化。在一個實施例中，第一遮罩114與第二遮罩118可為分隔的遮罩或相同的遮罩。若第一遮罩114與第二遮罩118形成單一遮罩，則將微影術製程弄成反向(reverse tone)阻劑，以致元件結構100的保護區域互補。第二區域120暴露配置於相鄰間隔墊特徵107上之介電層112的至少一部分。
第11圖是描繪介電質蝕刻製程結果之元件結構100的示意性橫剖面圖。此處，蝕刻第二區域120中之介電層112以暴露相鄰間隔墊特徵106的至少一部分與基板102的表面。因此，在相鄰間隔墊特徵106之間形成第二溝槽121。第二溝槽121可具有約1.5：1.0與約5.0：1.0間之深寬比。利用鈍化乾電漿蝕刻製程來蝕刻介電層112。應用之蝕刻劑物種可展現介電層112與間隔墊特徵106之金屬之間的高度選擇性。
在一個實施例中，利用C4F6來蝕刻介電層112。在此實例中，可在具有約200mT之壓力的環境中以約10sccm的速率流動C4F6前驅物氣體。可用約100W與約2000W間之RF功率與約50W與約500W間之偏壓將C4F6激發成電 漿。蝕刻劑物種經較佳地選擇以保護間隔墊特徵107之暴露表面122同時蝕刻介電層112。相似地，蝕刻劑物種對基板102具選擇性並經過選擇以蝕刻介電層112。在一個實施例中，可沉積介電質襯裡以鈍化間隔墊特徵107的暴露表面122。介電質襯裡可包括諸如Si、O、C、N、H與上述之組合的材料。
第12圖是描繪遮罩移除製程結果之元件結構100的示意性橫剖面圖。如圖所示，移除第二遮罩118以暴露介電層112。可藉由與用於移除第一遮罩114之製程相似的製程來移除第二遮罩118。
第13圖是描繪蓋層沉積製程結果之元件結構100的示意性橫剖面圖。將蓋層124沉積於元件結構100上，並覆蓋相鄰第二溝槽121之間隔墊特徵107的暴露表面122(參見第12圖)的至少一部分與介電層112。蓋層124包括低k含矽材料。舉例而言，蓋層124材料可包括SiOC、SiOCN、SiCN等等。
在一個實施例中，利用SiOC作為蓋層124。在此實例中，可在具有約1000mT與約3000mT間之壓力的環境中，以約50sccm與約500sccm間之速率流動有機含矽前驅物氣體並以約200sccm與約1000sccm間之速率流動含氧前驅物。可用約500W與約2000W間之RF功率將前驅物激發成電漿。在一個實例中，蓋層124沉積是橋接第二溝槽121之表面彎曲依賴性毯覆沉積製程。沉積製程可為時間依賴性CVD製程。
蓋層124沉積設以在第二溝槽121的一部分中沉積材料。因此，蓋層124可完全覆蓋相鄰第二溝槽121之間隔墊特徵106的頂部暴露表面122，並僅覆蓋相鄰第二溝槽121之間隔墊特徵106的側壁暴露表面122的一部分。蓋層124沉積製程設以避免蓋層124沉積在基板102的表面110上。因此，在相鄰間隔墊特徵107間之第二溝槽121中形成氣隙123。可藉由相鄰間隔墊特徵107、基板102與蓋層124來界定氣隙123。氣隙123實質上缺少空氣以外的任何材料。
第14圖是描繪CMP製程結果之元件結構的示意性橫剖面圖。先前沉積之介電層112與蓋層124可具有橫跨元件結構100之表面的非均勻厚度。執行CMP製程或其他平坦化製程以平坦化元件結構100的頂面，以致間隔墊特徵106、介電層112與蓋層124實質上共面。在一個實施例中，可應用間隔墊特徵107作為堅硬阻擋物，以確定平坦化/研磨終點。CMP製程可實施於自Applied Materials,Inc.(Santa Clara,CA)取得的REFLEXION GTTM系統或其他相容的CMP系統。亦可應用來自其他製造商的平坦化系統來執行所述製程。
CMP製程造成元件結構100具有平坦化上表面，並具有配置於第二溝槽121之上部分中的剩餘蓋層124部分以在下方界定氣隙123。在此氣隙整合方案中可執行CMP製程僅僅一次，因此排除傳統氣隙整合方案中金屬CMP與介電質CMP之多次CMP製程的必要性。
第15圖是描繪互連形成製程結果之元件結構100的示意性橫剖面圖。形成至少通過基板102之互連126至相鄰 氣隙123之導電性間隔墊特徵107的一者。可藉由蝕刻或燒蝕製程來形成介層洞(未圖示)，且可用互連材料來填充得到的介層洞。互連126可為導電材料(諸如，金屬或金屬矽化物)並可藉由多種製程加以沉積，多種製程包括CVD、PVD、原子層沉積(ALD)與磊晶沉積等等。互連126電性連接間隔墊特徵107至半導體元件的其他部件並可用於半導體封裝製程過程中。
第16圖是可用於執行本文所述之多種製程之設備200的示意平面圖。設備200包括基板搬運部分202與基板製程部分204。基板搬運部分202包括負載平台206、傳送平台208與介面平台210。在負載平台206處將基板載入設備200中。在某些實例中，負載操作可包括配置一或多個基板於用以傳送通過設備200之載體上。傳送平台208由負載平台206移動基板至介面平台210。若需要的話，傳送平台208可包括基板搬運特徵(例如，鰭狀件)。介面平台208提供基板至入口負載鎖定腔室212以進入通常在真空下運作的基板製程部分204。基板製程部分204包括複數個耦接至傳送腔室220的基板製程腔室216，傳送腔室220中配置有傳送機器人218。各個製程腔室216可為ALD腔室、低溫CVD腔室、高密度電漿CVD腔室、PECVD腔室、蝕刻腔室或電漿清潔腔室。在一個實施例中，腔室216包括形成可流動介電層之電漿CVD腔室以及可蝕刻矽層、氧化物層與/或金屬層之電漿蝕刻腔室。電漿CVD腔室可為HDP CVD腔室，而電漿蝕刻腔室可為遠端電漿腔室。出口負載鎖定腔室214接收處理過的基板 以傳送回基板搬運部分202。
在特徵為複數個配置於基板載體上以進行製程之基板的實施例中，製程腔室216各自可在同一時間下處理複數個基板。當應用設備200來執行上述之方法時，可同時在複數個基板上執行任何或所有製程。
雖然上文針對本揭露內容之實施例，但可設計出本揭露內容的其他與進一步實施例而不悖離本揭露內容之基本範圍，本揭露內容之範圍由後續之申請專利範圍所確定。
100‧‧‧元件結構
102‧‧‧基板
107‧‧‧間隔墊特徵
110‧‧‧表面
112‧‧‧介電層
123‧‧‧氣隙
124‧‧‧蓋層

Claims (20)

  1. 一種形成一半導體元件的方法，該方法包括：共形地沉積一金屬間隔墊層於一心軸結構上；蝕刻該金屬間隔墊層的至少一部分以形成一或多個間隔墊特徵；移除該心軸結構；沉積一介電層於該些間隔墊特徵上；圖案化該介電層；鈍化地蝕刻該些相鄰間隔墊特徵間之該介電層；及非共形地沉積一蓋層於該些間隔墊特徵上，其中一氣隙形成於該些相鄰間隔墊特徵之間。
  2. 如請求項1之方法，其中該心軸結構是一氧化物材料或一含矽材料。
  3. 如請求項2之方法，其中該金屬間隔墊層包括鎢或金屬矽化物材料。
  4. 如請求項1之方法，其中該金屬間隔墊層係選自鎢、鈷與鎳所構成之群組。
  5. 如請求項4之方法，其中該金屬間隔墊層係藉由一MOCVD製程而加以形成。
  6. 如請求項1之方法，其中該介電層係藉由一可流動CVD製程而加以沉積。
  7. 如請求項6之方法，其中該介電層包括一可調整低k材料。
  8. 如請求項7之方法，其中該介電層包括SiOCH。
  9. 如請求項1之方法，其中該些相鄰間隔墊特徵界定一溝槽，該溝槽具有一在1.5：1與5：1間之深寬比。
  10. 如請求項9之方法，其中該溝槽的一上方區域由該蓋層所界定。
  11. 如請求項10之方法，其中該蓋層包括一含矽材料。
  12. 一種形成一半導體元件的方法，該方法包括：共形地沉積一金屬間隔墊層在一心軸結構上；蝕刻該金屬間隔墊層的至少一部分以形成一或多個間隔墊特徵；移除該心軸結構；沉積一可流動介電層在該金屬間隔墊層上；圖案化該可流動介電層的一第一區域； 蝕刻該些間隔墊特徵的至少一者與該可流動介電層以形成一第一溝槽；重新沉積該可流動介電層於該第一溝槽中；圖案化該可流動介電層的一第二區域；蝕刻該些相鄰間隔墊特徵之間的該可流動介電層以形成一第二溝槽；非共形地沉積一蓋層在該些間隔墊特徵、該第二溝槽與該可流動介電層上，其中一氣隙形成於該第二溝槽中；及平坦化該蓋層的至少一部分與該可流動介電層。
  13. 如請求項12之方法，進一步包括形成一互連至相鄰該氣隙之該些間隔墊特徵的至少一者。
  14. 如請求項12之方法，其中該研磨包括一介電質CMP製程。
  15. 如請求項14之方法，其中該些間隔墊特徵界定該研磨的一停止點。
  16. 如請求項12之方法，其中該蓋層延伸進入該第二溝槽並低於該些間隔墊特徵的一頂面。
  17. 如請求項16之方法，其中該蓋層包括一含矽材料。
  18. 如請求項12之方法，其中該第二溝槽具有一在1.5：1與5：1間之深寬比。
  19. 如請求項18之方法，其中該第二溝槽的一上方區域由該蓋層所界定。
  20. 一種形成一半導體元件的方法，該方法包括：配置一基板於一製程腔室中，該基板上方形成有一氧化物心軸結構；共形地沉積一金屬間隔墊層於該氧化物心軸結構上；非等向性地乾電漿蝕刻該金屬間隔墊層的至少一部分以形成一或多個間隔墊特徵；蝕刻該心軸結構；沉積一可流動介電層於該金屬間隔墊層上；圖案化該可流動介電層的一第一區域；蝕刻該第一區域中該些間隔墊特徵的至少一者與該可流動介電層以形成一第一溝槽；重新沉積該可流動介電層於該第一溝槽中；圖案化該可流動介電層的一第二區域；蝕刻該第二區域中該些相鄰間隔墊特徵之間的該可流動介電層以形成一第二溝槽；非共形地沉積一含矽蓋層在該些間隔墊特徵、該第二溝槽與該可流動介電層上，其中一氣隙形成於該第二溝槽中； 平坦化該蓋層的至少一部分與該可流動介電層以形成一平坦化表面；及形成一互連通過該基板至相鄰該氣隙之該些間隔墊特徵的至少一者。
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US9305831B2 (en) 2016-04-05
US20150279726A1 (en) 2015-10-01
US9640424B2 (en) 2017-05-02
CN110444509A (zh) 2019-11-12
KR102414130B1 (ko) 2022-06-27
TW201804567A (zh) 2018-02-01
KR20210125113A (ko) 2021-10-15
TWI603429B (zh) 2017-10-21
CN106537576A (zh) 2017-03-22
WO2015153040A1 (en) 2015-10-08
KR20160138290A (ko) 2016-12-02
TWI645506B (zh) 2018-12-21
US20160211172A1 (en) 2016-07-21
CN106537576B (zh) 2019-08-27
KR102312269B1 (ko) 2021-10-12

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