TWI594370B - 作爲先進互連之介電覆蓋障壁的含金屬膜 - Google Patents

作爲先進互連之介電覆蓋障壁的含金屬膜 Download PDF

Info

Publication number
TWI594370B
TWI594370B TW103142212A TW103142212A TWI594370B TW I594370 B TWI594370 B TW I594370B TW 103142212 A TW103142212 A TW 103142212A TW 103142212 A TW103142212 A TW 103142212A TW I594370 B TWI594370 B TW I594370B
Authority
TW
Taiwan
Prior art keywords
layer
metal
dielectric layer
dielectric
low
Prior art date
Application number
TW103142212A
Other languages
English (en)
Other versions
TW201528430A (zh
Inventor
陳一宏
美歐里克愛柏亥吉巴蘇
那克美荷Ｂ
奈馬尼史林尼法斯Ｄ
Original Assignee
應用材料股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 應用材料股份有限公司 filed Critical 應用材料股份有限公司
Publication of TW201528430A publication Critical patent/TW201528430A/zh
Application granted granted Critical
Publication of TWI594370B publication Critical patent/TWI594370B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

作為先進互連之介電覆蓋障壁的含金屬膜
本發明的態樣大致關於用於半導體元件中之互連結構與形成上述結構的方法。
自從180奈米CMOS技術結點以後，由於銅互連的高互連傳導性與電遷移抗性，銅互連已經變成產業標準。然而，與其他過渡金屬相比，銅在矽基材料中具有遠遠較高的擴散率。元件運作過程中，銅原子快速擴散進入周圍二氧化矽或其他低介電常數介電材料造成短路路徑，短路路徑劣化介電層並造成元件失敗。因此，介電可靠性變成銅互連結構中的一個主要考量點。目前解決方案為將銅互連嵌入氮化鉭或鉭側壁阻障層中，並以含矽介電覆蓋層(諸如，氮化矽或碳化矽)封裝銅互連。由於電遷移的常見失敗機制是透過覆蓋層，覆蓋層的性質特別重要。
將覆蓋層製成更厚點來避免電遷移非為有效解決方案，因為金屬化堆疊中覆蓋層的介電常數是最高的，這嚴重 地損害互連級的有效介電常數。因此，覆蓋層的厚度必須最小化，同時仍維持有效的擴散阻擋特徵與相鄰層間的良好附著強度。
半導體元件的製造商永遠追求較低成本下的較小幾何結構與增加的容量。因此，亦必須降低互連結構與其各自覆蓋層的尺寸。因為難以在小於20奈米的厚度下確保必要的擴散阻擋特徵，含矽介電覆蓋層(諸如，氮化矽或碳化矽層)的厚度已經被限制為約20奈米。已經提出替代方案，例如在銅與含矽介電覆蓋層之間利用選擇性金屬覆蓋阻障層或銅氮化矽緩衝層。然而，由於互連抗性的增加並不樂見上述方案，互連抗性的增加會降低元件性能。
因此，存在改善互連結構與形成上述結構之方法的需求。
在一個實施例中，提供形成用於半導體元件中之互連結構的方法。方法包括形成低介電常數塊狀介電層於基板上；在低介電常數塊狀介電層中形成溝槽；在低介電常數塊狀介電層上形成襯裡層，襯裡層共形地沉積至溝槽；在襯裡層上形成銅層，其中銅層填充溝槽；移除銅層與襯裡層的部分以暴露低介電常數塊狀介電層的上表面、襯裡層的上表面與銅層的上表面；及在低介電常數塊狀介電層的上表面、襯裡層的上表面與銅層的上表面上形成含金屬介電層，其中含金屬介電層是選自金屬氧化物、金屬氮化物與金屬氮氧化物所構成之群組的金屬化合物。
在另一個實施例中，提供半導體互連結構。互連結構包括基板；低介電常數塊狀介電層，低介電常數塊狀介電層具有溝槽形成於低介電常數塊狀介電層中；襯裡層，共形地沉積於低介電常數塊狀介電層上且在溝槽之中；銅層，配置於襯裡層上且填充溝槽；及含金屬介電層，含金屬介電層具有接觸低介電常數塊狀介電層、襯裡層與銅層的底面，其中含金屬介電層是選自由金屬氧化物、金屬氮化物與金屬氮氧化物所構成之群組的金屬化合物。
100‧‧‧製程
102、104、106、108、110、112、114、116‧‧‧方塊
118‧‧‧決定操作
200‧‧‧基板
210‧‧‧低介電常數塊狀介電層
212‧‧‧溝槽
214‧‧‧襯裡層
216‧‧‧銅層
218‧‧‧介電層
220‧‧‧額外的低介電常數塊狀介電層
為了詳細理解本發明上述之特徵，可參照某些實施例來理解簡短概述於上的本發明的更明確描述，該等實施例中之一些實施例圖示於附圖中。然而，需注意附圖僅描繪本發明之典型實施例而因此附圖不被視為本發明之範圍的限制因素，因為本發明可接納其他等效實施例。
第1圖是形成互連結構之製程的製程流程圖。
第2A-2G圖描繪第1圖之製程的不同階段之互連結構。
為了促進理解，已經盡可能應用相同的元件符號來標示圖式中共有的相同元件。預期一個實施例揭露的元件可有利地併入其他實施例而不需特別詳述。
描繪提供優點於阻擋銅擴散之用於半導體元件中之互連結構與形成上述結構之方法。明確地說，將含金屬介電層應用作為互連結構中之覆蓋層以降低通過覆蓋層之電遷 移，藉此完成小臨界寸的更穩固互連。
第1圖是概述形成具有複數個層之互連結構的製程100之製程流程圖。第2A-2G圖是製程100之不同階段時之互連結構的橫剖面圖。方塊102，將基板200傳送進入沉積反應器的處理腔室。沉積反應器可為化學氣相沉積(CVD)腔室、電漿增強化學氣相沉積(PECVD)腔室、原子層沉積(ALD)腔室或物理氣相沉積(PVD)腔室或適合沉積低介電常數塊狀介電層210的其他腔室。基板200提供表面，表面上可形成有元件，利用形成於上方之互連結構而選擇性地連接元件。上述例子中，基板200可為半導體材料(諸如，矽、鍺或化合物半導體)、介電材料(諸如，玻璃、陶瓷或塑膠)或導電材料(諸如，鋁或另一金屬)。
方塊104，將低介電常數塊狀介電層210形成於基板200上。可沉積低介電常數塊狀介電層210達至少約1000Å的厚度。低介電常數塊狀介電層210由介電常數低於二氧化矽(或低於約4.0)的材料所形成，材料例如摻雜碳的氧化矽，例如自Applied Materials,Inc.(Santa Clara,Calif)取得的BLACK DIAMOND®低介電常數介電膜。適合用於形成BLACK DIAMOND®低介電常數介電膜之低介電常數塊狀介電層210的製程氣體可包括八甲基環四矽氧烷(OMCTS)、氦與氧。OMCTS的流率可為約2000sccm至約3500sccm，例如約2700sccm。氦的流率可為約600sccm至約1200sccm，例如約900sccm。氧的流率可為約100sccm至約200sccm，例如約160sccm。
在一個實施例中，PECVD製程被用來形成低介電常數塊狀介電層210，但可應用其他沉積方法。可在供應氣體混合物至處理腔室後，將提供至處理腔室以形成低介電常數塊狀介電層210的氣體混合物離子化成電漿。PECVD製程可利用高頻與低頻RF功率。可在約100瓦至約1500瓦的功率水平下以及約1MHz與約20MHz之間(例如，約13.56MHz)的頻率下提供高頻RF功率。可在約0瓦至約500瓦的功率水平下以及約200kHz與約1MHz之間(例如，約350kHz)的頻率下提供低頻RF功率。RF功率可為循環式或脈衝式且可為連續的或非連續的。低介電常數塊狀介電層210的沉積過程中，可將沉積反應器的處理腔室維持在約200℃與約650℃之間(例如，350℃)的溫度下以及約0.5托與20托(例如，5托)的壓力下。低介電常數塊狀介電層210的沉積過程中，噴頭與基板支撐基座之間的間距可在約200密耳與約1,000密耳之間(例如，350密耳)。
方塊106，將溝槽212形成於低介電常數塊狀介電層210中。可藉由圖案化低介電常數塊狀介電層210上之光阻劑層並利用適當的蝕刻製程來形成溝槽212。
方塊108，將襯裡層214形成於低介電常數塊狀介電層210上。襯裡層214亦共形地沉積至溝槽212。襯裡層214可被沉積成約0.5Å至約20Å的厚度。襯裡層214可為鉭、氮化鉭、釕或其他適當材料的層。在某些實施例中，ALD或PVD製程被用來形成襯裡層214，但可應用其他沉積方法。
方塊110，將銅層216形成於襯裡層214上。銅層 216填充溝槽212且可覆蓋低介電常數塊狀介電層210的一部分。可藉由任何適當的技術來沉積銅層216。舉例而言，可藉由利用ALD或PVD來形成銅晶種層以沉積銅層216的一部分，並接著藉由電鍍製程來形成銅層216的剩餘部分。
方塊112，移除銅層216與襯裡層214的部分以暴露低介電常數塊狀介電層210的上表面、襯裡層214的上表面與銅層216的上表面。可利用化學機械研磨來移除銅層216與襯裡層214的部分。在方塊112之後，低介電常數塊狀介電層210、襯裡層214與銅層216的上表面可實質上共面。
方塊114，將含金屬介電層218形成於低介電常數塊狀介電層210的上表面、襯裡層214的上表面與銅層216的上表面上。含金屬介電層218可為選自金屬氧化物、金屬氮化物與金屬氮氧化物所構成之群組的金屬介電化合物。
可應用作為含金屬介電層218之金屬氧化物的實例包括氧化鋁、氧化鋅、氧化鎂、氧化鎳、氧化鉿、氧化鋯、氧化鉭、氧化鈦、氧化銅、氧化鈰與上述之非化學當量形式或組合。可藉由利用ALD、CVD或PVD、旋塗技術或其他適當技術來沉積金屬氧化物。
在一個實施例中，氧化鋁被用作為含金屬介電層218。可透過藉由利用三甲基鋁(TMA)與水作為前驅物之ALD來形成氧化鋁層。或者，可藉由利用TMA與氧作為前驅物之電漿輔助製程來形成氧化鋁層。
在另一個實施例中，氧化鎂被用作為含金屬介電層218。可透過藉由利用二乙基鎂、雙(環戊二烯基)鎂或雙(乙基 環戊二烯基)鎂作為第一前驅物與水作為第二前驅物之ALD來形成氧化鎂層。
可被用作為含金屬介電層218之金屬氮化物的實例包括氮化鋁、氮化鈦與氮化鋯。在一個實施例中，氮化鋁被用作為含金屬介電層218。可透過藉由利用TMA與氨作為前驅物之電漿輔助ALD製程來形成氮化鋁層。
氮氧化鋁是可被用作為含金屬介電層218之示範性金屬氮氧化物。可利用TMA、氨與水作為前驅物來形成氮氧化鋁層。
含金屬介電層218的厚度可低於約20奈米(例如，約5奈米)。在某些實施例中，含金屬介電層218的厚度可在約0.5奈米與約1.0奈米之間(例如，約0.7奈米)。
在某些實施例中，介電常數低於12且介電強度在5 MV/公分與20 MV/公分之間的金屬介電化合物被用作為含金屬介電層218。具有上述介電常數與介電強度之組合的金屬介電化合物可在低於1奈米(例如，0.5奈米)的厚度下表現成銅互連的有效覆蓋層。
方塊116，將額外的低介電常數塊狀介電層220形成於含金屬介電層218上。可根據與參照形成低介電常數塊狀介電層210描述於上方之製程相似的製程來形成額外的低介電常數塊狀介電層220。
若基板200上需要額外的互連，那麼可如同決定操作118所述般重複形成溝槽212於低介電常數塊狀介電層210、形成襯裡層214於低介電常數塊狀介電層210上、形成 銅層216於襯裡層214上並填充溝槽212、移除銅層216與襯裡層214的部分以暴露低介電常數塊狀介電層210的上表面、襯裡層214的上表面與銅層216的上表面、形成含金屬介電層218於低介電常數塊狀介電層210的上表面、襯裡層214的上表面與銅層216的上表面上、並形成額外的低介電常數塊狀介電層220於含金屬介電層218上的製程。可藉由重複製程任何期望次數來提供任何數目的互連。
雖然上文針對本發明之實施例，但可設計出本發明的其他與進一步實施例而不悖離本發明之基本範圍，本發明之範圍由後續之申請專利範圍所確定。
100‧‧‧製程
102、104、106、108、110、112、114、116‧‧‧方塊
118‧‧‧決定操作

Claims (20)

  1. 一種形成一互連結構的方法，該方法包括以下步驟：(a)形成一低介電常數塊狀介電層於一基板上；(b)形成一溝槽於該低介電常數塊狀介電層中；(c)形成一襯裡層於該低介電常數塊狀介電層上，該襯裡層共形地沉積至該溝槽；(d)形成一銅層於該襯裡層上，其中該銅層填充該溝槽；(e)移除該銅層與該襯裡層的數個部分，以暴露該低介電常數塊狀介電層的一上表面、該襯裡層的一上表面與該銅層的一上表面；及(f)形成一含金屬介電層於該低介電常數塊狀介電層之該上表面、該襯裡層之該上表面與該銅層之該上表面上，其中該含金屬介電層係一選自由氮化鋁、氮化鈦及氮化鋯所構成之一群組的金屬化合物，其中該含金屬介電層係一介電常數低於12且一介電強度大於8MV/公分的一材料。
  2. 如請求項1所述之方法，更包括以下步驟：(g)形成一第二低介電常數塊狀介電層於該含金屬介電層上；及(h)重複步驟(b)至(f)。
  3. 如請求項1所述之方法，其中該含金屬介電層的一厚度係20奈米或更低。
  4. 如請求項1所述之方法，其中該含金屬介電層的一厚度係5奈米或更低。
  5. 如請求項1所述之方法，其中該含金屬介電層的一厚度係在約0.5奈米至約1奈米的範圍中。
  6. 如請求項1所述之方法，其中該含金屬介電層係氮化鈦。
  7. 如請求項1所述之方法，其中該含金屬介電層係氮化鋯。
  8. 如請求項1所述之方法，其中該含金屬介電層係氮化鋁。
  9. 如請求項6所述之方法，其中該含金屬介電層的一厚度係在約0.5奈米至約1奈米的範圍中。
  10. 一種半導體互連結構，包括：一基板；一低介電常數塊狀介電層，該低介電常數塊狀介電層具有一溝槽形成於該低介電常數塊狀介電層中；一襯裡層，該襯裡層共形地沉積於該低介電常數塊狀介電層上且在該溝槽之中；一銅層，該銅層配置於該襯裡層上且填充該溝槽；及一含金屬介電層，該含金屬介電層具有一底面，該底面接觸該低介電常數塊狀介電層、該襯裡層與該銅層，其中該 含金屬介電層係一選自由氮化鋁、氮化鈦及氮化鋯所構成之一群組的金屬化合物，其中該含金屬介電層係一介電常數低於12且一介電強度大於8MV/公分的一材料。
  11. 如請求項10所述之結構，更包括：一第二低介電常數塊狀介電層，該第二低介電常數塊狀介電層具有一溝槽形成於該第二低介電常數塊狀介電層中；一第二襯裡層，該第二襯裡層共形地沉積於該第二低介電常數塊狀介電層上且在該溝槽之中；一第二銅層，該第二銅層配置於該第二襯裡層上且填充形成於該第二低介電常數塊狀介電層中之該溝槽；及一第二含金屬介電層，該第二含金屬介電層具有一底面，該底面接觸該第二低介電常數塊狀介電層、該第二襯裡層與該第二銅層，其中該第二含金屬介電層係一選自由氮化鋁、氮化鈦及氮化鋯所構成之一群組的金屬化合物。
  12. 如請求項10所述之結構，其中該含金屬介電層的一厚度係20奈米或更低。
  13. 如請求項10所述之結構，其中該含金屬介電層的一厚度係5奈米或更低。
  14. 如請求項10所述之結構，其中該含金屬介電層的一厚度係在約0.5奈米至約1奈米的範圍中。
  15. 如請求項10所述之結構，其中該含金屬介電層係氮化鈦。
  16. 如請求項15所述之結構，其中該含金屬介電層的一厚度係5奈米或更低。
  17. 如請求項15所述之結構，其中該含金屬介電層的一厚度係在約0.5奈米至約1奈米的範圍中。
  18. 如請求項10所述之結構，其中該含金屬介電層係氮化鋁。
  19. 如請求項10所述之結構，其中該含金屬介電層係氮化鋯。
  20. 一種半導體互連結構，包括：一基板；一低介電常數塊狀介電層，該低介電常數塊狀介電層具有一溝槽形成於該低介電常數塊狀介電層中；一襯裡層，該襯裡層共形地沉積於該低介電常數塊狀介電層上且在該溝槽之中；一銅層，該銅層配置於該襯裡層上且填充該溝槽；及一含金屬介電層，該含金屬介電層具有一底面，該底面接觸該低介電常數塊狀介電層、該襯裡層與該銅層，其中該含金屬介電層包括氮化鋯，其中該含金屬介電層係一介電常數低於12且一介電強度大於8MV/公分的一材料。
TW103142212A 2013-12-20 2014-12-04 作爲先進互連之介電覆蓋障壁的含金屬膜 TWI594370B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201361918973P 2013-12-20 2013-12-20
US14/268,727 US9368448B2 (en) 2013-12-20 2014-05-02 Metal-containing films as dielectric capping barrier for advanced interconnects

Publications (2)

Publication Number Publication Date
TW201528430A TW201528430A (zh) 2015-07-16
TWI594370B true TWI594370B (zh) 2017-08-01

Family

ID=53400883

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103142212A TWI594370B (zh) 2013-12-20 2014-12-04 作爲先進互連之介電覆蓋障壁的含金屬膜

Country Status (5)

Country Link
US (1) US9368448B2 (zh)
KR (1) KR101767538B1 (zh)
CN (1) CN105830210B (zh)
TW (1) TWI594370B (zh)
WO (1) WO2015094606A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9806018B1 (en) * 2016-06-20 2017-10-31 International Business Machines Corporation Copper interconnect structures
US10858727B2 (en) 2016-08-19 2020-12-08 Applied Materials, Inc. High density, low stress amorphous carbon film, and process and equipment for its deposition
CN109273402B (zh) * 2018-09-13 2020-08-25 德淮半导体有限公司 金属阻挡层的制作方法、金属互连结构及其制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW479340B (en) * 1999-09-01 2002-03-11 Ibm Copper conductive line with redundant liner
US20050186801A1 (en) * 1999-06-24 2005-08-25 Shouochi Uno Method of manufacture of semiconductor integrated circuit
US20080280432A1 (en) * 2004-12-01 2008-11-13 Chung-Liang Chang Barrier Material and Process for Cu Interconnect
US20090137111A1 (en) * 2007-11-26 2009-05-28 Jeong-Ho Lee Method of fabricating metal interconnection and method of fabricating image sensor using the same
TW201117321A (en) * 2009-06-03 2011-05-16 Novellus Systems Inc Interfacial capping layers for interconnects
TW201138024A (en) * 2010-01-15 2011-11-01 Novellus Systems Inc Interfacial layers for electromigration resistance improvement in damascene interconnects

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100390951B1 (ko) * 1999-12-29 2003-07-10 주식회사 하이닉스반도체 반도체 소자의 구리 배선 형성 방법
TW478101B (en) * 2000-03-23 2002-03-01 Ibm Structure for protecting copper interconnects in low dielectric constant materials from oxidation
US6620721B1 (en) * 2002-06-04 2003-09-16 United Microelectronics Corp. Method of forming a self-aligning pad
EP1887624A4 (en) * 2005-06-02 2010-07-28 Fujitsu Semiconductor Ltd SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
US20070099417A1 (en) 2005-10-28 2007-05-03 Applied Materials, Inc. Adhesion and minimizing oxidation on electroless CO alloy films for integration with low K inter-metal dielectric and etch stop
US20080124924A1 (en) 2006-07-18 2008-05-29 Applied Materials, Inc. Scheme for copper filling in vias and trenches
US7618889B2 (en) 2006-07-18 2009-11-17 Applied Materials, Inc. Dual damascene fabrication with low k materials
US7749879B2 (en) 2006-08-03 2010-07-06 Micron Technology, Inc. ALD of silicon films on germanium
US9087877B2 (en) 2006-10-24 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Low-k interconnect structures with reduced RC delay
US7745282B2 (en) * 2007-02-16 2010-06-29 International Business Machines Corporation Interconnect structure with bi-layer metal cap
CN102054756A (zh) * 2009-11-10 2011-05-11 中芯国际集成电路制造(上海)有限公司 铜互连结构及其形成方法
US8993435B2 (en) 2010-03-15 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Low-k Cu barriers in damascene interconnect structures
US8314033B2 (en) 2010-09-24 2012-11-20 Applied Materials, Inc. Method of patterning a low-k dielectric film
US8492880B2 (en) 2011-04-01 2013-07-23 International Business Machines Corporation Multilayered low k cap with conformal gap fill and UV stable compressive stress properties
US8871650B2 (en) 2011-10-28 2014-10-28 Applied Materials, Inc. Post etch treatment (PET) of a low-K dielectric film

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050186801A1 (en) * 1999-06-24 2005-08-25 Shouochi Uno Method of manufacture of semiconductor integrated circuit
TW479340B (en) * 1999-09-01 2002-03-11 Ibm Copper conductive line with redundant liner
US20080280432A1 (en) * 2004-12-01 2008-11-13 Chung-Liang Chang Barrier Material and Process for Cu Interconnect
US20090137111A1 (en) * 2007-11-26 2009-05-28 Jeong-Ho Lee Method of fabricating metal interconnection and method of fabricating image sensor using the same
TW201117321A (en) * 2009-06-03 2011-05-16 Novellus Systems Inc Interfacial capping layers for interconnects
TW201138024A (en) * 2010-01-15 2011-11-01 Novellus Systems Inc Interfacial layers for electromigration resistance improvement in damascene interconnects

Also Published As

Publication number Publication date
TW201528430A (zh) 2015-07-16
WO2015094606A1 (en) 2015-06-25
KR101767538B1 (ko) 2017-08-11
CN105830210B (zh) 2019-07-16
WO2015094606A9 (en) 2015-08-13
KR20160098502A (ko) 2016-08-18
US20150179581A1 (en) 2015-06-25
CN105830210A (zh) 2016-08-03
US9368448B2 (en) 2016-06-14

Similar Documents

Publication Publication Date Title
US10096516B1 (en) Method of forming a barrier layer for through via applications
TWI603429B (zh) 形成具有氣隙之半導體元件的方法
TWI636501B (zh) 使用水蒸氣處理將材料層從基材移除的方法
TWI550765B (zh) 半導體結構及其形成方法
US20090093100A1 (en) Method for forming an air gap in multilevel interconnect structure
KR20160063378A (ko) 심리스 코발트 갭-충전을 가능하게 하는 방법
TW201117321A (en) Interfacial capping layers for interconnects
CN105336680B (zh) 一种半导体器件及其制作方法和电子装置
US11942362B2 (en) Surface modification layer for conductive feature formation
US9184093B2 (en) Integrated cluster to enable next generation interconnect
TWI594370B (zh) 作爲先進互連之介電覆蓋障壁的含金屬膜
JP2010199349A (ja) 半導体装置の製造方法
US9449872B1 (en) Method for forming cobalt barrier layer and metal interconnection process
US7732304B2 (en) Method of manufacturing semiconductor device
KR20220166338A (ko) 유전체 재료 충전 및 처리 방법들
TW202111870A (zh) 用於混成特徵金屬化之方法與設備
US10950500B2 (en) Methods and apparatus for filling a feature disposed in a substrate
KR20070042887A (ko) 피쳐 제한부들을 형성하는 방법
JP2005129937A (ja) 低ｋ集積回路相互接続構造
JP2006024668A (ja) 半導体装置の製造方法
CN108695237B (zh) 一种半导体器件及其制作方法
KR100587600B1 (ko) 듀얼 다마신 공정을 이용한 금속배선 형성방법
JP2023057062A (ja) 傾斜酸化を用いたシームレスな間隙充填のための方法
CN114946018A (zh) 在低温下的选择性钨沉积
TW202348825A (zh) 用於選擇性金屬沉積的選擇性抑制