CN105830210A - 作为用于先进互连的介电封顶阻挡层的含金属膜 - Google Patents

作为用于先进互连的介电封顶阻挡层的含金属膜 Download PDF

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CN105830210A
CN105830210A CN201480069735.8A CN201480069735A CN105830210A CN 105830210 A CN105830210 A CN 105830210A CN 201480069735 A CN201480069735 A CN 201480069735A CN 105830210 A CN105830210 A CN 105830210A
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dielectric layer
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copper
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CN105830210B (zh
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陈宏�
陈一宏
A·B·玛里克
M·B·奈克
S·D·耐马尼
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Abstract

提供一种形成用于半导体器件中的互连结构的方法。该方法开始于将低k块状介电层形成在基板上并接着在低k块状介电层中形成沟槽。在低k块状介电层上形成衬里层，该衬里层共形地沉积到该沟槽。在衬里层上形成铜层，该铜层填充沟槽。移除铜层与衬里层的部分以形成低k块状介电层、衬里层与铜层的上表面。在低k块状介电层、衬里层与铜层的上表面上形成含金属介电层。

Description

作为用于先进互连的介电封顶阻挡层的含金属膜
技术领域
本发明的各方面总体上涉及用于半导体器件中的互连结构与用于形成这种结构的方法。
背景技术
自从180纳米CMOS技术节点以来，由于铜互连的高互连传导性与电迁移抗性，铜互连已经变成产业标准。然而，与其他过渡金属相比，铜在硅基材料中具有较高的扩散率。在器件操作器件，铜原子快速扩散到周围的二氧化硅或其他低k介电材料中创建短路路径，短路路径劣化介电层并造成器件故障。因此，介电可靠性变成铜互连结构中的主要担忧之一。目前的解决方案是将铜互连嵌入氮化钽或钽侧壁阻挡层中并且利用含硅介电封顶层(诸如，氮化硅或碳化硅)来封装铜互连。由于电迁移的常见故障机制通过封顶层，封顶层的性质特别重要。
使封顶层更厚来避免电迁移不是有效的解决方案，因为在金属化层叠中封顶层的介电常数最高，这强力地削弱互连级的有效介电常数。因此，必须最小化封顶层的厚度，同时仍维持有效的扩散阻挡特征以及与邻接层的良好粘合强度。
半导体器件的制造商不断地追求较低成本下的具有增加的容量的较小几何结构。因此，也必须降低互连结构与其相应封顶层的尺寸。因为难以在小于20纳米的厚度下确保必要的扩散阻挡特征，含硅介电封顶层(诸如，氮化硅或碳化硅层)的厚度已经被限制到约20纳米。已经提出替代方案，诸如在铜与含硅介电封顶层之间使用选择性的金属封顶阻挡层或铜氮化硅缓冲层。然而，这种方案是不期望的，由于互连抗性的增加，这会降低器件性能。
因此，存在对改善的互连结构与形成这种结构的方法的需求。
发明内容
在一个实施例中，提供一种形成用于半导体器件中的互连结构的方法。该方法包括：在基板上形成低k块状介电层；在低k块状介电层中形成沟槽；在低k块状介电层上形成衬里层，衬里层共形地沉积至沟槽；在衬里层上形成铜层，其中铜层填充沟槽；移除铜层与衬里层的部分以暴露低k块状介电层的上表面、衬里层的上表面与铜层的上表面；以及在低k块状介电层的上表面、衬里层的上表面与铜层的上表面上形成含金属介电层，其中含金属介电层是选自由金属氧化物、金属氮化物与金属氮氧化物所构成的组的金属化合物。
在另一个实施例中，提供一种半导体互连结构。该互连结构包括基板；低k块状介电层，具有形成在该低k块状介电层中的沟槽；衬里层，共形地沉积在沟槽内的低k块状介电层上；铜层，设置在衬里层上且填充沟槽；以及含金属介电层，具有接触低k块状介电层、衬里层与铜层的底面，其中含金属介电层是选自由金属氧化物、金属氮化物与金属氮氧化物所构成的组的金属化合物。
附图说明
因此，为了可详细理解本发明的上述特征的方式，可通过参照实施例对上文中简短概述的本发明进行更特定的描述，这些实施例中的一些实施例在附图中示出。然而，需注意，附图仅描绘本发明的典型实施例，因此附图不被视为对本发明的范围的限制，因为本发明可接纳其他等效实施例。
图1是形成互连结构的工艺的工艺流程图。
图2A-2G描绘图1的工艺的不同阶段的互连结构。
为了促进理解，已经尽可能应用相同的附图标记指定附图所共有的相同元件。构想了在一个实施例中公开的元件可有益地并入其他实施例而不需特别详述。
具体实施方式
描述了提供阻挡铜扩散中的优势的用于半导体器件中的互连结构与形成这种结构的方法。具体地，采用含金属介电层作为互连结构中的封顶层以降低通过封顶层的电迁移，由此实现小临界寸的更稳固互连。
图1是概述用于形成具有多个层的互连结构的工艺100的工艺流程图。图2A–2G是工艺100的不同阶段时的互连结构的横剖面图。在框102处，将基板200传送到沉积反应器的处理腔室中。沉积反应器可以是化学气相沉积(CVD)腔室、等离子体增强化学气相沉积(PECVD)腔室、原子层沉积(ALD)腔室或物理气相沉积(PVD)腔室或适合用于沉积低k块状介电层210的其他腔室。基板200提供表面，在该表面上可形成器件，利用形成于上方的互连结构来选择性地连接器件。如此，基板200可以是半导体材料(诸如，硅、锗或化合物半导体)、介电材料(诸如，玻璃、陶瓷或塑料)或导电材料(诸如，铝或另一金属)。
在框104处，将低k块状介电层210形成在基板200上。可沉积低k块状介电层210达至少约的厚度。低k块状介电层210由介电常数小于二氧化硅(或小于约4.0)的材料形成，材料诸如掺杂碳的氧化硅，例如可从位于加利福尼亚州的圣克拉拉市的应用材料有限公司购买到的BLACK低k介电膜。适合用于形成BLACK低k介电膜的低k块状介电层210的工艺气体可包括八甲基环四硅氧烷(OMCTS)、氦与氧。OMCTS的流率可以是约2000sccm至约3500sccm，例如约2700sccm。氦的流率可以是约600sccm至约1200sccm，例如约900sccm。氧的流率可以是约100sccm至约200sccm，例如约160sccm。
在一个实施例中，PECVD工艺被用来形成低k块状介电层210，但可使用其他沉积方法。可在气体混合物被供应到处理腔室后，将提供至处理腔室以形成低k块状介电层210的气体混合物电离成等离子体。PECVD工艺可使用高频与低频RF功率。可以以约100瓦至约1500瓦的功率水平、以约1MHz与约20MHz之间(例如，约13.56MHz)的频率提供高频RF功率。可以以约0瓦至约500瓦的功率水平、以约200kHz与约1MHz之间(例如，约350kHz)的频率提供低频RF功率。RF功率可以是循环式或脉冲式且可以是连续的或非连续的。在低k块状介电层210的沉积期间，可将沉积反应器的处理腔室维持在约200℃与约650℃之间(例如，350℃)的温度下以及约0.5托与20托(例如，5托)的压力下。在低k块状介电层210的沉积期间，喷淋头与基板支撑基座之间的间距可在约200密耳与约1,000密耳之间(例如，350密耳)。
在框106处，将沟槽212形成在低k块状介电层210中。可通过图案化低k块状介电层210上的光刻胶层并使用适当的蚀刻工艺来形成沟槽212。
在框108处，将衬里层214形成在低k块状介电层210上。衬里层214还共形地沉积至沟槽212。衬里层214可被沉积到约至约的厚度。衬里层214可以是钽、氮化钽、钌或其他适当材料的层。在某些实施例中，ALD或PVD工艺被用来形成衬里层214，但可使用其他沉积方法。
在框110处，将铜层216形成在衬里层214上。铜层216填充沟槽212且可覆盖低k块状介电层210的一部分。可通过任何适当的技术来沉积铜层216。例如，可通过使用ALD或PVD来沉积铜层216的一部分以形成铜晶层，并接着通过电镀工艺来形成铜层216的剩余部分。
在框112处，移除铜层216与衬里层214的部分以暴露低k块状介电层210的上表面、衬里层214的上表面与铜层216的上表面。可使用化学机械研磨来移除铜层216与衬里层214的部分。在框112之后，低k块状介电层210、衬里层214与铜层216的上表面可基本上共面。
在框114处，将含金属介电层218形成在低k块状介电层210的上表面、衬里层214的上表面与铜层216的上表面上。含金属介电层218可以是选自由金属氧化物、金属氮化物与金属氮氧化物所构成的组的金属介电化合物。
可用作含金属介电层218的金属氧化物的示例包括氧化铝、氧化锌、氧化镁、氧化镍、氧化铪、氧化锆、氧化钽、氧化钛、氧化铜、氧化铈与上述的非化学计量的形式或组合。可通过使用ALD、CVD或PVD、旋涂(spin-on)技术或其他适当技术来沉积金属氧化物。
在一个实施例中，氧化铝被用作含金属介电层218。可通过将三甲基铝(TMA)与水用作前体来通过ALD形成氧化铝层。或者，可通过使用TMA与氧作为前体来使用等离子体增强工艺来形成氧化铝层。
在另一个实施例中，氧化镁被用作为含金属介电层218。可通过将二乙基镁、双(环戊二烯基)镁或双(乙基环戊二烯基)镁用作第一前体以及将水用作第二前体的ALD来形成氧化镁层。
可被用作为含金属介电层218的金属氮化物的示例包括氮化铝、氮化钛与氮化锆。在一个实施例中，氮化铝被用作为含金属介电层218。可通过将TMA与氨用作前体的等离子体增强ALD工艺来形成氮化铝层。
氮氧化铝是可被用于含金属介电层218的示例性金属氮氧化物。可将TMA、氨与水用作前体来形成氮氧化铝层。
含金属介电层218的厚度可小于约20纳米(例如，约5纳米)。在某些实施例中，含金属介电层218的厚度可在约0.5纳米与约1.0纳米之间(例如，约0.7纳米)。
在某些实施例中，具有小于12的介电常数以及在5MV/厘米与20MV/厘米之间的介电强度的金属介电化合物被用作含金属介电层218。具有这种介电常数与介电强度的组合的金属介电化合物可用作用于小于1纳米(例如，0.5纳米)的厚度的铜互连的有效封顶层。
在框116处，将附加的低k块状介电层220形成在含金属介电层218上。可根据与参照形成低k块状介电层210在上文描述的工艺相似的工艺来形成附加的低k块状介电层220。
若在基板200上需要附加的互连，那么可如决定操作118所述，重复以下工艺：将沟槽212形成在低k块状介电层210中；将衬里层214形成在低k块状介电层210上；将铜层216形成在衬里层214上并填充沟槽212；移除铜层216与衬里层214的部分以暴露低k块状介电层210的上表面、衬里层214的上表面与铜层216的上表面；将含金属介电层218形成在低k块状介电层210的上表面、衬里层214的上表面与铜层216的上表面上；以及将附加的低k块状介电层220形成在含金属介电层218上。可通过使工艺重复任何期望的次数来提供任何数目的互连。
虽然上文针对本发明的实施例，但可设计出本发明的其他与进一步实施例而不背离本发明的基本范围，且本发明的范围由所附权利要求书来确定。

Claims (15)

1.一种用于形成互连结构的方法，所述方法包括以下步骤：
(a)将低k块状介电层形成在基板上；
(b)将沟槽形成在所述低k块状介电层中；
(c)将衬里层形成在所述低k块状介电层上，所述衬里层共形地沉积至所述沟槽；
(d)将铜层形成在所述衬里层上，其中所述铜层填充所述沟槽；
(e)移除所述铜层与所述衬里层的数个部分以暴露所述低k块状介电层的上表面、所述衬里层的上表面与所述铜层的上表面；以及
(f)将含金属介电层形成在所述低k块状介电层的上表面、所述衬里层的上表面与所述铜层的上表面上，其中所述含金属介电层是选自由金属氧化物、金属氮化物与金属氮氧化物所构成的组的金属化合物。
2.如权利要求1所述的方法，进一步包括以下步骤：
(g)将第二低k块状介电层形成在所述含金属介电层上；以及
(h)重复步骤(b)至(f)。
3.如权利要求1所述的方法，其中所述含金属介电层是具有小于12的介电常数以及大于8MV/厘米的介电强度的材料。
4.如权利要求1所述的方法，其中所述含金属介电层的厚度是20纳米或更小。
5.如权利要求1所述的方法，其中所述含金属介电层的厚度在约0.5纳米至约1纳米的范围中。
6.如权利要求1所述的方法，其中所述含金属介电层是选自由氧化铝、氧化镁、氮化铝与氮氧化铝所构成的组的材料。
7.如权利要求1所述的方法，其中所述含金属介电层是氧化铝。
8.如权利要求6所述的方法，其中所述含金属介电层的厚度在约0.5纳米至约1纳米的范围中。
9.一种半导体互连结构，包括：
基板；
低k块状介电层，所述低k块状介电层具有沟槽，所述沟槽形成在所述低k块状介电层中；
衬里层，所述衬里层共形地沉积所述低k块状介电层上且在所述沟槽内；
铜层，所述铜层设置在所述衬里层上且填充所述沟槽；以及
含金属介电层，所述含金属介电层具有接触所述低k块状介电层、所述衬里层与所述铜层的底面，其中所述含金属介电层是选自由金属氧化物、金属氮化物与金属氮氧化物所构成的组的金属化合物。
10.如权利要求9所述的结构，进一步包括：
第二低k块状介电层，所述第二低k块状介电层具有沟槽，所述沟槽形成在所述第二低k块状介电层中；
第二衬里层，所述第二衬里层共形地沉积在所述第二低k块状介电层上且在所述沟槽内；
第二铜层，所述第二铜层设置在所述第二衬里层上且填充形成在所述第二低k块状介电层中的沟槽；以及
第二含金属介电层，所述第二含金属介电层具有接触所述第二低k块状介电层、所述第二衬里层与所述第二铜层的底面，其中所述第二含金属介电层是选自由金属氧化物、金属氮化物与金属氮氧化物所构成的组的金属化合物。
11.如权利要求9所述的结构，其中所述含金属介电层是具有小于12的介电常数以及大于8MV/厘米的介电强度的材料。
12.如权利要求9所述的结构，其中所述含金属介电层的厚度是20纳米或更小。
13.如权利要求9所述的结构，其中所述含金属介电层的厚度在约0.5纳米至约1纳米的范围中。
14.如权利要求9所述的结构，其中所述含金属介电层是选自由氧化铝、氧化镁、氮化铝与氮氧化铝所构成的组的材料。
15.如权利要求14所述的结构，其中所述含金属介电层的厚度在约0.5纳米至约1纳米的范围中。
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