TW478101B - Structure for protecting copper interconnects in low dielectric constant materials from oxidation - Google Patents

Structure for protecting copper interconnects in low dielectric constant materials from oxidation Download PDF

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Publication number
TW478101B
TW478101B TW089128210A TW89128210A TW478101B TW 478101 B TW478101 B TW 478101B TW 089128210 A TW089128210 A TW 089128210A TW 89128210 A TW89128210 A TW 89128210A TW 478101 B TW478101 B TW 478101B
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patent application
copper
scope
oxygen
layer
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TW089128210A
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Chinese (zh)
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Vincent J Mcgahay
Ernest N Levine
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Ibm
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A diffusion barrier of dense material for protecting a copper structure from oxidation in the presence of oxygen or water in an integrated circuit but subject to defects such as pinholes is repaired in-situ by oxidation of a material capable of forming a protective oxide in a self-limiting manner which is placed in contact with the dense material, preferably as a film. This provision of protection for copper structures allows the high conductivity of copper to be exploited in combination with low dielectric constant (low K) materials, that are now recognized to support diffusion of oxygen and water, to enhance signal propagation speed.

Description

案號 89128210 # 年/>月；^日 修正 五、發明說明（1) 發明背景 發明範圍 本發明大致有關積體電路裝置，更特別的是，有關使用 銅互連與低介電係數（低Κπ )絕緣體二者之積體電路裝 置。 先前技藝敘述 已知在性能、機能度與製造經濟性上之益處，提供了提 高積體電路裝置積合密度的強烈動機。雖然，提高之製造 經濟性與機能度係出自裝置數量增加，其中該裝置數量增 加係在既定材料處理製程（例如平版印刷、蝕刻、澱積、 植入等）中形成，但是當以更大物理近接性放置開關元件 時，可由減少之訊號傳播時間（及，通常稱為雜訊免除性） 得到經提高性能。雖然降低電容通常會導致導體間之電容 藕合雜訊減少，但是互連長度較短通常可以減少該連接之 電阻與電容二者，並產生更快之訊號轉移上升與下降時 間。 然而，雖然互連之近接性提高可能增加其間之電容，但 是訊號轉移速率提高亦會增加可能在導體間電容藕合之雜 訊量。因此，在本技藝目前狀態下，研究顯示低介電常數 (例如Κ = 3 · 0或以下）之介電體，以最小化介於具有既定 尺寸與間隔之導體之間的電容。同時，已發現與供互連用 之導電性較低材料相較，銅可以提供明顯的性能·優點，其 與某些其他材料（諸如銀與金）比較時，提供顯著經濟優 勢，而且不會造成某些耐火性金屬所示之製程複雜度。銅Case No. 89128210 # year / >month; ^ day amendment V. Description of the invention (1) Background of the invention The present invention relates generally to integrated circuit devices, and more particularly, to the use of copper interconnects and low dielectric constant (low (Kπ) integrated circuit device of both insulators. Prior art descriptions Known benefits in performance, functionality, and manufacturing economy provide a strong incentive to increase the integrated density of integrated circuit devices. Although the increased manufacturing economy and performance are due to the increase in the number of devices, which is formed in a given material processing process (such as lithography, etching, deposition, implantation, etc.), but with greater physical Improved performance can be obtained by reducing the signal propagation time (and often referred to as noise immunity) when switching elements are placed in close proximity. Although lowering the capacitance usually results in a reduction in the capacitive coupling noise between the conductors, a shorter interconnect length usually reduces both the resistance and the capacitance of the connection and produces faster signal transfer rise and fall times. However, although the increased proximity of the interconnect may increase the capacitance between them, the increase in signal transfer rate also increases the amount of noise that may be combined between the capacitances of the conductors. Therefore, in the current state of the art, studies have shown dielectrics with low dielectric constants (eg, K = 3 · 0 or less) to minimize capacitance between conductors with a given size and spacing. At the same time, it has been found that copper can provide significant performance and advantages compared to less conductive materials for interconnects, and it offers significant economic advantages when compared to certain other materials, such as silver and gold, without Causes the process complexity shown by some refractory metals. copper

O:\67\67895.ptc 第5頁 478101 五、發明說明（2) 亦比某些其他金屬不容易產 名的為鋁。 產生至屬遷移，此等金屬中最著 化物：成因：：：：H:經常包括氧化物或主要由氧 即使”構在氧之故， =:二者，雖”通常與===== 彼擴散。因此，習用構121ί但疋乳或水仍可能經由 失六丈可处+ k積體電路中，因為銅氧化所致之 此：但：在：Ϊ低!!習用晶片之計劃使用期限。雖然如 連之寬度血厚二可預知之積合密度下’因為銅互 更危險。度大】更小，所以預料此種氧化作用實質上 :常結構中形成細微低電阻互連，該層狀 黏合層(例如纽或氮化组）、-銅層以及- 二re”/保護層：然而，此種密封/保護層若由 明顯。已知而：；使=形成土：導體之製程複雜度相當 分緻密材料（諸如组〆、他緻拉障礙材料膜，但是因為充 針孔瑕疵的傾\ 、Ρ或虱化鈕）具有形成足使氧或水擴散之 Ψ^傾向，很難確定此種膜沒有瑕疵。 形成最小障礙會消耗有限空f[而且若橫向尺寸 此點，另外已貝r能迫使積合密度產生限制。關於 中該晶片係自一 用通常最容易自晶片邊緣發生，其 該晶片中所有芦=切成’而且除非提供邊緣密封，否則 β間界面均露出，然而該邊緣密封又涉及實 第6頁 478101O: \ 67 \ 67895.ptc Page 5 478101 V. Description of the invention (2) Aluminum, which is also less prone to produce than some other metals. The most common compounds in these metals are: cause :::: H: often includes oxides or is mainly composed of oxygen, even if "structured in oxygen, =: both, although" is usually ===== That spread. Therefore, the conventional structure 121, but milk or water may still be in the + k integrated circuit through loss of six feet, because of copper oxidation. This: But: In: Low! The planned life of conventional wafers. Although even the width of the blood is thick and the predictable cumulative density is lower, because copper is more dangerous. Degree] is smaller, so it is expected that this oxidation is essentially: a fine low-resistance interconnection is formed in the normal structure, the layered adhesive layer (such as a button or nitride group), -copper layer, and -re "/ protective layer : However, if this kind of seal / protective layer is obvious. Known and :; make = form soil: the process complexity of the conductor is quite dense of the dense material (such as the film of the group, other pulling barrier material film, but due to pinhole defects It has a tendency to form enough to diffuse oxygen or water, and it is difficult to determine that the membrane is not defective. The formation of the smallest obstacle will consume finite space f [and if the horizontal dimension is this point, and Be can force a limit on the accumulated density. With regard to the wafer, it is usually the easiest to occur from the edge of the wafer. All the wafers in the wafer are cut into 'and unless the edge seal is provided, the β interface is exposed. However, This edge seal in turn involves the actual page 6 478101

478101 五、發明說明（4) 為了完成此等與其他本發明目的，提出一種半導體誓 置，包括一層絕緣層、一銅結構與一介於該絕緣層與該銅 包括一層緻密材料，以及一層 或水之下，以自調方式形成保 結構間 材料膜 護性氧 根據 方法， 一個銅 在氧或 及形成 化物之 間。 根據 裝置内 礙接觸 材料。 擴散障礙，其 料可於存在氧 之複合 ，該材 化物。 本發明其他實施樣態 其包括形成一個複合 主體，一層緻密材料 水之下，以自調方式 一個絕緣體之另外步 材料層置於該絕緣體 本發明 擴散障 下，氧 另外實施樣態 礙之方法，其 化於存在氧或 ，提出一種製造半導體裝置之 導體之步驟，該複合導體包括 之擴散障層，以及一層可於存 形成保護性氧化物之材料；以 驟’其中將該可形成保護性氧 與該銅主體以及該擴散障礙之 ，提出一種在原位修補半導體 包括以自調方式並與該擴散障 水之下可形成保護性氧化物之 將：ί之本發明較佳具體實确，並參考唯-圖式， 月暸刖述與其他目的、實施樣態以及優點， 本二ΪΪΙ體體結構之橫剖面0，其取自-個 子又佳具體3例之導體連接。 本發明較佳具體實例詳述 L 本發明一範例具體實例。因為本發明之較佳應 圖現ί ί:該圖式’其中-個積體電路-部分之橫剖面478101 V. Description of the invention (4) In order to accomplish these and other purposes of the present invention, a semiconductor device is proposed, including an insulating layer, a copper structure, and a layer of dense material between the insulating layer and the copper, and a layer or water Below, a protective film is formed in a self-adjusting manner to protect the oxygen of the material. According to the method, a copper is between the oxygen and the formed compound. Contact the material according to the internal obstacle of the device. Diffusion barrier, the material can be in the presence of oxygen, the material. Other embodiments of the present invention include forming a composite body, a layer of dense material under water, another layer of an insulator in a self-adjusting manner under the insulator of the present invention, and a method of impeding oxygen, It is based on the presence of oxygen or a step for manufacturing a semiconductor device conductor. The composite conductor includes a diffusion barrier layer and a layer of a material that can form a protective oxide in order to form a protective oxygen. With the copper body and the diffusion barrier, a method for repairing semiconductors in situ including forming a protective oxide in a self-adjusting manner and under the diffusion barrier water is proposed: With reference to the Wei-schema, the description and other purposes, implementation styles, and advantages, the cross section 0 of the body structure of this article is taken from the conductor connection of a good and specific 3 cases. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION L An exemplary embodiment of the present invention. Because the better application of the present invention is shown in the drawing: a cross-section of the scheme, of which a integrated circuit

478101 五、發明說明（5) 用係保護銅導體與包括線和拽 僅顯示具有一連接通路夕τ路之互連避免於氧化，所以 以使熟知本技藝者暸解並同：1的導體，而且發現此足 =以表面上形成之導體，並覆蓋= 此外，Λ形成金屬鑲喪導體。 鍺等介電體相t ^ /、諸如氧化矽、氮化矽、氮化 料’諸如有機聚合物與孔狀絕(緣=二κ:乂·°或以下)材 散作用差之障礙。自具有錮、2體通吊係抗氧及/或水擴 發生鋼氧化作用，其中=之晶圓切下之晶片極容易 確定此等障礙沒有瑕疲以、及：『材料/=。因為很難 ”針孔，1，所以即栋括祝毛避免使虱及/或水通過之 化鈕），仍麸存在針' /緻密金屬障礙（諸如鈕及/或氮 密障礙之材;二开2 示出此等氧化物或其他化合物;，但是其並未顯 任何針孔與其他瑕疲的性質物…以有效阻塞所產生之 因此，本發明在銅結構（哎舜 層為佳）與-絕緣體（諸如一:亥銅結構之緻密障 層。該額外障#传ώ ^ ^ , 一材料）之間提供一額外障 料製得，、ΐ=:Γ可生長自調保護氧化物之材 如就金屬鑲嵌導體而士、#，μμ β /陬礙。車父佳情況（例 之下層，於上：乂係此額外障層形成'緻密障層 之。該自限性保護氧化物#在 =冓，見在茲詳細敘述 又軋化物係在—銅結構附近可能擴散氧或 第9頁 478101478101 V. Description of the invention (5) Protecting copper conductors with wires and wires only showing interconnections with a connection path and τ road to avoid oxidation, so that those skilled in the art understand and agree with: 1 conductor, and It was found that this foot = conductor formed on the surface and covered = In addition, Λ formed a metal embedded conductor. Dielectric phases such as germanium, such as silicon oxide, silicon nitride, and nitrides, such as organic polymers, have poor barrier effects with porous materials (edge = two κ: 绝 · ° or less). Oxidation of steel occurs due to self-propelled, two-body suspension system oxidation resistance and / or water expansion. Among them, wafers cut from wafers are very easy to confirm that these obstacles are not flawless, and: "Material / =. Because it is difficult to "pinholes", that is to say, do n’t forget to prevent the lice and / or water from passing through the button), there are still needles / dense metal barriers (such as buttons and / or nitrogen-tight barrier materials; two) Kai 2 shows these oxides or other compounds; but it does not show any pinholes and other weak properties ... to effectively block them. Therefore, the present invention is suitable for copper structures -Insulators (such as: a dense barrier layer of copper copper structure. The additional barrier is made by providing an additional barrier material between 传, 材料 =: Γ can grow a self-regulating protective oxide material For example, in the case of metal inlaid conductors, #, μμ β / 陬. The situation of the car is good (eg the lower layer, above: the extra barrier layer forms a 'dense barrier layer'. The self-limiting protective oxide # 在= 冓, see detailed description here and the rolled material is in the vicinity of-copper structure may diffuse oxygen or page 478101

五、發明說明（6) 水之任何地 之銅結構， 的任何針孔 現在茲參 製造方法。 2 〇，各絕緣 詳知該金屬 凹洞，並使 質與結構性 膜。因此， 藝有關。 層2 0之導 體部分32與 4 〇相當於更 頁平面之前 中一部分。 屬鑲嵌導體 裎，然後覆 積與平坦化 常視所使用 可以確實地 對於順利 般金屬鑲嵌 重要。同樣 方形成，其不 亦用以阻塞平 瑕疲。 考該圖式說明 必須明白，所 層内均形成一 鑲後製程，其 該金屬與該絕 強健導體。該 該圖式中沒有 僅保護下層剩餘地方以及其環繞 常提供之緻密材料障層中所產生 一使用本發明之結構實例以及其 顯不之結構包括兩層絕緣層丨0盥 個金屬鑲嵌導體。然而，通常/已 係藉由將金屬澱積在一絕緣體之 緣體表面一般平坦，以形成高品 圖式亦包括根據本發明之障礙 一部分被視為與本發明之先前技 體結構30係所謂雙重金屬鑲嵌構造，盆且 如所述，層10中之金屬鑲嵌S :見之金屬鑲嵌導體構造，但是亦可能代表該 及/或之後具有一通路之雙重金屬鑲嵌結構其 可以熟知本技藝者熟悉之數種方式形成雙重金 1ίΐ在單一絕緣層上之一連續掩模與蝕刻製 孤，纟巴纟層並在其上形成線圖，以及—或多個澱 步驟’以填滿該成形凹洞。較佳之特別方法通 之特定材料，特別是視該絕緣體之性質，以及 於該絕緣體進行之製程而定。 進行本發明而言，本技藝中已習知並進行之一 與雙重金屬鑲嵌製程中所使用之特定方法並不 地，本發明不受限於在一絕緣體之凹洞内形V. Description of the invention (6) Any structure of copper in any place of water, any pinhole Now we refer to the manufacturing method. 2 〇, each insulation knows the metal pits in detail, and makes quality and structural film. So art is related. The conductive portions 32 and 40 of the layer 20 are equivalent to a part before the page plane. It is a damascene conductor 裎, and then it is covered and flattened. It is definitely important for smooth metal damascene. The same side is formed, and it is not used to block the flat fatigue. It must be understood from the diagram description that a post-mounting process is formed in all layers, the metal and the strong conductor. The diagram does not only protect the remaining part of the lower layer and the dense material barrier layer often provided around it. An example of the structure using the present invention and its obvious structure includes two insulating layers and two metal inlaid conductors. However, it is usually / has been achieved by depositing metal on an insulator. The surface of the body is generally flat to form a high-quality pattern. It also includes obstacles according to the present invention. Part of it is considered to be the same as the prior art structure 30 of the present invention. Double metal inlaid structure, as described, the metal inlaid S in layer 10: see the metal inlaid conductor structure, but it may also represent the double metal inlaid structure with a path after and / or it may be familiar to those skilled in the art Several methods of forming a double gold layer on a single insulating layer with continuous masking and etching to isolate the silicon layer, forming a line pattern on it, and—or multiple deposition steps—to fill the forming cavity. . The particular material that is preferred for the particular method depends in particular on the nature of the insulator and the process performed on the insulator. For the purpose of carrying out the present invention, one that is already known and performed in the art is not the same as the specific method used in the dual metal damascene process. The present invention is not limited to the shape of a cavity in an insulator.

第10頁 478101Page 10 478101

五、發明說明（7) 的結構，其亦適用於费& 況下，現在即將一種絕緣體之表面結構。後者情 言，該製圖方】之=熟知本技藝者而 亦能成功地進行。因J:”者)在/發明此等表面結構 具體實例與應用時，孰朵二Z 2，政作用有關本發明較佳 明。 “、、，v"本技藝者通常可以成功實行本發 由絕緣體層1 〇 ( JL可沒士 氮化物或其他堅硬、而I、=之材料）開始，將一種 止點）絕緣層！ 2覆在Λ面/ (作為勉刻及7或磨光 使用該硬式掩模1 2 /笋\ ^ '丨衣⑥形成一硬式掩杈。 料之蝕刿南丨 H 错由任何蝕刻方法與適用於該絕緣材 ;上形成凹洞14。然•，根據本 成声16，J：将拉出娘姑—)膜覆於該凹洞内部，形 為;σ 2心日^鑛、祭發或化學蒸氣殿積（CVD)進行 1〇〇土埃以、下Λ Λ足以在凹洞14内部提供完全覆蓋，約 100埃以下之極溥（I早礙膜通常就已足夠。 化f:V:任何習知方式覆蓋緻密材料(例如，㉟及/或氮 之擴散障層18 ’形成層18。必須記得包括此種緻密 t層（18)已習知用以抗氧及/或水擴散，但是其存 在诸如針孔等瑕疵，此等瑕疵會發生某些擴散作用。 然後以鋼填滿該凹洞其他部分，形成高導電性連接或其 =構40 ’並覆蓋氮化物罩42。然後，在與該銅電連接之 斤需位置（例如通路），將該氮化物罩製圖至該銅上。鈇 後’覆蓋次一層絕緣層20並.製圖’其可能為一連串經'製圖V. Description of the invention (7) The structure is also applicable to the & In the latter case, the cartographer] can be successfully performed by those skilled in the art. Because J: "者) In / invent specific examples and applications of these surface structures, it is better to understand the political role of this invention." ,,, v " The artist can usually successfully implement the invention from the insulator Layer 1 0 (JL may be nitride or other hard, and I, = materials), a kind of stop) insulation layer! 2 overlay on the Λ surface / (use as a engraving and 7 or polishing using the hard mask 1 2 / bamboo \ ^ '丨 clothing ⑥ to form a hard mask. Erosion of materials 丨 H 丨 by any etching method and applicable A cavity 14 is formed on the insulating material. Then, according to the original sound 16, J: The film is pulled out of the mother-in-law to cover the inside of the cavity, and the shape is: σ 2 心 日 ^ ore, offering or Chemical vapor deposition (CVD) for 100 soils and below Λ Λ is sufficient to provide complete coverage inside the cavity 14, which is about 100 Angstroms or less (I prematurely obstructing the film is usually sufficient. Chemical f: V: Any Conventional methods cover dense materials (eg, a diffusion barrier layer of tritium and / or nitrogen 18 'to form layer 18. It must be remembered that including such dense t-layers (18) is already known to resist oxygen and / or water diffusion, but its There are imperfections such as pinholes, which will cause some diffusion. Then fill the rest of the cavity with steel to form a highly conductive connection or its structure 40 'and cover the nitride cover 42. Then, in contact with The copper electrical connection requires a location (such as a via), and the nitride cover is mapped onto the copper. Afterwards, 'cover the next layer of insulating layer 20 and. FIG 'which may be through a series of' Drawing

第11頁Page 11

I號 89128210 修正 曰No. 89128210 amendment

V 五、發明說明（8) 層，若需要前文提及材料，則重複上述製程，形成可以自 限方式形成保護性氧化物之材料障礙膜2 6和緻密材料襯裡 凹洞2 4之擴散障層2 8以及銅通路3 4與導體3 2，然後形成氮 化罩3 8。若情況需要，可重複此製程，在額外絕緣層中形 成額外導體。 在該圖式所示之完整圖式中，可以得知該凹洞（其中形 成該銅結構）内部襯有一種緻密材料之擴散障礙以及一層 形成保護性氧化物之材料障礙膜。當可氧化銅之氧或水擴 散過絕緣體1 0、2 0到達該障礙膜1 6、2 8時，以自限方式形 成一種保護性氧化物，其不僅保護該膜其餘部分，亦可用 以阻塞該緻密材料障礙層1 8、2 8中可能存在之任何瑕疵。 有鑒於銅之氧化作用並非自限性質，因此該自限性氧化作 用在原位置上，經由數種方法中任何一者以及所形成效果 或其組合，保護並有效地修補該緻密材料中之瑕疵。 覆蓋該銅結構之該氮化罩通常係一種充分擴散障礙，而 且當其被限制在相當於低Κ絕緣層厚度之小面積與體積 時，其不會明顯提高該淨介電係數。在任何場合中，在歐 姆連接附近介於導體3 2與40之間的電容對於訊號傳播時間 之雜訊藕合實質上並不重要。 反之，該凹洞内所有材料實質上均有導電性，而且藉由 僅使用低Κ材料最小化與其他導電性結構之電容。必須注 意該障礙膜2 6與擴散障礙2 8可伸過一個通路底部，其間有 一個電連接通過。在氮化物罩4 2上形成之障礙膜2 6係一種 可避免以該通路連接至銅結構40之障礙膜26内氧化的充分V. Description of the invention (8) layer, if the aforementioned materials are required, repeat the above process to form a material barrier film 2 6 which can form protective oxides in a self-limiting manner and a diffusion barrier layer of dense material lining recesses 2 4 2 8 and the copper via 3 4 and the conductor 32, and then a nitride mask 38 is formed. This process can be repeated if necessary to form additional conductors in additional insulation. In the complete diagram shown in the figure, it can be seen that the cavity (where the copper structure is formed) is lined with a dense material diffusion barrier and a material barrier film forming a protective oxide. When the oxidizable copper oxygen or water diffuses through the insulators 10 and 20 to reach the barrier films 16 and 28, a protective oxide is formed in a self-limiting manner, which not only protects the rest of the film, but also can be used to block Any imperfections that may exist in the dense material barrier layers 18, 28. In view of the fact that the oxidation of copper is not self-limiting, the self-limiting oxidation acts in place and protects and effectively repairs defects in the dense material through any of several methods and the effect or combination thereof. The nitride cap covering the copper structure is usually a sufficient diffusion barrier, and when it is limited to a small area and volume equivalent to the thickness of a low-K insulating layer, it does not significantly increase the net dielectric constant. In any case, the capacitance between conductors 3 2 and 40 near the ohm connection is essentially not important for the noise combination of signal propagation time. In contrast, all the materials in the cavity are substantially conductive, and the capacitance with other conductive structures is minimized by using only low-K materials. It must be noted that the barrier film 26 and the diffusion barrier 28 can extend through the bottom of a path with an electrical connection therebetween. The barrier film 2 6 formed on the nitride cover 4 2 is a type which can prevent the oxidation in the barrier film 26 connected to the copper structure 40 through the via.

O:\67\67895.ptc 第12頁 478101 五、發明說明（9) 一 _, 严早礙。相對於大幅接高之、墓 其中發生的任何伴蠖性氧二電常數與電容，在該膜處或 散障礙之品質盥強声以另j獒出一種用以改善緻密材料擴 術。因此，即使使；促传：補其中可能形成之瑕疵的技 緣體時，本發明經由氧二；二水上擴散之似材料作為絕 發明使其他昂貴且邊際力丈^二^避免銅結構變質。本 於積體電路内之任：：結m以廉價而且確實地應用 度及雜訊免除性最大^w以保持且使訊號傳播速 雖然已租C 乂蒂 , 知本技藝者將會；體實例形式說明本發明，不過孰 進行改良。 白可在附錄申請專利範圍精神與 第13頁 478101 圖式簡單說明 第14頁O: \ 67 \ 67895.ptc Page 12 478101 V. Description of the invention (9) A _, serious early obstacles. Compared to the large-scale, high-accuracy oxygen-related dielectric constants and capacitances in the tomb, the quality of the barrier or scattered sound at the membrane is another way to improve the expansion of dense materials. Therefore, even if it is used to facilitate the transmission of defects that may form in it, the present invention uses oxygen two; similar materials that diffuse on the water as the absolute invention to make other expensive and marginal forces avoid the deterioration of copper structure. Anything in the integrated circuit: the junction m can be cheaply and reliably applied and the noise immunity can be maximized ^ w to maintain and make the signal propagation speed albeit rented C, know that the artist will; The form illustrates the invention, but it is improved. White can apply for the spirit of patent scope in the appendix and page 13 478101 Schematic illustration of page 14

Claims (1)

478101 六、申請專利範圍 1. 一種半導體裝置，包括 一層絕緣層， 一層銅結構，以及 介於該絕緣層與該銅結構之複合擴散障礙，其包括 一層緻密材料，以及 一層於存在氧或水之下，以可自限方式形成保護性氧 化物之材料膜。 2. 如申請專利範圍第1項之裝置，另外包括一個位於該 銅結構表面上之保護罩。 3. 如申請專利範圍第2項之裝置，其中該保護罩係由氮 化物形成。 4. 如申請專利範圍第1項之裝置，其中該銅結構係一種 金屬鑲嵌導體。 5. 如申請專利範圍第1項之裝置，其中該銅結構係一種 雙重金屬鑲嵌導體。 6. 如申請專利範圍第1項之裝置，包括數層絕緣層，該 數層絕緣層中至少兩層包括一個所述銅結構與一層所述複 合層。 7. 如申請專利範圍第1項之裝置，其中該絕緣體之介電 常數為3. 0或更低。 8. 如申請專利範圍第1項之裝置，其中該材料膜包括至 少一種材料，其選自包括紹、石夕與Cu3Ge。 9. 一種製造半導體裝置之方法，包括下列步驟： 形成一種複合導體' 其包括：478101 VI. Scope of patent application 1. A semiconductor device includes an insulating layer, a copper structure, and a composite diffusion barrier between the insulating layer and the copper structure, which includes a dense material and a layer in the presence of oxygen or water. Next, a material film of protective oxide can be formed in a self-limiting manner. 2. If the device in the scope of patent application is No. 1, it also includes a protective cover on the surface of the copper structure. 3. The device according to item 2 of the patent application, wherein the protective cover is formed of a nitride. 4. The device according to item 1 of the patent application scope, wherein the copper structure is a metal inlaid conductor. 5. The device according to the scope of patent application, wherein the copper structure is a double metal inlaid conductor. 6. The device according to item 1 of the patent application scope includes several insulating layers, and at least two of the insulating layers include one of the copper structure and one of the composite layers. 7. The device as claimed in claim 1 wherein the dielectric constant of the insulator is 3.0 or less. 8. The device as claimed in claim 1, wherein the material film includes at least one material selected from the group consisting of Shao, Shi Xi and Cu3Ge. 9. A method of manufacturing a semiconductor device, comprising the steps of: forming a composite conductor, which comprises: 第15頁 478101 六、申請專利範圍 一個銅主體 一層緻密材料之擴散障層，以及 一層於存在氧咬 化物之材料層，以及另外之㈣可以自限方式形成保護氧 形成一絕緣體，豆Γ 介於兮维鏠卿你#“ 、 ^成保護性氧化物之材料；® 5 Λ Λ 銅主體μn 1 〇 ·如申請專利範圍第q 凹洞内形成該複合導體。、/ ，，、中在該絕緣體中之 包括一另外步 1 1 ·如申請專利範圍第9項之方法 在該銅主體表面形成保護罩。 1 2 ·如申晴專利範圍第9 在該絕緣體與誃福人、旨 ’，，匕括另外步驟： 在該另外絕緣層/中^ 〇 V上形成一另外絕緣體，以及 1 q/ 成一另外複合導體。 1 3 ·如申μ專利範圍笛 性氧化物之材料包括$ ,員之方法，其中該可以形成保護 材料。 括至少一種選自包括鋁、矽與Cu3Ge之 於存在氧或水之下， 一 性氧化物之材料 艮方式氧化可形成保護 亥材枓係與該擴散障礙接觸。Page 15 478101 VI. Scope of patent application: a copper body, a diffusion barrier layer of dense material, and a layer of material in the presence of oxygen occlusion, and in addition, the protective oxygen can be formed in a self-limiting manner to form an insulator. Xi Xi 鏠 卿 你 # ", ^ to form a protective oxide material; ® 5 Λ Λ copper body μn 1 〇 · If the scope of the patent application for the q cavity formed the composite conductor., / ,,, in the insulator This includes an additional step 1 1 · Form a protective cover on the surface of the copper body as described in item 9 of the scope of the patent application. 1 2 · Case 9 of the scope of the patent for Shen Qing Including additional steps: forming an additional insulator on the other insulating layer / in ^ 0V, and 1 q / forming an additional composite conductor. 1 3 · If the material of the fusible oxide in the patent application scope includes the method, Among them, it can form a protective material. Including at least one material selected from the group consisting of aluminum, silicon, and Cu3Ge in the presence of oxygen or water, and a single oxide can be oxidized to form a protective system. The diffusion barrier contacts. 第16頁Page 16
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