CN110444509A - 整合式金属间隔垫与气隙互连 - Google Patents

整合式金属间隔垫与气隙互连 Download PDF

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CN110444509A
CN110444509A CN201910748960.9A CN201910748960A CN110444509A CN 110444509 A CN110444509 A CN 110444509A CN 201910748960 A CN201910748960 A CN 201910748960A CN 110444509 A CN110444509 A CN 110444509A
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separation pad
dielectric layer
feature
groove
substrate
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任河
M·B·奈克
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Applied Materials Inc
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Applied Materials Inc
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Abstract

本文所述的实施例涉及形成气隙互连的方法。将金属间隔垫层共形地沉积在其上形成有心轴结构的基板上。蚀刻金属间隔垫层以形成间隔垫特征并从基板移除心轴结构。可执行多种其他电介质沉积、图案化与蚀刻步骤以期望地图案化基板上存在的材料。最终，在相邻的间隔垫特征之间形成沟槽并在沟槽上沉积盖层以在相邻的间隔垫特征之间形成气隙。为了封装目的，互连通孔可配置成接触邻近气隙的间隔垫特征中的至少一者。

Description

整合式金属间隔垫与气隙互连
本申请是申请日为2015年3月3日、申请号为“201580022152.4”、发明名称为“整合式金属间隔垫与气隙互连”的发明专利申请的分案申请。
技术领域
本文所述的实施例总体上涉及用于形成具有气隙的半导体器件的方法。更具体地，本文所述的实施例涉及整合式金属间隔垫与气隙互连。
背景技术
对于先进的节点技术而言，互连RC延迟(转换性能)与归因于电容的功率阻尼是器件性能的重要阀值。已知传统低k材料在降低介电常数(k值)的缩放性能限制(作为损害机械强度与电流泄漏性能的结果)，一个用于电容缩放的有希望的候选者包括在金属线路之间采用气隙。气隙具有接近1.0的k值，这有助于将组件中的整体有效k值降低至可接受水平。然而，气隙整合需要额外的处理步骤，包括排除掩模光刻、电介质凹陷、衬里沉积、电介质沉积、电介质化学机械研磨(CMP)等等。这些额外的步骤提高整合气隙的成本并降低气隙技术的优点与接受性。
此外，通常使用双图案化代替单印刷图案化来形成气隙。双图案化的某些示例包括光刻-蚀刻-光刻-蚀刻(LELE)与间隔垫对齐双图案化(SADP)。这些双图案化技术不仅需要额外的暴露与蚀刻工艺，而且还需要掩模以界定连接件与接线端。双图案化工艺将期望的设计转移至最终产物，但却是以增加的成本与降低的效率来完成。
因此，需要的是用于形成气隙互连结构的改进的方法。
发明内容
在一个实施例中，提供一种形成半导体器件的方法。此方法包括在心轴结构上共形地沉积金属间隔垫层，并蚀刻金属间隔垫层的至少一部分以形成一个或多个间隔垫特征。移除心轴结构，将电介质层沉积在间隔垫特征上，以及图案化电介质层并且在相邻的间隔垫特征之间蚀刻电介质层。接着在间隔垫特征上非共形地沉积盖层以在相邻的间隔垫特征之间形成气隙。
在另一个实施例中，提供一种形成半导体器件的方法。此方法包括在心轴结构上共形地沉积金属间隔垫层，并蚀刻金属间隔垫层的至少一部分以形成一个或多个间隔垫特征。移除心轴结构，将可流动电介质层沉积在金属间隔垫层上，以及图案化可流动电介质层的第一区域。接着蚀刻间隔垫特征中的至少一者与可流动电介质层以形成第一沟槽，且将可流动电介质层重新沉积于第一沟槽中。图案化并在相邻的间隔垫特征之间蚀刻可流动电介质层的第二区域以形成第二沟槽。将盖层非共形地沉积在间隔垫特征、第二沟槽与可流动电介质层上以在第二沟槽中形成气隙。最终，平坦化盖层与可流动电介质层的至少一部分。
在又另一个实施例中，提供一种形成半导体器件的方法。此方法包括提供其上形成有氧化物心轴结构的基板并且在此氧化物心轴结构上共形地沉积金属间隔垫层。蚀刻金属间隔垫层的至少一部分以形成一个或多个间隔垫特征。蚀刻心轴结构，在金属间隔垫层上沉积可流动电介质层，以及图案化可流动电介质层的第一区域。在第一区域中蚀刻间隔垫特征中的至少一者与可流动电介质层以形成第一沟槽，并将可流动电介质层重新沉积于第一沟槽中。图案化可流动电介质层的第二区域，并在第二区域中蚀刻相邻的间隔垫特征之间的可流动电介质层以形成第二沟槽。将含硅盖层沉积在间隔垫特征、第二沟槽与可流动电介质层上以在第二沟槽中形成气隙。研磨盖层与可流动电介质层的至少一部分以形成平坦化表面，且互连形成为通过基板到达邻近气隙的间隔垫特征中的至少一者。
附图说明
因此，为了详细理解本公开的上述特征的方式，可参照某些实施例得出以上简短概述的本公开的更具体的描述，该等实施例中的一些实施例在附图中示出。然而，需注意，附图仅描绘本公开的典型实施例而因此附图不被视为本公开的范围的限制因素，因为本公开内容可接纳其他等效实施例。
图1-15是描绘根据本文公开的一个实施例的形成气隙互连的顺序的基板的示意性横剖面图。
图16是可用于执行本文所述的多种工艺的设备的示意性平面图。
为了促进理解，已经尽可能应用相同的附图标号来标示附图中共有的相同元件。预期一个实施例中公开的元件可有利地用于其他实施例而不需特别详述。
【实施例】
本文所述的实施例涉及形成气隙互连的方法。将金属间隔垫层共形地沉积在其上形成有心轴结构的基板上。蚀刻金属间隔垫层以形成间隔垫特征并从基板移除心轴结构。可执行多种其他电介质沉积、图案化与蚀刻步骤以期望地图案化基板上存在的材料。由于处理顺序，在相邻的间隔垫特征之间形成沟槽并在沟槽上沉积盖层以在相邻的间隔垫特征之间形成气隙。为了封装，互连通孔可配置成接触邻近气隙的间隔垫特征中的至少一者。
下方详细描述的形成顺序描绘半导体器件在不同制造阶段时的部分视图。除了形成气隙互连外，预期下方描述的方法可用以形成实现在互连技术以外的气隙。下方描述的顺序提供形成气隙互连的一个实施例，然而应当理解可在顺序上重新排列、删除、重复或以上述的任何组合来执行多种操作的形成顺序。
图1描绘器件结构100的示意性横剖面图。器件结构100包括基板102与形成在基板102上的一个或多个心轴结构104。在一个实施例中，基板102包括蚀刻终止层且可由多种材料(诸如SiN、SiCN、SiOC、SiON、Si、C、O、N、金属氮化物(例如，AlN)与上述的组合)形成。心轴结构104彼此间隔以界定后续沉积材料的模板。心轴结构104由氧化物或含硅材料所形成。例如，心轴结构104可由二氧化硅或多晶硅所形成。
图2是描绘金属沉积工艺的结果的器件结构100的示意性横剖面图。将金属间隔垫层106共形地沉积在基板102与心轴结构104上。金属间隔垫层106使用的材料的示例包括金属有机化学气相沉积(MOCVD)的钨、物理气相沉积(PVD)的金属硅化物与化学气相沉积(CVD)的金属硅化物。适当金属硅化物材料的示例包括硅化钴、硅化钛、硅化镍与上述的组合。
金属间隔垫层材料可经选择以使得金属间隔垫层106与心轴结构104材料反应以形成器件结构100的最终金属布线。在已经沉积金属间隔垫层106后，可执行沉积后硅化工艺以促进金属间隔垫层106/心轴结构104反应。所得心轴结构104维持电介质性质，而将金属间隔垫层106形成为低电阻率导体。
适当的心轴结构材料与金属间隔垫层材料组合的示例包括氧化物/MOCVD钨、多晶硅/MOCVD钨与氧化物或硅/硅化物。金属间隔垫层材料也可包括镍、钴、钨等等。共形地沉积在心轴结构104上的金属间隔垫层106形成金属互联布线，因此降低或排除传统气隙互连技术中的传统金属缝隙填充的必要性。再者，直接在最终金属布线(金属间隔垫层106)上执行下面更详细描述的图案化工艺，这降低或排除用于气隙互连形成的图案转移(蚀刻)步骤的必要性。
图3是描绘蚀刻工艺结果的器件结构100的示意性横剖面图。各向异性地蚀刻金属间隔垫层106以移除金属间隔垫层106的数个部分。在一个示例中，可应用各向异性干式等离子体蚀刻工艺。若金属间隔垫层106包括钨，那么可应用CF4干式等离子体来蚀刻金属间隔垫层106。在此示例中，在具有约10mT与约50mT之间的压力的环境中，可以以约50sccm至约200sccm之间的速率使CF4前体气体流动。可用约200W与约400W之间的RF功率与约100W与约500W之间的偏置将CF4激发成等离子体。可用于执行所述的蚀刻工艺的工艺腔室的一个示例是自加利福尼亚州圣克拉拉市的应用材料有限公司取得的MESATM蚀刻腔室。然而，预期来自其他制造商的其他相似配置的腔室也可执行所述的工艺。
由于蚀刻工艺，移除金属间隔垫层106的至少一部分以暴露心轴结构104的顶面108与基板102的表面110。金属间隔垫层106的蚀刻可以是与时间有关的或终点受控的以使得金属间隔垫层106的剩余部分与心轴结构104的顶面108共面。在蚀刻金属间隔垫层106后，先前连续的金属间隔垫层106现在包括分离的不连续结构。这些结构可被称为间隔垫特征106。本文后续使用的术语间隔垫特征107与金属间隔垫层106指的是相同的材料，然而，间隔垫特征107是金属间隔垫层106的蚀刻后形式。
图4是描绘蚀刻工艺结果的器件结构100的示意性横剖面图。利用与间隔垫特征107的金属材料不反应的选择性蚀刻工艺来蚀刻心轴结构104。在一个实施例中，利用稀释HF溶液的湿式蚀刻工艺被用来蚀刻心轴结构104。湿蚀刻工艺可进行一段足以从基板102完全移除心轴结构104的时间。在另一个实施例中，利用NF3与NH3的各向异性干式蚀刻工艺可被用来移除心轴结构104。在此示例中，可在具有约200mT与约3000mT之间的压力的环境中，以约10sccm与约200sccm之间的速率使NF3前体气体流动并以约100sccm与约1000sccm之间的速率使NH3前体气体流动。可用约200W与约2000W之间的RF功率将NF3与NH3激发成等离子体。得到的器件结构100包括通过基板102的暴露表面110而彼此分隔的间隔垫特征107。图1至图4中所述的工艺完成金属间隔垫层106的图案化。
图5是描绘可流动CVD沉积工艺结果的器件结构100的示意性横剖面图。如图所示，通过可流动或类流动CVD工艺将电介质层112沉积在器件结构100上并且在基板102与间隔垫特征107上。以毯覆方式沉积电介质层112，以使得电介质层112填充相邻间隔垫特征107之间的空间并接触基板102。由于可流动电介质层112的特性，最小化或消除电介质层112中的空隙且电介质层112的顶面基本上是平坦的。用配置成延伸到间隔垫特征107上方的厚度来沉积电介质层112。
在可流动CVD工艺的一个示例中，在约100℃或更低的温度下使有机硅前体与氧前体反应以形成电介质层112。适当的有机硅前体具有低于约8的碳原子与硅原子的比例。适当的有机硅化合物也可具有约0至约6的氧与硅原子的比例，且可包括Si-O-Si键，Si-O-Si键促进形成具有来自碳与羟基基团的污染物降低的SiOx膜。适当的氧前体可包括氧分子(O2)、臭氧(O3)、氮-氧化合物(诸如，NO、NO2或N2O)、氢-氧化合物(诸如，水或过氧化物)、碳-氧化合物(诸如，一氧化碳或二氧化碳)与其他含氧前体。在一个实施例中，电介质层112包括SiOCH且具有约2.0与约3.0之间的k值。
也可与有机硅与氧前体一起提供载气(例如，惰性气体)。可在引导至腔室之前激活氧前体，例如利用远程等离子体产生器，远程等离子体产生器可包括热解离、紫外光解离、RF、DC与/或微波解离。在一个实施例中，可将4-6kW的RF功率耦合至900-1,800sccm的氩与600-1,200sccm的氧分子的流。可与氧前体分开提供有机硅前体至腔室以避免在腔室外部反应。可以在约800mgm至约1,600mgm的液体-等效流动速率下将有机硅前体作为气体引导至腔室。可包括在约600sccm至约2,400sccm的流动速率下的氦作为载气。可以以约3sLm与约20sLm之间的流动速率将激活的氧前体引导至腔室。
前体反应以在基板102上沉积可流动氧化物层或电介质层112。上述的CVD工艺可实施于自加利福尼亚州圣克拉拉市的应用材料有限公司取得的ETERNATMFCVD系统上。然而，预期来自其他制造商的其他相似配置的腔室也可执行所述的工艺。
图6是描绘掩模形成与图案化工艺结果的器件结构100的示意性横剖面图。将第一掩模114(诸如，光阻剂材料)沉积于电介质层112上并接着加以图案化。第一掩模114可以是毯覆沉积于电介质层112上的光敏聚合物材料。图案化第一掩模114以形成暴露的第一区域116。在一个实施例中，利用193nm浸润式光刻工艺来图案化第一掩模114并暴露第一区域116。移除第一区域116中的第一掩模114并暴露电介质层112。在一个实施例中，间隔垫特征107中的至少一者被包括于第一区域116的下方。在一个示例中，第一区域116界定后续将从器件结构100移除的接线端。
图7是描绘接线端移除工艺结果的器件结构100的示意性横剖面图。可应用各向异性蚀刻工艺以移除第一区域116(参见图6)中的材料以便形成第一沟槽117。可应用多种蚀刻技术，包括湿式蚀刻与干式等离子体蚀刻技术。在此示例中，应用一个或多个蚀刻剂以移除第一区域116中的电介质层112与间隔垫特征107以便形成第一沟槽117。例如，可应用可移除第一区域116中的电介质层112与间隔垫特征106两者的单一蚀刻剂或对电介质层112或间隔垫特征107具选择性的多个蚀刻剂来形成第一沟槽117。第一沟槽117的底部由基板102的表面110所界定，而第一沟槽117的侧壁由电介质层112所界定。通过移除第一区域116中的间隔垫特征107，形成器件结构100的接线端以创建期望的布线结构，并且可进行进一步的工艺。
图8是描绘掩模移除工艺结果的器件结构100的示意性横剖面图。如图所示，已经移除第一掩模114以暴露电介质层112。可通过多种方法(包括灰化或蚀刻第一掩模114)来移除第一掩模114。例如，经由对电介质层112的材料具选择性的湿式清洁工艺来移除第一掩模114。
图9是描绘可流动电介质沉积工艺结果的器件结构100的示意性横剖面图。根据详细参照图5所示的工艺，用可流动电介质层112填充第一沟槽117。得到的电介质层112具有相似于最初沉积的电介质层112的特征。
图10是描绘掩模形成与图案化工艺结果的器件结构100的示意性横剖面图。将第二掩模118(可以相似于第一掩模114的方式加以形成)沉积于电介质层112上并经图案化以暴露第二区域120。第二掩模118可保护先前暴露的第一区域116与填充第一沟槽117的后续沉积的电介质层112。以相似于第一掩模114的图案化的方式来执行第二掩模118的图案化。在一个实施例中，第一掩模114与第二掩模118可以是分开的掩模或相同的掩模。若第一掩模114与第二掩模118形成单一掩模，则在反向色调(reverse tone)阻剂中完成光刻工艺，以使得器件结构100的保护区域互补。第二区域120暴露设置在相邻的间隔垫特征107上的电介质层112的至少一部分。
图11是描绘电介质蚀刻工艺结果的器件结构100的示意性横剖面图。此处，蚀刻第二区域120中的电介质层112以暴露相邻的间隔垫特征106的至少一部分与基板102的表面。如此，在相邻的间隔垫特征106之间形成第二沟槽121。第二沟槽121可具有约1.5：1.0与约5.0：1.0之间的深宽比。利用钝化干式等离子体蚀刻工艺来蚀刻电介质层112。所利用的蚀刻剂物种可展现电介质层112与间隔垫特征106的金属之间的高度选择性。
在一个实施例中，利用C4F6来蚀刻电介质层112。在此示例中，可在具有约200mT的压力的环境中以约10sccm的速率使C4F6前体气体流动。可用约100W与约2000W之间的RF功率与约50W与约500W之间的偏置将C4F6激发成等离子体。蚀刻剂物种优选地选择成在蚀刻电介质层112时保护间隔垫特征107的暴露表面122。相似地，蚀刻剂物种对基板102具选择性并经选择成蚀刻电介质层112。在一个实施例中，可沉积电介质衬里以钝化间隔垫特征107的暴露表面122。电介质衬里可包括诸如Si、O、C、N、H与上述的组合的材料。
图12是描绘掩模移除工艺结果的器件结构100的示意性横剖面图。如图所示，移除第二掩模118以暴露电介质层112。可通过与用于移除第一掩模114的工艺相似的工艺来移除第二掩模118。
图13是描绘盖层沉积工艺结果的器件结构100的示意性横剖面图。将盖层124沉积于器件结构100上且在邻近第二沟槽121的间隔垫特征107的暴露表面122(参见图12)的至少一部分与电介质层112上。盖层124包括低k含硅材料。例如，盖层124材料可包括SiOC、SiOCN、SiCN等等。
在一个实施例中，利用SiOC作为盖层124。在此示例中，可在具有约1000mT与约3000mT之间的压力的环境中，以约50sccm与约500sccm之间的速率使含有机硅前体气体流动并以约200sccm与约1000sccm之间的速率使含氧前体流动。可用约500W与约2000W之间的RF功率将前体激发成等离子体。在一个示例中，盖层124沉积是桥接第二沟槽121的表面弯曲相关的毯覆沉积工艺。沉积工艺可以是时间相关的CVD工艺。
盖层124沉积配置成在第二沟槽121的一部分中沉积材料。如此，盖层124可完全覆盖邻近第二沟槽121的间隔垫特征106的顶部暴露表面122，并且仅覆盖邻近第二沟槽121的间隔垫特征106的侧壁暴露表面122的一部分。盖层124沉积工艺配置成防止盖层124沉积在基板102的表面110上。因此，在相邻间隔垫特征107之间的第二沟槽121中形成气隙123。可由相邻的间隔垫特征107、基板102与盖层124来界定气隙123。气隙123基本上没有除了空气以外的任何材料。
图14是描绘CMP工艺结果的器件结构的示意性横剖面图。先前沉积的电介质层112与盖层124可具有横跨器件结构100的表面的非均匀厚度。执行CMP工艺或其他平坦化工艺以平坦化器件结构100的顶面，以使得间隔垫特征106、电介质层112与盖层124基本上共面。在一个实施例中，可应用间隔垫特征107作为坚硬停止件，以确定平坦化/研磨终点。CMP工艺可实施于从加利福尼亚州圣克拉拉市的应用材料有限公司取得的REFLEXION GTTM系统或其他兼容的CMP系统。也可应用来自其他制造商的平坦化系统来执行所述工艺。
CMP工艺造成器件结构100具有平坦化的上表面，并具有设置在第二沟槽121的上部中的剩余盖层124部分以在下方界定气隙123。在此气隙整合方案中可执行CMP工艺仅仅一次，因此消除传统气隙整合方案中的金属CMP与电介质CMP的多次CMP工艺的必要性。
图15是描绘互连形成工艺结果的器件结构100的示意性横剖面图。至少通过基板102至邻近气隙123的导电性的间隔垫特征107中的一者来形成互连126。可通过蚀刻或烧蚀工艺来形成通孔(未示出)，且可用互连材料来填充得到的通孔。互连126可以是导电材料(诸如，金属或金属硅化物)并可通过多种工艺加以沉积，多种工艺包括CVD、PVD、原子层沉积(ALD)与外延沉积等等。互连126将间隔垫特征107电性连接至半导体器件的其他部件并可在半导体封装工艺过程中使用。
图16是可用于执行本文所述的多种工艺的设备200的示意平面图。设备200包括基板搬运部分202与基板工艺部分204。基板搬运部分202包括装载站206、传送站208与接口站210。在装载站206处将基板装载到设备200中。在某些示例中，装载操作可包括在载体上设置一个或多个基板以便传送通过设备200。传送站208将基板从装载站206移动至接口站210。若需要的话，传送站208可包括基板搬运特征(诸如，鳍状件)。接口站208将基板提供至入口负载锁定腔室212以便进入通常在真空下操作的基板工艺部分204。基板工艺部分204包括多个耦接至传送腔室220的基板处理腔室216，传送腔室220中设置有传送机器人218。处理腔室216的每一个可以是ALD腔室、低温CVD腔室、高密度等离子体CVD腔室、PECVD腔室、蚀刻腔室或等离子体清洁腔室。在一个实施例中，腔室216包括形成可流动电介质层的等离子体CVD腔室以及可蚀刻硅层、氧化物层和/或金属层的等离子体蚀刻腔室。等离子体CVD腔室可以是HDP CVD腔室，而等离子体蚀刻腔室可以是远程等离子体腔室。出口负载锁定腔室214接收处理过的基板以传送回基板搬运部分202。
在特征为多个设置于基板载体上以进行处理的基板的实施例中，处理腔室216中的每一个可在同一时间下处理多个基板。当应用设备200来实践上述的方法时，可同时在多个基板上执行任何或所有工艺。
虽然上文针对本公开的实施例，但可设计出本公开的其他与进一步的实施例而不背离本公开的基本范围，本公开的范围由所附权利要求书确定。

Claims (20)

1.一种形成半导体器件的方法，所述方法包括：
在基板上形成含金属间隔垫特征；
在所述含金属间隔垫特征上沉积电介质层；
图案化所述电介质层；
蚀刻相邻的含金属间隔垫特征之间的所述电介质层；以及
在所述含金属间隔垫特征上沉积盖层，其中气隙形成在相邻的含金属间隔垫特征之间。
2.如权利要求1所述的方法，进一步包括：
在心轴结构上共形地沉积金属间隔垫层；以及
蚀刻所述金属间隔垫层的至少一部分以形成所述含金属间隔垫特征。
3.如权利要求2所述的方法，其中所述金属间隔垫层包括钨或金属硅化物材料。
4.如权利要求2所述的方法，其中所述金属间隔垫层是选自钨、钴与镍所构成的组。
5.如权利要求2所述的方法，其中所述金属间隔垫层由MOCVD工艺形成。
6.如权利要求1所述的方法，其中所述电介质层通过可流动CVD工艺来沉积。
7.如权利要求6所述的方法，其中所述电介质层包括可调低k材料。
8.如权利要求7所述的方法，其中所述电介质层包括SiOCH。
9.如权利要求1所述的方法，其中相邻的含金属间隔垫特征限定沟槽，所述沟槽具有在约1.5：1与约5：1之间的深宽比。
10.如权利要求9所述的方法，其中所述沟槽的上部区域由所述盖层来限定。
11.如权利要求10所述的方法，其中所述盖层包括含硅材料。
12.一种形成半导体器件的方法，所述方法包括：
在基板上形成金属硅化物心轴结构；
在所述基板上形成间隔垫特征；
移除所述金属硅化物心轴结构；
在所述间隔垫特征上沉积可流动电介质层；
图案化所述可流动电介质层；
蚀刻相邻的间隔垫特征之间的所述可流动电介质层以形成沟槽；
在所述间隔垫特征、所述沟槽、和所述可流动电介质层上沉积盖层，其中气隙形成在所述沟槽中；以及
平坦化所述盖层与所述可流动电介质层的至少一部分。
13.如权利要求12所述的方法，进一步包括形成至邻近所述气隙的所述间隔垫特征中的至少一个的互连。
14.如权利要求12所述的方法，其中平坦化包括电介质CMP工艺。
15.如权利要求14所述的方法，其中所述间隔垫特征为所述平坦化限定终点。
16.如权利要求12所述的方法，其中所述盖层延伸到所述沟槽中且在所述间隔垫特征的顶面下方。
17.如权利要求16所述的方法，其中所述盖层包括含硅材料。
18.如权利要求12所述的方法，其中所述沟槽具有在约1.5：1与约5：1之间的深宽比。
19.一种形成半导体器件的方法，所述方法包括：
将基板定位在第一处理腔室中，所述基板上形成有含金属间隔垫特征；
在所述间隔垫特征上沉积电介质层；
在第一区域中蚀刻所述电介质层以及所述间隔垫特征中的至少一个以形成第一沟槽；
在第二区域中蚀刻相邻的间隔垫特征之间的所述电介质层以形成第二沟槽；
在所述间隔垫特征、所述第二沟槽和所述电介质层上沉积盖层，其中气隙形成在所述第二沟槽中；
将所述基板传送到第二处理腔室；以及
平坦化所述盖层与所述电介质层的至少一部分。
20.如权利要求19所述的方法，进一步包括：
形成通过所述基板至邻近所述气隙的所述间隔垫特征中的至少一个的互连。
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