TW201517272A - 半導體元件及其形成方法 - Google Patents

半導體元件及其形成方法 Download PDF

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TW201517272A
TW201517272A TW103125966A TW103125966A TW201517272A TW 201517272 A TW201517272 A TW 201517272A TW 103125966 A TW103125966 A TW 103125966A TW 103125966 A TW103125966 A TW 103125966A TW 201517272 A TW201517272 A TW 201517272A
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gate electrode
fin structure
fin
dummy gate
substrate
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TWI591827B (zh
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Che-Cheng Chang
chang-yin Chen
Jr-Jung Lin
Chih-Han Lin
Yung-Jung Chang
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Taiwan Semiconductor Mfg Co Ltd
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Abstract

一種半導體元件,其包括基底。半導體元件還包括位於基底上之第一鰭結構及第二鰭結構。半導體元件更包括分別橫越於第一鰭結構及第二鰭結構上之第一閘極電極及第二閘極電極。此外,半導體元件包括介於第一鰭結構與第一閘極電極之間,且介於第二鰭結構與第二閘極電極之間的閘極介電層。再者,半導體元件包括位於基底上之虛置閘極電極。虛置閘極電極位於第一閘極電極與第二閘極電極之間,且虛置閘極電極之較高部分寬於虛置閘極電極之較低部分。

Description

半導體元件及其形成方法
本揭露書係有關於半導體元件及其形成方法,且特別是有關於鰭式場效電晶體元件及其形成方法。
半導體元件使用於多種電子應用中,例如個人電腦、行動電話、數位相機、及其他電子裝備。半導體元件之製作係藉由連續地於半導體基底上沉積絕緣層或介電層、導電層、及半導體層,並使用微影及蝕刻製程將許多材料層圖案化,以於半導體基底上形成電路構件及元件。
為了追求更高元件密度、更佳效能、及更低成本,半導體工業已進展至奈米技術製程,來自製程及設計的挑戰已促使三維設計的發展,例如鰭式場效電晶體(fin field effect transistor,FinFET)。鰭式場效電晶體被製作成具有延伸自基底之薄垂直鰭(thin vertical fin)(或鰭結構)。鰭式場效電晶體之通道(channel)係形成於此垂直鰭之中。鰭上提供有閘極。鰭式場效電晶體之優點可包括短通道效應(short channel effect)之減輕及更高的電流量。
然而,由於特徵尺寸(feature size)持續縮小,製程亦持續地變得更難以進行。因此,形成包含鰭式場效電晶體之可靠半導體元件更具挑戰性。
本揭露書之實施例提供一種半導體元件,包括:一基底;一第一鰭結構及一第二鰭結構,位於該基底之上;一第一閘極電極及一第二閘極電極,分別橫越於該第一鰭結構及該第二鰭結構之上;一閘極介電層,介於該第一鰭結構與該第一閘極電極之間,且介於該第二鰭結構與該第二閘極電極之間以及一虛置閘極電極,位於該基底之上,其中該虛置閘極電極位於該第一閘極電極與該第二閘極電極之間,且該虛置閘極電極之一較高部分寬於該虛置閘極電極之一較低部分。
本揭露書之實施例提供一種半導體元件,包括:一基底;一第一鰭結構及一第二鰭結構,位於該基底之上;一第一閘極電極及一第二閘極電極,分別橫越於該第一鰭結構及該第二鰭結構之上;一閘極介電層,介於該第一鰭結構與該第一閘極電極之間,且介於該第二鰭結構與該第二閘極電極之間以及一虛置閘極電極,位於該基底之上,其中該虛置閘極電極位於該第一閘極電極與該第二閘極電極之間,且一凹陷位於該虛置閘極結構之一較低部分處。
本揭露書之實施例提供一種半導體元件的形成方法,包括:於一基底上形成一第一鰭結構及一第二鰭結構;於該第一鰭結構、該第二鰭結構、及該基底上沉積一閘極介電層及一閘極電極層;以及進行一蝕刻製程以部分移除該閘極電極層,以形成分別橫越該第一鰭結構及該第二鰭結構之一第一閘極電極及一第二閘極電極,並於該基底上及該第一鰭結構與該第二鰭結構之間形成一虛置閘極電極,其中該虛置閘極電極之一底部部分是凹陷的。
10、30、30’‧‧‧半導體元件
100、100a、100b‧‧‧鰭式場效電晶體元件
102‧‧‧基底
104、104a、104b‧‧‧鰭結構
105a、105b‧‧‧鰭末端
106‧‧‧閘極介電層
108‧‧‧隔離結構
110、110a、110b‧‧‧閘極電極
110d‧‧‧虛置閘極電極
111‧‧‧通道區
112a、112b‧‧‧硬遮罩
114‧‧‧源極區
116‧‧‧汲極區
117‧‧‧殘留物
300a、300b‧‧‧鰭式場效電晶體元件
310‧‧‧閘極電極層
310a、310a’、310b、310b’‧‧‧閘極電極
310d、310d’‧‧‧虛置閘極電極
312‧‧‧頂部
314、314’‧‧‧凹陷
316、316’、317、317’、319‧‧‧側壁
D、D’、D”‧‧‧間隔
W1、W2、W2’、W3、W3’、W4、W5‧‧‧寬度
θ1、θ2‧‧‧角度
第1圖顯示根據一些實施例之鰭式場效電晶體元件的立體圖。
第2A圖為根據一些實施例之半導體元件的布局上視圖,其包含二或更多個鰭式場效電晶體元件。
第2B圖為根據一些實施例之半導體元件的剖面圖,其係取自第2A圖中之切線b-b。
第2C圖為根據一些實施例之半導體元件的剖面圖,其係取自第2A圖中之切線c-c。
第3A-3C圖顯示根據一些實施例之半導體元件的製程上視圖。
第4A-4D圖顯示根據一些實施例之半導體元件的製程剖面圖。
第5A-5D圖顯示根據一些實施例之半導體元件的製程剖面圖。
第6A-6B圖顯示根據一些實施例之半導體元件的剖面圖。
以下將詳細說明本揭露書實施例之製作與使用方式。然應注意的是,本揭露書提供許多可供應用的發明概念,其可以多種特定形式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式,非用以限制本發明之範圍。此外,在敘述中,第一製程與第二製程之進行,可包括第二製程 於第一製程之後立刻進行之實施例,亦可包括其他附加製程於第一製程與第二製程之間進行之實施例。許多元件可能被任意地繪製成不同的尺寸比例。這僅是為了簡化與清楚化。再者,當述及一第一材料層位於一第二材料層上或之上時,包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。以下,敘述了實施例之一些變化。在不同的圖式與實施例敘述中,相似的標號可用以標示相似的元件。
請參照第1圖,其顯示根據一些實施例之鰭式場效電晶體元件100的立體圖。鰭式場效電晶體元件100包括基底102。基底102包括半導體基底。在一些實施例中,基底102為塊狀半導體基底(bulk semiconductor substrate),例如矽晶圓。基底102可為結晶結構之矽。在一些其他實施例中,基底102包括其他元素半導體(例如,鍺),或其包括化合物半導體(compound semiconductor)。化合物半導體可包括碳化矽、砷化鎵、砷化銦、磷化銦、及/或其相似物。在一些實施例中,基底102包括絕緣層上覆半導體(semiconductor-on-insulator,SOI)基底。絕緣層上覆半導體基底可藉著使用氧離子植入隔離(separation by implantation of oxygen,SIMOX)製程、晶圓接合(wafer bonding)製程、及/或其他適合方法而製作。
鰭式場效電晶體元件100還包括一或多個鰭結構(fin structures)104(例如,矽鰭(Si fins)),其延伸自基底102。鰭結構104可選擇性包括鍺。鰭結構104可藉著使用適合的製程而形成,例如微影及蝕刻製程。在一些實施例中,鰭結構104係使用乾式蝕刻或電漿製程而蝕刻自基底102。隔離結構 108(例如,淺溝槽絕緣(STI)結構)被形成來圍繞鰭結構104。在一些實施例中,鰭結構104之較低部分由隔離結構108所圍繞,而鰭結構104之較高部分突出於隔離結構108,如第1圖所示。
鰭式場效電晶體元件100更包括閘極結構,包括閘極電極110及閘極介電層106。閘極結構係形成於鰭結構104之中間部分上。在一些實施例中,多重的閘極結構形成於鰭結構104之上。許多其他材料層亦可存在於閘極結構之中,例如蓋層(capping layers)、界面層(interfacial layers)、間隔構件(spacer elements)、及/或其他適合的結構。
在一些實施例中,閘極介電層106包括鄰接於鰭結構104之界面層(未顯示)。界面層可包括氧化矽。閘極介電層106可包括其他的介電材料,例如氧化矽、氮化矽、氮氧化矽、具高介電常數(high-k)之介電材料、或前述之組合。高介電常數材料之例子包括氧化鉿(hafnium oxide)、氧化鋯(zirconium oxide)、氧化鋁(aluminum oxide)、二氧化鉿-氧化鋁合金(hafnium dioxide-aluminum alloy)、氧化矽鉿(hafnium silicon oxide)、氮氧化矽鉿(hafnium silicon oxynitride)、氧化鉭鉿(hafnium tantalum oxide)、氧化鈦鉿(hafnium titanium oxide)、氧化鋯鉿(hafnium zirconium oxide)、其相似物、或前述之組合。
閘極電極110可包括多晶矽或金屬,其包括氮化鈦(TiN)、氮化鉭(TaN)、矽化鎳(NiSi)、矽化鈷(CoSi)、鉬(Mo)、銅(Cu)、鎢(W)、鋁(Al)、鈷(Co)、鋯(Zr)、鉑(Pt)、其他適合的材料、或前述之組合。閘極電極110可形成於後閘極製程(gate last process)(或稱閘極置換製程,gate replacement process)。
每一鰭結構104包括通道區111,其由閘極電極110極閘極介電層106所圍繞或纏繞。可摻雜鰭結構104以提供用作N型鰭式場效電晶體(NMOS元件)或P型鰭式場效電晶體(PMOD)之適當通道。可使用適合的製程摻雜鰭結構104,例如離子佈植製程(ion implantation process)、擴散製程(diffusion process)、退火製程(annealing process)、其他可應用製程、或前述之組合。每一鰭結構104包括通道區111兩旁之源極區114及汲極區116。鰭式場效電晶體元件100可為包含在微處理器(microprocessor)、記憶體元件(memory cell)(例如,靜態隨機存取記憶體,SRAM)、及/或其他積體電路中之元件。
如上所述,鰭式場效電晶體元件可包括多個閘極結構及多個鰭結構。第2A圖為根據一些實施例之半導體元件10的布局上視圖,其包含二或更多個鰭式場效電晶體元件。如第2A圖所示,顯示了一部分的半導體元件10。半導體元件10包括鰭式場效電晶體元件100a及100b。圍繞著鰭式場效電晶體元件100a及100b之隔離結構108使鰭式場效電晶體元件100a及100b彼此電性絕緣。
如第2A圖所示,根據一些實施例,鰭式場效電晶體元件100a及100b包括多個鰭結構及多個閘極電極。鰭式場效電晶體元件100a包括多個鰭結構104a及橫越鰭結構104a之多個閘極電極110a。鰭結構104a可大抵彼此平行。閘極電極110a亦可彼此平行,並大抵垂直於鰭結構104a。相似地,鰭式場效電晶體元件100b亦包括多個鰭結構104b及多個閘極電極 110b。
根據一些實施例,虛置閘極電極110d係位於鰭式場效電晶體元件100a與100b之間。虛置閘極電極110d可用以減少圖案負載效應(pattern-loading effect)(或疏密效應,iso-dense effect)。虛置閘極電極110d係設計成不與鰭結構104a及104b或閘極電極110a及110b電性連接。如第2A圖所示,每一鰭結構104a具有接近虛置閘極電極110d之鰭末端(fin terminal)105a。虛置閘極電極110d與鰭末端105a相隔一間隔D。由於電子構件之積成密度藉著持續縮減最小特徵尺寸而持續增加,鰭末端105a與虛置閘極電極110d之間的間隔D因而變得更小。在一些實施例中,間隔D之長度係介於約10奈米至約120奈米之間。
根據一些實施例,第2B圖為半導體元件10的剖面圖,其係取自第2A圖中之切線b-b。根據一些實施例,第2C圖為半導體元件10的剖面圖,其係取自第2A圖中之切線c-c。在一些實施例中,閘極介電層106及閘極電極層(例如,多晶矽層)相繼沉積於隔離結構108及鰭結構(包括鰭結構104a及104b)之上。之後,形成圖案化硬遮罩112a及112b於閘極電極層之上。接著,使用蝕刻製程部分移除閘極電極層及閘極介電層106。因此,形成了數個閘極堆疊(gate stacks)。閘極堆疊包括閘極介電層106及閘極電極110a及110b。虛置閘極電極110d亦形成於隔離結構108之上。
如第2B圖所示,在一些實施例中,閘極電極110a及虛置閘極電極110d的輪廓係大抵相同。在一些其他實施例中,閘極電極110a之輪廓較虛置閘極電極110d之輪廓更為錐狀化 (tapered)。
然而,因為間隔D很小,殘留物(residue)117可能留在虛置閘極電極110d與鰭結構104a之鰭端點105a之間。殘留物117可能來自閘極電極層之未完全移除的材料,或是在蝕刻製程期間因再沉積(re-deposited)而產生。在一些實施例中,殘留物117直接接觸虛置閘極電極110d及鰭結構104a。在一些實施例中,殘留物117亦形成於虛置閘極電極110d與鰭結構104b之間並與之直接接觸(見第2A圖)。因此,鰭結構104a與104b之間可能透過虛置閘極電極110d及殘留物117而形成短路,其導致良率下降。
在一些實施例中,隨著間隔D持續縮小,上述問題更為嚴重。因此,為了減少或解決上述問題,可找尋形成具有鰭式場效電晶體元件之半導體元件的替代實施例。
根據一些實施例,第3A-3C圖顯示之半導體元件30的製程上視圖。根據一些實施例,第4A-4D圖顯示半導體元件30的製程剖面圖(其取自第3A-3C圖中之切線I-I)。根據一些實施例,第5A-5D圖顯示半導體元件30的製程剖面圖(其取自第3B-3C圖中之切線J-J)。
如第3A及4A圖所示,根據一些實施例,鰭結構104a及104b係形成於基底102之上。在一些實施例中,藉著先於基底102上沉積並圖案化出硬遮罩層(未顯示),將基底102蝕刻以形成出鰭結構104a及104b。硬遮罩層形成出覆蓋部分基底102之圖案。之後,蝕刻基底102以於被硬遮罩層所覆蓋之區域之間形成溝槽。因此,於溝槽之間形成出鰭結構104a及104b。
如第3A及4A圖所示,在一些實施例中,將隔離結構108形成於溝槽之中以圍繞鰭結構104a及104b。將介電材料(例如,氧化矽)沉積進溝槽中並覆蓋鰭結構104a及104b。之後,將介電材料平坦薄化化至鰭結構104a及104b或硬遮罩之頂表面,並接著將介電材料蝕刻至低於鰭結構104a及104b之頂表面的高度。因而,鰭結構104a及104b之較高部分突出於隔離結構108之上,而鰭結構104a及104b之較低部分由隔離結構108所圍繞及覆蓋,如第4A圖所示。
或者,隔離結構108係先形成在基底102之上。於隔離結構108之間形成溝槽已露出基底102。接著,於溝槽中例如藉著使用磊晶製程(epitaxial process)成長半導體材料(例如,矽、矽鍺、或其他可應用材料)以形成鰭結構104a及104b。在鰭結構104a及104b成長至所需高度後,將隔離結構108回蝕刻至低於鰭結構104a及104b之頂表面的高度。因此,部分的鰭結構104a及104b突出於隔離結構108,如第4A圖所示。
請參照第3B及5A圖,在一些實施例中,於鰭結構104a及104b及隔離結構108之上形成閘極介電層106及閘極電極層310。在一些實施例中,閘極電極層310由多晶矽所形成。閘極電極層310可藉著使用化學氣相沉積(chemical vapor deposition,CVD)製程或其他可應用製程而形成。
閘極電極層310及閘極介電層106將被圖案化以形成橫越鰭結構104a及104b之閘極堆疊(gate stacks)。如第4B及5B圖所示,在一些實施例中,於閘極電極層310之上形成一或多層之硬遮罩。在一些實施例中,於閘極電極層310之上形成 硬遮罩112a及112b之堆疊。硬遮罩112a可由氧化矽、氮化矽、氮氧化矽、或其他可應用材料形成。硬遮罩112b可由氧化矽、氮化矽、氮氧化矽、或其他可應用材料形成。硬遮罩112a及112b形成覆蓋部分閘極電極層310之圖案,有助於後續形成閘極電極之圖案化製程。
在一些實施例中,對閘極電極層310進行多次蝕刻處理(multiple etching operations)以形成閘極電極。如第4C及5C圖所示,在一些實施例中,進行第一蝕刻處理以部分移除閘極電極層310之較高部分。閘極電極層310之較高部分可高於鰭結構104a及104b。例如,將閘極電極層310部分蝕刻,直至露出鰭結構104a及104b頂表面上之閘極介電層106。
第一蝕刻處理可於製程反應室(process chamber)中進行。在一些實施例中,第一蝕刻處理所使用之蝕刻劑包括Cl2、SF6、N2、CF4、CHF3、CH2F2、N2H2、O2、He、其他適合的蝕刻劑、或前述之組合。製程反應室之壓力可維持於約1mtorr至約40mtorr。第一蝕刻處理之製程溫度可維持於約10℃至約50℃。第一蝕刻處理之偏壓功率可為約100W至約1000W。
如第3C、4D、及5D圖所示,在一些實施例中,進行第二蝕刻處理以部分移除閘極電極層310之較低部分,因而形成閘極電極310a及310b及虛置閘極電極310d。在一些實施例中,第二蝕刻處理與第一蝕刻處理係於相同的製程反應室中進行。可將製程反應室抽真空,而可在第二蝕刻處理進行前,移除第一蝕刻製程中所使用之蝕刻劑。在一些實施例中,對基底 102施加偏壓。因此,第二蝕刻處理中所使用之蝕刻劑可受到導引而主要蝕刻閘極電極層310之較低部分。閘極電極層310之較高部分大抵維持已於第一蝕刻製程中所形成之輪廓。因此,形成了閘極電極310a及310b及虛置閘極電極310d。
在一些實施例中,於第二蝕刻處理中所使用的蝕刻劑包括Cl2、BCl3、N2、CF4、CHF3、CH2F2、N2H2、O2、其他適合的蝕刻劑、或前述之組合。製程反應室之壓力可維持於約1mtorr至約10mtorr。第二蝕刻處理之製程溫度可維持於約10℃至約50℃。第二蝕刻處理中所使用之偏壓功率可為約100W至約1000W。
在第二蝕刻處理中,透過調整製程參數以控制虛置閘極電極310d之輪廓。在一些實施例中,第二蝕刻處理中結合使用許多種蝕刻劑。例如,Cl2用做第一蝕刻劑,而CHF3及/或CH2F2用做第二蝕刻劑。在一些實施例中,藉著調整第一蝕刻劑與第二蝕刻劑之含量比例,控制虛置閘極電極310d之輪廓。例如,藉著提升第一蝕刻劑之含量,可提升橫向蝕刻速度(lateral etching rate)。因此,虛置閘極電極310d之底部部分可更為凹陷。亦可調整其他製程參數以控制虛置閘極電極310d之輪廓。
如第4D及5D圖所示,在一些實施例中,凹陷314係形成在虛置閘極電極310d的較低部分處。凹陷314延伸自虛置閘極電極310d之較高部分的側壁316。即,虛置閘極電極310d於其較低部分是凹陷的。如第4D及5D圖所示,虛置閘極電極310d於接近虛置閘極電極310d之頂部312處具有寬度W1。虛置 閘極電極310d還於接近基底102處具有寬度W3。虛置閘極電極310d之具有寬度W2的部分係介於具有寬度W1與W3的部分之間。寬度W1大於寬度W3
寬度W1可為約10nm至約40nm。寬度W3可為約5nm至約30nm。在一些實施例中,寬度W3對寬度W1之比例(W3/W1)為約1/8至約3。在一些實施例中,寬度W2大於寬度W3,並小於寬度W1。在一些實施例中,寬度W2大抵等於寬度W3。在一些實施例中,虛置閘極電極310d之較低部分具有垂直的側壁317。側壁317可大抵平行於虛置閘極電極310d之較高部分的側壁316。在一些其他實施例中,側壁317具有曲表面(curved surface)。
如第4D圖所示,虛置閘極電極310d於較低部分處縮窄。相較於第2C圖所顯示結構的間隔D,於其中一鰭結構104a之鰭末端105a與虛置閘極電極310d之側壁317之間的間隔D’更為擴大。在一些實施例中,間隔D’的長度為約10nm至約120nm。因為間隔D’較大,較少的殘留物形成於虛置閘極電極310d與鰭結構104a之鰭末端105a之間。鰭結構104a與虛置閘極電極310d之間的短路現象可顯著地減少或避免。相似地,虛置閘極電極310d與鰭結構104b之鰭末端105b之間的間隔亦增大。鰭結構104b與虛置閘極電極310d之間的短路現象亦可顯著地減少或避免。因此,相較於第2C圖所示之實施例,鰭結構104a與104b之間透過虛置閘極電極310d而發生短路的可能性可減小。
如第5D圖所示,在一些實施例中,閘極電極310a及310b具有垂直的側壁。可能沒有凹陷形成於閘極電極310a及 310b之側壁。本揭露書之實施例不限於此。在一些其他實施例中,閘極電極310a及310b具有傾斜的側壁(inclined sidewalls)。在一些實施例中,虛置閘極電極310d之底部輪廓(較低部分之輪廓)相較於閘極電極310a及310b更為凹陷。
如第4D及5D圖所示,在一些實施例中,移除閘極介電層106之未被閘極電極310a及310b及虛置閘極電極310d所覆蓋之部分。可進行蝕刻製程以部分移除閘極介電層106,因而露出部分的鰭結構104a及104b。
可接著進行一些製程以完成半導體元件30之製作。如第3C圖所示,在一些實施例中,進行許多製程以形成半導體元件30之鰭式場效電晶體元件300a及300b。
在一些實施例中,接著對鰭結構104a及104b非位於閘極結構下之部分摻雜以形成淺摻雜源極/汲極區(LDS/D)(未顯示)。所使用之摻質(dopant)取決於電晶體之導電型態。淺摻雜源極/汲極區可藉著離子佈植(ion-implantation)或電漿摻雜(plasma doping)而形成,其中摻質被沉積至鰭結構104a及104b之上且進入鰭結構104a及104b中,並接著被退火(annealed)。類似於第1圖所示之結構,亦可於橫越在鰭結構104a及104b上之閘極電極310a及310b的兩側處,於鰭結構104a及104b上形成源極/汲極區(S/D)(未顯示)。源極/汲極區可藉由離子佈植製程而形成。或者,可移除部分的鰭結構104a及104b形成凹陷,並在摻雜條件下於凹陷中重新磊晶成長以形成源極/汲極區。
在一些實施例中,進行閘極置換製程(或後閘極製 程)而以金屬材料取代閘極電極310a及310b中之多晶矽。金屬材料包括功函數材料(work function material)。在這些情形中,閘極電極310a及310b包括一或多種金屬材料。虛置閘極電極310d亦可以金屬材料取代。因此,虛置閘極電極310d亦可包括一或多種金屬材料。
如前所述,閘極電極及虛置閘極電極之輪廓可藉由調變蝕刻製程條件而調整。根據一些實施例,第6A-6B圖顯示半導體元件30’之剖面圖,其相似於第4D及5D圖所示之結構。
如第6A圖所示,半導體元件30’包括閘極電極310a’及310b’,其橫越於鰭結構104a及104b之上。在一些實施例中,虛置閘極電極310d位於閘極電極310a’及310b’之間。虛置閘極電極310d’亦位於鰭結構104a及104b之間。
如前所述,在一些實施例中,於第二蝕刻處理中,Cl2被用做第一蝕刻劑,而CHF3及/或CH2F2被用做第二蝕刻劑。相較於第4D圖所述之實施例,在一些實施例中,更大量地使用第二蝕刻劑。因此,可獲得第6A圖所示之輪廓。虛置閘極電極310d’之較低部分具有傾斜的側壁317’,而虛置閘極電極310d’之較高部分具有大抵垂直的側壁316’。凹陷314’形成自側壁316’,且朝內向虛置閘極電極310d’之中心延伸。
如第6A圖所示,在一些實施例中,虛置閘極電極310d’於較低部分逐漸縮窄。虛置閘極電極310d’之寬度W2’逐漸縮減為底部部分的寬度W3’。因此,相較於第2C圖所顯示結構的間隔D,於其中一鰭結構104a之鰭末端105a與虛置閘極電 極310d’之側壁317’之間的間隔D”更為擴大。因此,相較於第2C圖所示之實施例,鰭結構104a與104b之間透過虛置閘極電極310d’而發生短路的可能性可減小。
如第6B圖所示,在一些實施例中,閘極電極310a’具有傾斜的側壁319。在一些實施例中,閘極電極310a’之寬度W4逐漸增加至底部部分的寬度W5。寬度W5較虛置閘極電極310d’之寬度W3’還寬。在傾斜側壁319與閘極電極310a’之底部的延伸平面之間夾有角度θ1。在一些實施例中,角度θ1大於約90度。在側壁317’與虛置閘極電極310d’之底部的延伸平面之間夾有角度θ2。在一些實施例中,角度θ2小於角度θ1,且不大於約90度。在一些其他實施例中,角度θ1小於約90度。在這些情形下,在一些實施例中,角度θ2仍小於角度θ1。在一些實施例中,角度θ1與角度θ2之間的角度差異(angle difference,θ12)為約0.1度至約90度。在一些其他實施例中,角度θ1與角度θ2彼此相同。
本揭露書之實施例具有許多變化。例如,側壁317’及/或側壁319不限於是平坦表面。在一些其他實施例中,其中一或全部的側壁317’及319具有曲表面(curved surface)。
根據一些實施例,提供了形成包含鰭式場效電晶體元件之半導體元件的方法。藉著對閘極電極層進行包括多次蝕刻處理之蝕刻製程,可形成橫越鰭結構之閘極電極及一或多個位於鰭結構之間的虛置閘極電極。蝕刻處理經調整而可用以控制虛置閘極電極之較低部分的輪廓。虛置閘極電極於較低部分處縮窄。凹陷係形成於虛置閘極電極之較低部分處。因此, 鰭結構之鰭末端與虛置閘極電極之底部之間的間距可擴大。鰭結構與虛置閘極電極之間的短路現象可減少或避免。半導體元件之良率與可靠度可因而增進。
根據一些實施例,提供了一種半導體元件。半導體元件包括基底。半導體元件還包括位於基底上之第一鰭結構及第二鰭結構。半導體元件更包括分別橫越於第一鰭結構及第二鰭結構上之第一閘極電極及第二閘極電極。此外,半導體元件包括介於第一鰭結構與第一閘極電極之間,且介於第二鰭結構與第二閘極電極之間的閘極介電層。再者,半導體元件包括位於基底上之虛置閘極電極。虛置閘極電極位於第一閘極電極與第二閘極電極之間,且虛置閘極電極之較高部分寬於虛置閘極電極之較低部分。
根據一些實施例,提供了一種半導體元件。半導體元件包括基底。半導體元件還包括位於基底上之第一鰭結構及第二鰭結構。半導體元件更包括分別橫越於第一鰭結構及第二鰭結構上之第一閘極電極及第二閘極電極。此外,半導體元件包括介於第一鰭結構與第一閘極電極之間,且介於第二鰭結構與第二閘極電極之間的閘極介電層。再者,半導體元件包括位於基底上之虛置閘極電極。虛置閘極電極位於第一閘極電極與第二閘極電極之間,且虛置閘極電極之底部部分是凹陷的。
根據一些實施例,提供了一種半導體元件的形成方法。方法包括於基底上形成第一鰭結構及第二鰭結構。方法還包括於第一鰭結構、第二鰭結構、及基底上沉積閘極介電層及閘極電極層。方法更包括進行蝕刻製程以部分移除閘極電極 層,因而形成分別橫越第一鰭結構及第二鰭結構之第一閘極電極及第二閘極電極,並於基底上及第一鰭結構與第二鰭結構之間形成虛置閘極電極。虛置閘極電極之底部部分是凹陷的。
雖然本揭露書已以數個較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本揭露書之精神和範圍內,當可作任意之更動與潤飾,因此本揭露書之保護範圍當視後附之申請專利範圍所界定者為準。
30‧‧‧半導體元件
102‧‧‧基底
104a、104b‧‧‧鰭結構
105a、105b‧‧‧鰭末端
106‧‧‧閘極介電層
108‧‧‧隔離結構
112a、112b‧‧‧硬遮罩
310a、310b‧‧‧閘極電極
310d‧‧‧虛置閘極電極
312‧‧‧頂部
314‧‧‧凹陷
316、317‧‧‧側壁
D’‧‧‧間隔
W1、W2、W3‧‧‧寬度

Claims (10)

  1. 一種半導體元件,包括:一基底;一第一鰭結構及一第二鰭結構,位於該基底之上;一第一閘極電極及一第二閘極電極,分別橫越於該第一鰭結構及該第二鰭結構之上;一閘極介電層,介於該第一鰭結構與該第一閘極電極之間,且介於該第二鰭結構與該第二閘極電極之間;以及一虛置閘極電極,位於該基底之上,其中該虛置閘極電極位於該第一閘極電極與該第二閘極電極之間,且該虛置閘極電極之一較高部分寬於該虛置閘極電極之一較低部分。
  2. 如申請專利範圍第1項所述之半導體元件,其中該第一閘極電極之一較低部分的一側壁與該第一閘極電極之一底部之一延伸平面之間夾有一第一角度,且該虛置閘極電極之該較低部分之一側壁與該虛置閘極電極之一底部之一延伸平面之間夾有一第二角度,該第一角度大於該第二角度。
  3. 如申請專利範圍第1項所述之半導體元件,其中該第一閘極電極之該較低部分寬於該虛置閘極電極之該較低部分。
  4. 一種半導體元件,包括:一基底;一第一鰭結構及一第二鰭結構,位於該基底之上;一第一閘極電極及一第二閘極電極,分別橫越於該第一鰭結構及該第二鰭結構之上;一閘極介電層,介於該第一鰭結構與該第一閘極電極之間, 且介於該第二鰭結構與該第二閘極電極之間;以及一虛置閘極電極,位於該基底之上,其中該虛置閘極電極位於該第一閘極電極與該第二閘極電極之間,且一凹陷位於該虛置閘極結構之一較低部分處。
  5. 如申請專利範圍第4項所述之半導體元件,其中該虛置閘極之該較低部分具有一側壁,該側壁具有一曲表面。
  6. 如申請專利範圍第4項所述之半導體元件,其中該虛置閘極電極之該較低部分之一側壁與該虛置閘極電極之一底部之一延伸平面之間夾有一角度,且該角度不大於約90度。
  7. 一種半導體元件的形成方法,包括:於一基底上形成一第一鰭結構及一第二鰭結構;於該第一鰭結構、該第二鰭結構、及該基底上沉積一閘極介電層及一閘極電極層;以及進行一蝕刻製程以部分移除該閘極電極層,以形成分別橫越該第一鰭結構及該第二鰭結構之一第一閘極電極及一第二閘極電極,並於該基底上及該第一鰭結構與該第二鰭結構之間形成一虛置閘極電極,其中該虛置閘極電極之一底部部分是凹陷的。
  8. 如申請專利範圍第7項所述之半導體元件的形成方法,其中該蝕刻製程包括:進行一第一蝕刻處理以部分移除該閘極電極層之一較高部分;以及進行一第二蝕刻處理以部分移除該閘極電極層之一較低部分。
  9. 如申請專利範圍第8項所述之半導體元件的形成方法,其中該第二蝕刻處理使用了一第一蝕刻劑及一第二蝕刻劑。
  10. 如申請專利範圍第8項所述之半導體元件的形成方法,其中在該第二蝕刻處理期間,該基底被施加了一偏壓。
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