TW201310545A - Method for forming oxide semiconductor film, semiconductor device, and method for manufacturing semiconductor device - Google Patents

Abstract

The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.

Description

Method of forming oxide semiconductor film, semiconductor device, and method of manufacturing the same

The present invention relates to a method of forming an oxide semiconductor film and a method of fabricating a semiconductor device.

In this specification, a semiconductor device means a general-purpose device that can function by utilizing semiconductor characteristics, and the electro-optical device, the semiconductor circuit, and the electronic device are all semiconductor devices.

A technique for forming a transistor by using a semiconductor film formed on a substrate (having an insulating surface) has been attracting attention. Such a transistor is applied to a wide range of electronic devices such as an integrated circuit (IC) and an image display device (display device). As a material of a semiconductor thin film which can be applied to such a transistor, a germanium-based semiconductor material has been widely used, but an oxide semiconductor as an alternative material has attracted attention.

For example, an active layer whose active layer is formed by using an oxide semiconductor containing In, Ga, and Zn and having an electron carrier concentration of less than 10 ¹⁸ /cm ³ is disclosed, and sputtering is considered to be most suitable as A method of forming a film of the oxide semiconductor (see Patent Document 1).

[references]

[Patent Document 1] Japanese Laid-Open Patent Application No. 2006-165528

Some cases have been formed by using an oxide semiconductor The body is inferior to the transistor formed by the use of amorphous germanium in terms of reliability. In the present invention, a semiconductor device including a highly reliable transistor formed by using an oxide semiconductor is provided.

Further, a method of forming an oxide semiconductor film, which can be used to provide such a semiconductor device, is described.

Impurities (such as hydrogen, nitrogen, and carbon) contained in the oxide semiconductor film may cause disadvantageous semiconductor characteristics of the oxide semiconductor film.

For example, hydrogen and nitrogen contained in the oxide semiconductor film generate carriers in the oxide semiconductor film. Therefore, hydrogen and nitrogen in the oxide semiconductor film included in the transistor may cause the transistor threshold voltage to shift in the negative direction, resulting in a decrease in reliability of the transistor.

Further, nitrogen, carbon, and a rare gas contained in the oxide semiconductor film may suppress formation of a crystalline region in the oxide semiconductor film in some cases. For example, the nitrogen molecules and the carbon dioxide molecules have a large diameter; therefore, formation of a crystalline region in the oxide semiconductor film is particularly suppressed. Further, when a carbon atom is substituted by a metal atom in the oxide semiconductor film, the crystal structure is cut at a position where the substitution occurs.

This is why it is important to obtain an oxide semiconductor film containing a small amount of impurities in order to manufacture a highly reliable transistor.

Specifically, the hydrogen concentration in the oxide semiconductor film measured by secondary ion mass spectrometry (SIMS) is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably lower than or equal to 5 × 10 ¹⁸ atoms / Cm ³ , more preferably lower than or equal to 1 × 10 ¹⁸ atoms/cm ³ , still more preferably lower than or equal to 5 × 10 ¹⁷ atoms/cm ³ .

The nitrogen concentration in the oxide semiconductor film measured by SIMS is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably lower than or equal to 5 × 10 ¹⁸ atoms / cm ³ , more preferably lower than or equal to 1 × 10 ¹⁸ atoms/cm ³ , more preferably lower than or equal to 5 × 10 ¹⁷ atoms/cm ³ .

The carbon concentration in the oxide semiconductor film measured by SIMS is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably lower than or equal to 5 × 10 ¹⁸ atoms / cm ³ , more preferably lower than or equal to 1 × 10 ¹⁸ atoms/cm ³ , more preferably lower than or equal to 5 × 10 ¹⁷ atoms/cm ³ .

When electrons are generated due to hydrogen contained in an oxide semiconductor film included in the transistor (including water contained in water or the like) and nitrogen, a drain current can flow in the transistor even if there is no A gate voltage is applied (the transistor is normally open). Note that the drain current means a current flowing between the source and the drain of the transistor, and the gate voltage means a potential difference between the source potential and the gate potential as a reference potential. As a result, the threshold voltage is shifted in the negative direction. A transistor formed by using an oxide semiconductor film may have n-type conductivity, and it has a normally-on characteristic by a shift of a threshold voltage in a negative direction.

Further, the threshold voltage of the transistor formed by using the oxide semiconductor film may be changed due to hydrogen or nitrogen entering the oxide semiconductor film after the transistor is fabricated. The offset of the threshold voltage significantly impairs the reliability of the transistor.

For this reason, the oxide semiconductor film and the hydrogen and nitrogen contained in the film in contact with the oxide semiconductor film need to be reduced to form a highly reliable transistor.

Similarly, electrons are known due to oxygen vacancies in an oxide semiconductor film. Was produced.

In order to prevent oxygen vacancies from being generated in the oxide semiconductor film, it is preferred that the oxide semiconductor film contains oxygen between the crystal lattices. Oxygen between the crystal lattices can fill the oxygen vacancies generated in the oxide semiconductor film.

In the case where the oxide semiconductor film included in the transistor is a single crystal, carriers caused by oxygen vacancies are generated in the oxide semiconductor film because oxygen in the oxygen vacancies between the crystal lattices is lacking; The threshold voltage of the transistor is offset in the negative direction in some cases. Therefore, the oxide semiconductor film is preferably a non-single crystal.

Preferably, a CAAC-OS (c-axis aligned crystalline oxide semiconductor) film can be used as the oxide semiconductor film.

The CAAC-OS film is not completely single crystal or completely non-single crystal. The CAAC-OS film is an oxide semiconductor film having a crystal-amorphous mixed phase structure in which a crystalline region and an amorphous region are included in an amorphous phase. It is noted that in many cases, the crystalline region matches the inside of a cube with a side less than 100 nm. In the observation image obtained by a transmission electron microscope (TEM), the boundary between the amorphous region and the crystallization interval in the CAAC-OS film is not clear. Further, no grain boundaries in the CAAC-OS film were found by TEM. Therefore, in the CAAC-OS film, a decrease in electron mobility caused by grain boundaries is suppressed.

In the crystallization zone included in the CAAC-OS film, the c-axis is aligned in a direction parallel to the normal vector of the surface on which the CAAC-OS film is formed, or aligned with the surface of the CAAC-OS film. The direction in which the line vectors are parallel, the order of the triangles or hexagons viewed from the direction perpendicular to the ab plane is Formed, and the metal atoms are arranged in a layered manner when viewed from a direction perpendicular to the c-axis, or the metal atoms and oxygen atoms are arranged in a layered manner. It is noted that the directions of the a-axis and the b-axis of one crystallization zone may be different from the other crystallization zone. In this specification, the simple term "vertical" means a range of 85° to 95°. Further, the simple term "parallel" means a range of -5 to 5 degrees.

In the CAAC-OS film, the distribution of the crystallization zone is not necessarily uniform. For example, in the case where crystal growth occurs from the surface side of the oxide semiconductor film in the formation process of the CAAC-OS film, in some cases, the ratio of the crystallization region near the surface of the CAAC-OS film is higher than that of the CAAC- The ratio of the crystalline regions near the surface on which the OS film is formed. Further, when an impurity is added to the CAAC-OS film, the crystallization region in the region where the impurity is added becomes amorphous in some cases.

The c-axis of the crystalline region included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the surface on which the CAAC-OS film is formed, or aligned with the surface of the CAAC-OS film. The direction in which the line vectors are parallel may be different from each other depending on the shape of the CAAC-OS film (the cross-sectional shape of the surface on which the CAAC-OS film is formed or the cross-sectional shape of the surface of the CAAC-OS film) . Note that when the CAAC-OS film is formed, the direction of the c-axis of the crystallization region is a direction parallel to the normal vector of the surface on which the CAAC-OS film is formed, or the surface of the CAAC-OS film. The direction in which the line vectors are parallel. The crystallization zone is formed by deposition or by performing a treatment for crystallization after deposition.

Visible in a transistor formed by using a CAAC-OS film The change in electrical characteristics caused by light or ultraviolet light irradiation can be reduced. Therefore, the transistor has high reliability.

In order to improve the crystallinity of the oxide semiconductor film, the following factors are important: the flatness of the surface on which the oxide semiconductor film is formed and the method of forming the oxide semiconductor film.

Specifically, the surface on which the oxide semiconductor film is formed has an average surface roughness (R _a ) of nm or lower, preferably 0.3 nm or lower, more preferably 0.1 nm or lower.

Further, the oxide semiconductor film is preferably formed by sputtering while the substrate is heated in an oxygen atmosphere. The entrance of impurities, which suppresses the formation of a crystalline region in the oxide semiconductor film, is suppressed as much as possible during film formation.

A specific example of the impurity which suppresses the formation of the crystallization region in the oxide semiconductor film is carbon dioxide. In addition, large diameter atoms or molecules, nitrogen, carbon monoxide, and hydrocarbons of some rare gases (helium, helium, argon, helium, and neon) may also inhibit the formation of crystalline regions in the oxide semiconductor film. Impurities.

In order to prevent the above impurities from entering the oxide semiconductor film, it is necessary to reduce impurities in the target, the deposition gas, and the deposition chamber.

Specifically, a deposition gas having a purity of 8 N or higher, preferably 9 N or higher, can be used.

The impurities present in the deposition chamber can be reduced in the following manner.

The impurities present in the deposition chamber depend on the balance between the amount of gas reduced from the deposition chamber and the amount of gas leaking into the deposition chamber. Therefore, preferred Yes, the amount of gas reduced from the deposition chamber is large and the amount of gas leaking into the deposition chamber is small.

The amount of gas reduced from the deposition chamber depends on the type and capacity of the vacuum pump and the length and thickness of the tubing connected to the vacuum pump. For example, as the line connected to the vacuum pump is shorter and thicker, a larger amount of gas can be reduced.

Further, the parallel connection of different types of vacuum pumps allows for a reduction in various gases. For example, it is preferred to use a turbo molecular pump and a cryopump that are connected in parallel.

Alternatively, the same kind of vacuum pumps can be connected in parallel. For example, in the case where two cryopumps are connected in parallel, when one of the cryopumps is in regeneration, evacuation can be performed by using another vacuum pump. Therefore, the downtime of the apparatus in the regeneration of the cryopump can be reduced, resulting in an increase in productivity. Further, when evacuation is performed by using a plurality of vacuum pumps together, higher evacuation performance can be achieved.

In addition, it is also necessary to reduce the amount of gas leaking into the deposition chamber.

Leakage into the deposition chamber includes internal leakage caused by impurities adsorbed to the inner wall of the deposition chamber and external leakage from the sealed portion.

For example, in order to remove impurities adsorbed to the inner wall of the deposition chamber, evacuation may be performed while the deposition chamber is heated. Heating the deposition chamber allows impurities adsorbed to the inner wall of the deposition chamber to be desorbed; therefore, impurities can be efficiently removed.

Further, it is preferable to form a virtual film. It is noted that the virtual film formation means film formation on a virtual substrate, wherein a film is deposited on the dummy substrate The inner walls of the plates and the deposition chamber are such that impurities in the deposition chamber and adsorbents on the inner walls of the deposition chamber are confined in the film. The dummy film formation can be performed while the deposition chamber is heated.

In order to remove impurities present in the deposition chamber, it is preferred that heated oxygen or a heated inert gas such as heated rare gas, or the like, is supplied to increase the pressure in the deposition chamber and after passing a certain section After the time, the process for evacuating the deposition chamber is carried out. Supplying the heated gas allows the adsorbed impurities in the deposition chamber to be desorbed from the deposition chamber, so that impurities in the deposition chamber can be reduced. It is noted that it is effective to repeatedly perform this process. A gas heating system may be provided in the deposition apparatus itself to supply heated oxygen or a heated inert gas such as a heated rare gas. The provision of a gas heating system in the deposition apparatus makes it possible to reduce the piping distance between the gas heating system and the deposition chamber or the like; therefore, the gas can be maintained at a high temperature supply into the deposition chamber.

By the above method, the leak rate is 3 × 10 ^-5 Pa. m ³ /s or lower, preferably 1 × 10 ^-5 Pa. m ³ /s or lower, more preferably 3×10 ^-6 Pa. m ³ /s or lower, and more preferably 1 × 10 ^-6 Pa. m ³ /s or lower, and more preferably 3×10 ^-7 Pa. m ³ /s or lower.

Note that the gas with a mass-to-charge ratio (m/z) of 28 (for example, nitrogen molecules) has a leak rate of 1 × 10 ^-5 Pa. m ³ /s or lower, preferably 3 × 10 ^-6 Pa. m ³ /s or lower.

Note that the gas with a mass-to-charge ratio (m/z) 44 (for example, carbon oxide molecules) has a leakage rate of 3 × 10 ^-6 Pa. m ³ /s or lower, preferably 1 × 10 ^-6 Pa. m ³ /s or lower.

Note that the gas with a mass-to-charge ratio (m/z) of 18 (for example, water molecules) has a leak rate of 1 × 10 ^-7 Pa. m ³ /s or lower, preferably 3 × 10 ^-8 Pa. m ³ /s or lower.

Further, by the above method, the pressure in the deposition chamber is specifically 1×10 ⁻⁴ Pa or lower, preferably 3×10 ⁻⁵ Pa or lower, more preferably 1×10 ⁻⁵ Pa or Lower.

In the deposition chamber under such conditions, an oxide semiconductor film is formed.

It is noted that in forming the oxide semiconductor film, impurities adsorbed onto the surface of the oxide semiconductor film to be formed are preferably removed in advance.

Specifically, the plasma treatment and/or the heat treatment may be performed to remove impurities adsorbed onto the surface of the oxide semiconductor film to be formed. It is noted that the plasma treatment and the heat treatment are preferably carried out in a reduced pressure atmosphere. The reduced pressure atmosphere in this specification means an atmosphere having a pressure of 10 Pa or less, 1 Pa or less, 1 × 10 ^-2 Pa or less, or 1 × 10 ^-4 Pa or less.

Preferably, after the treatment for removing impurities adsorbed onto the surface of the oxide semiconductor film to be formed, the substrate is transferred (without exposure to air) to the oxide semiconductor film The deposition chamber is such that the impurities are not adsorbed onto the surface of the oxide semiconductor film to be formed.

Here, the oxide semiconductor film preferably has a substrate heating temperature of 100 ° C (inclusive) to 650 ° C (inclusive), preferably 150 ° C (inclusive) to 600 ° C (inclusive), more preferably 200 ° C (inclusive) to 500. It is formed under the conditions of °C (inclusive). When the substrate heating temperature falls within the above range, the impurity concentration in the oxide semiconductor film can be reduced, and the oxide semiconductor film may have high crystallinity.

After the formation of the oxide semiconductor film, heat treatment is preferably carried out. The heat treatment is carried out at 250 ° C to 650 ° C (including), preferably 300 ° C to 600 ° C (including) in an inert atmosphere, a reduced pressure atmosphere, or an oxidizing atmosphere. Through this heat treatment, the impurity concentration in the oxide semiconductor film can be reduced, and the oxide semiconductor film may have high crystallinity.

The transistor formed by using the oxide semiconductor film formed in the foregoing manner has high reliability and a small variation in threshold voltage.

It is possible to provide an oxide semiconductor film from which impurities such as hydrogen, nitrogen, and carbon are reduced and which have low carrier density and high crystallinity.

By using the oxide semiconductor film, a transistor having high reliability and a small variation in threshold voltage can be provided.

By using the transistor, a semiconductor device having high reliability and excellent characteristics can be provided.

Hereinafter, embodiments and examples of the invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the following description, and those skilled in the art will readily appreciate that the modes and details disclosed herein may be varied in various ways. Further, the present invention should not be construed as being limited to the description of the embodiments and the examples. In describing the structure of the present invention with reference to the drawings, common element symbols are used in the same parts in different drawings. It is noted that the same hatched pattern is applied to similar components, and in some cases such similar components are not specifically represented by component symbols.

It is noted that the ordinal numbers such as "first" and "second" in this specification are used for convenience and do not indicate the order of steps or the stacking order of layers. In addition, the ordinal numbers in this specification are not intended to indicate the specific names of the present invention.

(Example 1)

In this embodiment, a method of forming an oxide semiconductor film containing a small amount of impurities and a transistor formed by using the oxide semiconductor film will be described.

First, the structure of a deposition apparatus that allows a small amount of impurities to enter during film formation will be described by using FIGS. 1A and 1B.

Figure 1A shows a multi-chamber deposition apparatus. The deposition apparatus includes a substrate supply chamber 11, three latching gates 14 for supporting the substrate, load lock chambers 12a and 12b, a transfer chamber 13, a substrate heating chamber 15, and deposition chambers 10a, 10b, and 10c. The substrate supply chamber 11 is connected to the load lock chambers 12a and 12b. The load lock chambers 12a and 12b are connected to the transfer chamber 13. The substrate heating chamber 15 and the deposition chambers 10a to 10c are each connected only to the transfer chamber 13. A gate valve is provided for the connection portion between the chambers so that the respective chambers can be independently held in a vacuum. Although not shown, the transfer chamber 13 has one or more substrate transfer robot arms. Here, the substrate heating chamber 15 is preferably also used as a plasma processing chamber. With a single-wafer multi-chamber deposition apparatus, the substrate does not need to be exposed to air between treatments, and impurities are adsorbed to the substrate can be suppressed. Further, the order of film formation, heat treatment, or the like can be freely determined. Note that the number of deposition chambers, the number of load lock chambers, and the number of substrate heating chambers are not limited to the above, and may be appropriately determined by visual placement space or process. set.

An example of a deposition chamber (sputter chamber) shown in Fig. 1A will be described with reference to Fig. 2A. The deposition chamber 10 includes a target 32, a target holder 34 for supporting the target, a substrate holder 42 for supporting the substrate (which is embedded in the substrate heater 44), and a shutter plate 48 (capable of being able to wrap around) The plate shaft 46 rotates). The target bracket 34 is connected to an RF power source 50 for supplying power via the matching box 52. The deposition chamber 10 is connected to a gas supply source 56 via a purifier 54 and is connected to a vacuum pump 58 and a vacuum pump 59. Here, the deposition chamber 10, the RF power source 50, the shutter shaft 46, the shutter 48, and the substrate holder 42 are grounded. It is noted that one or more of deposition chamber 10, baffle shaft 46, baffle 48, and substrate support 42 may be in a floating state depending on the application.

Further, the number of vacuum pumps is not limited to two (vacuum pumps 58 and 59), and three or more vacuum pumps may be provided or only one of the vacuum pumps may be provided. For example, another vacuum pump can be placed in series with the vacuum pump 58.

As the vacuum pumps 58 and 59, a rough vacuum pump (such as a dry pump) and a high vacuum pump (such as a sputter ion pump, a turbo molecular pump, and a cryopump) can be used in a suitable combination. It is known that a turbomolecular pump is capable of stably removing a gas of a large diameter atom or molecule, requires a low maintenance frequency, and thus can have high productivity, and vice versa has a low performance in removing hydrogen and water. Therefore, a combination of a cryopump (having high performance in removing atoms or molecules having a relatively high melting point such as water) and a sputter ion pump (high performance in removing highly reactive atoms or molecules) are effective. . Enter one In the step, a turbomolecular pump provided with a cryotrap can be used for the vacuum pump. The temperature of the freezer of the cryotrap is 100 K or less, preferably 80 K or less. In the case where the cryotrap comprises a plurality of chillers, it is preferred to set the temperatures of the chillers at different temperatures, as efficient vacuuming is possible. For example, the temperatures of the first-stage chiller and the second-stage chiller may be set to 100 K or lower and 20 K or lower, respectively.

It is noted that the cryopump is an entrapment pump; therefore, regeneration needs to be performed periodically. Cryopumps are not commonly used in mass production equipment because they are unable to perform vacuuming during regeneration, resulting in low productivity. To solve this problem, two or more cryopumps can be connected in parallel. In the case where two or more cryopumps are connected in parallel, even when one of the cryopumps is in regeneration, evacuation can be performed by using any of the other cryopumps. Alternatively, the cryopump and the turbomolecular pump can be connected in parallel. In this case, for example, the turbomolecular pump is used for evacuation in film formation and the cryopump is used in a process other than film formation, so that the frequency of regeneration can be lowered.

Further, the number of gas supply sources 56 and the number of purifiers 54 can each be plural. For example, the number of deposition gas supply sources and the number of purifiers may each increase depending on the number of deposition gas species. The gas supply source and purifier can be directly connected to the deposition chamber 10. In this case, a mass flow controller for controlling the flow rate of the deposition gas may be disposed between each of the purifiers and the deposition chamber 10. Alternatively, the gas supply source and purifier may be connected to a line between the deposition chamber 10 and the purifier 54.

Wherein the gas heating system is disposed between the purifier 54 and the deposition chamber 10 An example will be described with reference to Figures 38A to 38C. The drawings 38A to 38C each show a detailed structure of connection from the gas supply source 56 to the deposition chamber 10.

Figure 38A shows a structure in which the deposition chamber 10 and the gas heating system 57 are connected via a pipeline, the gas heating system 57 and the mass flow controller 55 are connected via a pipeline, and the mass flow controller 55 and the purifier 54 are connected via a pipeline. And the purifier 54 and the gas supply source 56 are connected via a pipeline.

Figure 38B shows a structure in which the deposition chamber 10 and the mass flow controller 55 are directly connected via a pipeline, the mass flow controller 55 and the gas heating system 57 are connected via a pipeline, and the gas heating system 57 and the purifier 54 are connected via a pipeline. Connected, and the purifier 54 and the gas supply source 56 are connected via a pipeline.

It is noted that a mass flow controller (in the case of using a heater body) that can accurately control even the flow rate of the heated gas is preferably used.

Fig. 38C shows a structure in which the deposition chamber 10 and the gas heating system 57 are connected via a line, the gas heating system 57 and the purifier 54 are connected via a line, and the purifier 54 and the gas supply source 56 are connected via a line.

In the configuration of Fig. 38C, the mass flow controller is not provided, and a gas flow rate control system different from the mass flow controller can be set. Alternatively, a system by which a certain amount of gas is supplied can be provided.

The structure in Fig. 38C can be used, for example, in the case where the gas flow rate is not necessarily controlled with high accuracy. Mass flow controllers require periodic maintenance and replacement of components and are relatively expensive. Therefore, there is no mass flow control The structure in Figure 38C of the device allows for a reduction in the cost of the device.

For example, the structure in Fig. 38C can be used to reduce impurities in the deposition chamber 10, and a heated gas (described later) is used in the deposition chamber 10.

The gas to be supplied to the deposition chamber 10 can be heated to 40 ° C (inclusive) to 400 ° C (inclusive), preferably 50 ° C (inclusive) to 200 ° C (inclusive) by the gas heating system 57.

Subsequently, the deposition chamber shown in Fig. 2A will be described. A magnet (not shown) is preferably disposed inside or below the target holder 34 because the high density plasma can be confined to the periphery of the target. By this method called magnetron sputtering, an increase in deposition rate, a decrease in plasma damage on the substrate, and an improvement in film quality can be achieved. When the magnet can be rotated while using the magnetron sputtering method, the non-uniformity of the magnetic field can be suppressed, so that the use efficiency of the target can be increased and the film quality variation in the plane of the substrate can be reduced.

Although an RF power source is used herein as a sputter power source, one embodiment of the present invention is not necessarily limited to an RF power source. The DC power source, the AC power source, or two or more power sources in which switching can be implemented can be set for visual use. In the case where a DC power source or an AC power source is used, a matching box between the power source and the target holder is not necessary.

The substrate holder 42 needs to be provided with a fixture system for supporting the substrate. As the jig system, an electrostatic jig system, a clamping system, and the like can be provided. In order to increase the uniformity of film quality and film thickness in the plane of the substrate, the substrate holder 42 may be provided with a rotating system. Further, a plurality of substrate holders may be disposed in the deposition chamber such that the film shape of the plurality of substrates Cheng can be implemented simultaneously. Further, a structure in which the shutter shaft 46, the shutter 48, and the substrate heater 44 are not disposed can be employed. In the structure of FIG. 2A, the target faces up and the substrates face downward; however, it is also possible to adopt a structure in which the target faces downward and the substrate faces upward, or a target in which the target And the substrate is laterally disposed such that they face each other.

In the substrate heating chamber 15, for example, a resistance heater or the like can be used for heating. Alternatively, heat conduction or heat radiation from a medium such as a heated gas may be used for heating. For example, a rapid thermal annealing (RTA) device such as a gas rapid thermal annealing (GRTA) device or a lamp rapid thermal annealing (LRTA) device can be used. An LRTA device is a device for heating an object by radiation (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. device. In the GRTA apparatus, the heat treatment is carried out by using a high temperature gas. An inert gas is used as the gas.

For example, the substrate heating chamber 15 may have the structure shown in FIG. 2B. In the substrate heating chamber 15, a substrate holder 42 in which the substrate heater 44 is embedded is provided. The substrate heater 15 is connected to the gas supply source 56 via the purifier 54 and is connected to the vacuum pump 58 and the vacuum pump 59. It is noted that instead of a heating system having a substrate heater, the LRTA device can be placed to face the substrate holder. In this case, the reflecting plate can be placed on the substrate holder 42 for efficient heat transfer. Here, in the case where the substrate heating chamber 15 is also used as a plasma processing chamber, the substrate holder 42 is connected to the RF power source 50 via the matching box 52, and the counter electrode 68 is disposed to face the substrate holder 42.

It is noted that the back pressure of each of the deposition chamber 10 and the substrate heating chamber 15 is 1 × 10 ^-4 Pa or lower, preferably 3 × 10 ^-5 Pa or lower, more preferably 1 × 10 ^-5 Pa or lower.

In each of the deposition chamber 10 and the substrate heating chamber 15, the partial pressure of the gas having the mass-to-charge ratio (m/z) 18 is 3 × 10 ^-5 Pa or lower, preferably 1 × 10 ^-5 Pa or more. Low, better 3 x 10 ^-6 Pa or lower.

In each of the deposition chamber 10 and the substrate heating chamber 15, the partial pressure of the gas having the mass-to-charge ratio (m/z) 28 is 3 × 10 ^-5 Pa or lower, preferably 1 × 10 ^-5 Pa or more. Low, better 3 x 10 ^-6 Pa or lower.

In each of the deposition chamber 10 and the substrate heating chamber 15, the partial pressure of the gas having the mass-to-charge ratio (m/z) 44 is 3 × 10 ^-5 Pa or lower, preferably 1 × 10 ^-5 Pa or more. Low, better 3 x 10 ^-6 Pa or lower.

Further, in each of the deposition chamber 10 and the substrate heating chamber 15, the leakage rate is 3 × 10 ^-6 Pa. m ³ /s or lower, preferably 1 × 10 ^-6 Pa. m ³ /s or lower.

In each of the deposition chamber 10 and the substrate heating chamber 15, the gas leakage rate of the gas-to-charge ratio (m/z) 18 is 1 × 10 ^-7 Pa. m ³ /s or lower, preferably 3 × 10 ^-8 Pa. m ³ /s or lower.

In each of the deposition chamber 10 and the substrate heating chamber 15, the gas leakage rate of the gas-to-charge ratio (m/z) 28 is 1 × 10 ^-5 Pa. m ³ /s or lower, preferably 1 × 10 ^-6 Pa. m ³ /s or lower.

In each of the deposition chamber 10 and the substrate heating chamber 15, the gas leakage rate of the gas-to-charge ratio (m/z) 44 is 3 × 10 ^-6 Pa. m ³ /s or lower, preferably 1 × 10 ^-6 Pa. m ³ /s or lower.

The leak rate depends on external and internal leaks. External leakage means the inflow of gas from the outside of the vacuum system via microvias, sealing defects, or the like. The internal leak is due to leakage through a spacer (such as a valve) in the vacuum system or due to gas released from the internal components. It is necessary to obtain measurements from both external leakage and internal leakage so that the leakage rate is lower than or equal to the above value.

For example, the opening/closing portion of the deposition chamber is preferably sealed with a metal gasket. For the metal gasket, a metal material covered with iron fluoride, aluminum oxide, or chromium oxide is preferably used. The metal gasket enables higher adhesion than the O-ring, resulting in reduced external leakage. Further, the release of a gas containing impurities generated from the metal spacer is performed by using a metal material covered with iron fluoride, aluminum oxide, chromium oxide, or the like in a passive state. It will be suppressed so that internal leaks can be reduced.

Aluminum, chromium, titanium, zirconium, nickel, or vanadium (which releases a relatively small amount of impurity-containing gas) is used for the components of the deposition apparatus. Alternatively, an alloy material containing iron, chromium, nickel, and the like covered with the above materials may be used. Alloy materials containing iron, chromium, nickel, and the like are rigid, heat resistant, and suitable for handling. Here, when the surface unevenness of the member is reduced by polishing or the like to reduce the surface area, the release of gas can be reduced.

Alternatively, the above components of the deposition apparatus may be covered with iron fluoride, aluminum oxide, chromium oxide, or the like.

The components of the deposition apparatus are preferably formed by using only a metallic material where possible. For example, by using quartz or similar In the case where the viewing window is provided, the surface is preferably thinly covered with iron fluoride, aluminum oxide, chromium oxide, or the like to suppress the release of gas.

When the purifier for depositing gas is disposed, the length of the line between the purifier and the deposition chamber is less than or equal to 5 m, preferably less than or equal to 1 m. When the length of the line is less than or equal to 5 m or less than or equal to 1 m, the effect of gas release from the line can be correspondingly reduced.

As the piping for depositing a gas, a metal piping whose inside is covered with iron fluoride, aluminum oxide, chromium oxide, or the like is preferably used. With the above piping, the amount of the released gas containing impurities is small and the entry of impurities into the deposition gas may be reduced as compared with, for example, the SUS316L-EP piping. Further, a high performance ultra small metal gasket joint (UPG joint) is preferably used as a joint for the pipeline. A structure in which all of the material of the piping is a metallic material is preferable because the influence of gas release or external leakage may be reduced as compared with a structure in which a resin or the like is used.

The adsorbate does not affect the pressure in the deposition chamber when present in the deposition chamber; however, the adsorbate releases gas when the deposition chamber is evacuated. Therefore, although there is no correlation between the leak rate and the evacuation rate, it is important that the adsorbate present in the deposition chamber is desorbed as much as possible and evacuation is performed in advance by using a pump having high evacuation performance. It is noted that the deposition chamber can be heated to promote desorption of the adsorbate. With this heating, the desorption rate of the adsorbate can be increased by about ten times. This heating can be carried out at a temperature in the range of 100 ° C to 450 ° C. At this time, when the adsorbate is removed while the inert gas is supplied, the desorption rate of water or the like (which is difficult to be desorbed only by vacuuming) can be further increased. Notice when it is to be supplied When the gas is heated to a temperature substantially the same as the heating temperature of the deposition chamber, the desorption rate of the adsorbate can be further increased. Here, the rare gas is preferably used as an inert gas. Depending on the type of film to be formed, oxygen or the like can be used instead of an inert gas. For example, in the case of depositing oxide, the use of oxygen, which is the main component of the oxide, is preferred in some cases.

Alternatively, the treatment for evacuating the deposition chamber is preferably carried out after heated oxygen, heated inert gas (such as heated rare gas), or the like is supplied to increase the pressure in the deposition chamber. time. The supply of heated gas promotes the desorption of the adsorbate in the deposition chamber. It is noted that the positive effect can be achieved when the treatment is repeated 2 to 30 times (including), preferably 5 to 15 times (included). Specifically, an inert gas, oxygen, or the like at a temperature in the range of 40 ° C to 400 ° C, preferably 50 ° C to 200 ° C, is supplied to the deposition chamber such that the pressure therein is maintained at 0.1 Pa to 10 kPa. (included), 1 Pa to 1 kPa (included), or 5 Pa to 100 Pa (included) for 1 minute to 300 minutes (included) or 5 minutes to 120 minutes (included). Thereafter, the deposition chamber is evacuated for 5 minutes to 300 minutes (included) or 10 minutes to 120 minutes (included).

The desorption rate of the adsorbate can also be further increased by the formation of a virtual film. For the dummy substrate, a material that releases a smaller amount of gas is preferably used, and a material such as the substrate 100 (described later) can be used. It is noted that the dummy film formation can be carried out at the same time as the heating of the deposition chamber.

Fig. 1B shows a deposition apparatus having a structure different from that of Fig. 1A. The deposition apparatus includes a load lock chamber 22a, a substrate heating chamber 25, deposition chambers 20a and 20b, and a load lock chamber 22b. The load lock chamber 22a is connected to the substrate heating chamber 25. The substrate heating chamber 25 is connected to the deposition chamber 20a. The deposition chamber 20a is connected to the deposition chamber 20b. The deposition chamber 20b is connected to the load lock chamber 22b. Gate valves are provided for the connection portions between the chambers so that the respective chambers can be independently held in a vacuum state. It is noted that the deposition chambers 20a and 20b have a structure similar to the deposition chambers 10a to 10c in Fig. 1A. The substrate heating chamber 25 has a structure similar to the substrate heating chamber 15 in Fig. 1A. The substrate is transported only in one direction indicated by the arrow of FIG. 1B, and the entrance and exit of the substrate are different. Unlike the single wafer multi-chamber deposition apparatus of Figure 1A, there is no transfer chamber and the footprint can be correspondingly reduced. It is noted that the number of deposition chambers, the number of load lock chambers, and the number of substrate heating chambers are not limited to the above, and may be appropriately determined depending on the placement space or the process. For example, the deposition chamber 20b may be omitted, or a second substrate heating chamber or a third deposition chamber connected to the deposition chamber 20b may be disposed.

When the oxide semiconductor film is formed by using the above deposition apparatus, impurities can be suppressed from entering the oxide semiconductor film. Further, when a film in contact with the oxide semiconductor film is formed by using the above deposition apparatus, impurities can be suppressed from entering the oxide semiconductor film from the film in contact with the oxide semiconductor film.

Next, a method for forming an oxide semiconductor film having a very low concentration of hydrogen, nitrogen, and carbon which is an impurity is provided.

The oxide semiconductor film is heated in an oxygen atmosphere at a substrate heating temperature of 100 ° C to 600 ° C (including), preferably 150 ° C to 550 ° C (including), and more preferably 200 ° C to 500 ° C (included). form. The thickness of the oxide semiconductor film is higher than or equal to 1 nm and less than or equal to 40 nm, preferably higher than or equal to 3 nm and lower than or equal to 20 nm. As the substrate heating temperature at the time of film formation is high, the impurity concentration of the obtained oxide semiconductor film is low. Further, the atomic arrangement in the oxide semiconductor film is ordered and its density is increased, so that a polycrystalline film or a CAAC-OS film may be formed. Further, since an oxygen atmosphere is employed for film formation, unnecessary atoms are not included in the oxide semiconductor film (unlike a rare gas atmosphere or the like), making the polycrystalline film or the CAAC-OS film easy. form. It is noted that a mixed atmosphere of oxygen and a rare gas can be used. In this case, the percentage of oxygen is higher than or equal to 30 vol.%, preferably higher than or equal to 50 vol.%, more preferably higher than or equal to 80 vol.%. As the oxide semiconductor film is thinner, the short channel effect of the transistor can be reduced. However, when the oxide semiconductor film is too thin, it is significantly affected by interface scattering; therefore, field effect mobility may be lowered.

The oxide semiconductor film is formed under the following conditions: a deposition pressure of less than or equal to 0.8 Pa, preferably less than or equal to 0.4 Pa; and a distance between the target and the substrate of less than or equal to 40 mm, preferably less than or equal to 25 mm. When the oxide semiconductor film is formed under such conditions, the collision frequency of the scattering particles with another scattering particle, gas, or ion can be lowered. That is, depending on the deposition pressure, the distance between the target and the substrate is shorter than the average free path of the scattering particles, gas, or ions, so that the impurities enter the The film can be reduced.

For example, when the pressure is 0.4 Pa and the temperature is 25 ° C (absolute temperature is 298 K), the hydrogen molecule (H ₂ ) has an average free path of 48.7 mm, and the helium atom (He) has an average free path of 57.9 mm, water molecules. (H ₂ O) has an average free path of 31.3 mm, the methane molecule (CH ₄ ) has an average free path of 13.2 mm, the germanium atom (Ne) has an average free path of 42.3 mm, and the nitrogen molecule (N ₂ ) has a diameter of 23.2 mm. The mean free path, the carbon monoxide molecule (CO) has an average free path of 16.0 mm, the oxygen molecule (O ₂ ) has an average free path of 26.4 mm, the argon atom (Ar) has an average free path of 28.3 mm, and the carbon dioxide molecule (CO ₂ ) With an average free path of 10.9 mm, the germanium atom (Kr) has an average free path of 13.4 mm and the germanium atom (Xe) has an average free path of 9.6 mm. Note that doubling the pressure will halve the mean free path and doubling the absolute temperature will double the mean free path.

The mean free path depends on pressure, temperature, and the diameter of the atom or molecule. In the case of constant pressure and temperature, the average free path is shorter as the diameter of the atom or molecule is larger. Note that the diameters of the following atoms or molecules are as follows: H ₂ : 0.218 nm; He: 0.200 nm; H ₂ O: 0.272 nm; CH ₄ : 0.419 nm; Ne: 0.234 nm; N ₂ : 0.316 nm; CO: 0.380 nm; O ₂ : 0.296 nm; Ar: 0.286 nm; CO ₂ : 0.460 nm; Kr: 0.415 nm; and Xe: 0.491 nm.

Therefore, as the diameter of the atom or molecule is larger, the average free diameter is shorter, and the growth of the crystal region is suppressed due to the larger diameter of the atom or molecule when the molecule enters the film. For this reason, it can be said that, for example, An atom or molecule having an Ar atom diameter or larger may be regarded as an impurity.

Here, whether or not the crystal structure can be maintained in the case where CO ₂ is added between the In-Ga-Zn-O crystal layers is evaluated by classical molecular dynamics simulation.

Figure 30 is a schematic diagram of the crystal of In-Ga-Zn-O. Here, CO ₂ is added to the layer shown by the arrow in Fig. 30. The addition ratio of CO ₂ to all atoms in the In-Ga-Zn-O crystal was 0.07% (5.19 × 10 ¹⁹ /cm ³ ), 0.15% (1.04 × 10 ²⁰ /cm ³ ), 0.22% (1.65 × 10). ²⁰ /cm ³ ), 0.30% (2.08 × 10 ²⁰ /cm ³ ), 0.37% (2.60 × 10 ²⁰ /cm ³ ), 0.44% (3.11 × 10 ²⁰ /cm ³ ), 0.52% (3.63 × 10 ²⁰ / Cm ³ ), 0.59% (4.15 × 10 ²⁰ /cm ³ ), or 0.67% (4.67 × 10 ²⁰ /cm ³ ).

For this simulation, Materials Explorer 5.0 manufactured by Fujitsu Co., Ltd. was used, and the temperature, pressure, time step size, and number of steps were 298 K, 1 atm, 0.2 fs, and 5,000,000, respectively.

As a result, when the addition ratio of CO ₂ is 0.07% to 0.52%, the crystal of In-Ga-Zn-O is maintained, and when the addition ratio of CO ₂ is 0.59% to 0.67%, the crystal of In-Ga-Zn-O is crystallized. Can't be maintained.

This result shows that the addition ratio of CO ₂ to all atoms in the In-Ga-Zn-O crystal needs to be 0.52% or less or less than 0.59%, so that the In-Ga-Zn-O crystal can be obtained.

Second, the heat treatment is carried out. The heat treatment is in a decompression atmosphere at an inert rate of 250 ° C to 650 ° C (including), preferably 300 ° C to 600 ° C (including) It is implemented in a sexual atmosphere or an oxidizing atmosphere. By this heat treatment, the impurity concentration in the oxide semiconductor film can be lowered. Further, the oxide semiconductor film is likely to have high crystallinity. The oxidizing atmosphere means an atmosphere containing an oxidizing gas such as oxygen, ozone, or nitrous oxide of 10 ppm or more.

The heat treatment is preferably carried out in such a manner that after the heat treatment is carried out in a reduced pressure atmosphere or an inert atmosphere, the atmosphere is switched to an oxidizing atmosphere while the temperature is maintained and the heat treatment is further carried out. When the heat treatment is carried out in a reduced pressure atmosphere or an inert atmosphere, the impurity concentration in the oxide semiconductor film can be lowered; however, oxygen vacancies are simultaneously generated. Oxygen vacancies generated can be reduced by heat treatment in an oxidizing atmosphere.

When the heat treatment is performed on the oxide semiconductor film after the film formation (except for substrate heating in film formation), the impurity concentration in the film can be remarkably lowered.

With the above deposition apparatus, an oxide semiconductor film containing a small amount of impurities can be formed. Such an oxide semiconductor film containing a small amount of impurities has low carrier density and high crystallinity; therefore, it is excellent in semiconductor characteristics. Therefore, a transistor including such an oxide semiconductor film can be highly reliable.

Specifically, the hydrogen concentration in the oxide semiconductor film (which is measured by SIMS) is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably lower than or equal to 5 × 10 ¹⁸ atoms / cm ³ , more preferably low. It is equal to or greater than 1 × 10 ¹⁸ atoms / cm ³ , more preferably lower than or equal to 5 × 10 ¹⁷ atoms / cm ³ .

The nitrogen concentration in the oxide semiconductor film (which is measured by SIMS) is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably lower than or equal to 5 × 10 ¹⁸ atoms / cm ³ , more preferably lower than or equal to 1 ×10 ¹⁸ atoms/cm ³ , more preferably lower than or equal to 5 × 10 ¹⁷ atoms/cm ³ .

The carbon concentration in the oxide semiconductor film (which is measured by SIMS) is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably lower than or equal to 5 × 10 ¹⁸ atoms / cm ³ , more preferably lower than or equal to 1 ×10 ¹⁸ atoms/cm ³ , more preferably lower than or equal to 5 × 10 ¹⁷ atoms/cm ³ .

The amount of each of the following gases released from the oxide semiconductor film is 1 × 10 ¹⁹ /cm ³ or lower, preferably 1 × 10 ¹⁸ /cm ³ or lower (which is thermally desorbed (TDS)). Analytically measured): a gas having a mass-to-charge ratio (m/z) 2 (for example, water molecules), a gas having a mass-to-charge ratio (m/z) 18, and a gas having a mass-to-charge ratio (m/z) of 28. And a gas having a mass-to-charge ratio (m/z) of 44.

A method of measuring the amount of released oxygen atoms (which will be described later) is referred to for a measurement method of the amount of release by using TDS analysis.

Subsequently, the transistor including the oxide semiconductor film formed by using the above deposition apparatus will be referred to FIGS. 3A and 3B, 4A and 4B, 5A and 5B, 6A and 6B, and 7A to 7C. And 8A and 8B are described.

The crystals shown in Figs. 3A and 3B, 4A and 4B, 5A and 5B, and 6A and 6B are excellent in productivity because the number of photolithography processes is small. The transistors shown in FIGS. 3A and 3B, 4A and 4B, 5A and 5B, and 6A and 6B are often used for display devices in which the transistors have relatively large sizes, and the like. By.

First, the structure of the transistor in Figs. 3A and 3B will be described. Figure 3A is a top view of the transistor. Fig. 3B is a cross-sectional view taken along the broken line A-B in Fig. 3A.

The transistor in FIG. 3B includes a base insulating film 102 over the substrate 100; an oxide semiconductor film 106 disposed over the base insulating film 102; and is disposed over and at least partially in contact with the oxide semiconductor film 106 a pair of electrodes 116; a gate insulating film 112 provided to cover the oxide semiconductor film 106 and the pair of electrodes 116; and a gate electrode 104 disposed to overlap the oxide semiconductor film 106 with the gate insulating film 112 interposed therebetween .

Here, the oxide semiconductor film having a low impurity concentration described in this embodiment can be used as the oxide semiconductor film 106.

The thickness of the oxide semiconductor film 106 is greater than or equal to 1 nm and less than or equal to 50 nm, preferably greater than or equal to 3 nm and less than or equal to 20 nm. Particularly in the case where the transistor has a channel length of 30 nm or less and the oxide semiconductor film 106 has a thickness of about 5 nm, the short channel effect can be suppressed and stable electrical characteristics can be obtained.

The oxide semiconductor film 106 preferably contains at least In and Zn. Further, it is preferable that the oxide semiconductor film 106 contains Ga, Sn, Hf, or Al in addition to In and Zn, so that the change in electrical characteristics of the transistor can be reduced.

Alternatively, the oxide semiconductor film 106 may contain one or more lanthanides other than In and Zn, such as La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu make the change in electrical characteristics of the transistor can be reduced.

For the oxide semiconductor film 106, any of the following may be used: for example, an In-Zn-O based material, a Sn-Zn-O based material, an Al-Zn-O based material, a Zn-Mg-O based material, Sn-Mg-O based material, In-Mg-O based material, and two-component metal oxide of In-Ga-O based material; such as In-Ga-Zn-O based material, In-Al-Zn-O based Material, In-Sn-Zn-O based material, Sn-Ga-Zn-O based material, Al-Ga-Zn-O based material, Sn-Al-Zn-O based material, In-Hf-Zn-O based Material, In-La-Zn-O based material, In-Ce-Zn-O based material, In-Pr-Zn-O based material, In-Nd-Zn-O based material, In-Sm-Zn-O based Material, In-Eu-Zn-O based material, In-Gd-Zn-O based material, In-Tb-Zn-O based material, In-Dy-Zn-O based material, In-Ho-Zn-O based a material, an In-Er-Zn-O based material, an In-Tm-Zn-O based material, an In-Yb-Zn-O based material, and a three-component metal oxide of an In-Lu-Zn-O based material; In-Sn-Ga-Zn-O based material, In-Hf-Ga-Zn-O based material, In-Al-Ga-Zn-O based material, In-Sn-Al-Zn-O based material, In- A Sn-Hf-Zn-O based material and a four-component metal oxide of an In-Hf-Al-Zn-O based material.

For example, "In-Ga-Zn-O-based material" means an oxide containing In, Ga, and Zn as its main components, and the ratio of In:Ga:Zn is not particularly limited.

For example, high field effect mobility can be relatively easily achieved in the case of a transistor formed using an In-Sn-Zn-O based material. Specifically, the transistor may have 31 cm ² /Vs or higher, 40 cm ² /Vs or higher, 60 cm ² /Vs or higher, 80 cm ² /Vs or higher, or 100 cm ² / Field effect mobility of Vs or higher. In the case of a transistor formed by using a material other than the In—Sn—Zn—O-based material (for example, an In—Ga—Zn—O-based material), the field-effect mobility can be reduced by reducing the defect density. increase.

In the case where an In-Zn-O based material is used for the oxide semiconductor film 106, the atomic ratio of In to Zn is from 0.5:1 to 50:1, preferably from 1:1 to 20:1, more preferably 1.5:1. In the range of 15:1. When the atomic ratio of In to Zn is in the above range, the field effect mobility of the transistor can be increased. Here, when the atomic ratio of In:Zn:O of the compound is X:Y:Z, Z>1.5X+Y is preferably satisfied.

A material represented by InMO ₃ (ZnO) _m (m>0) can be used for the oxide semiconductor film 106. Here, M represents one or more metal elements selected from the group consisting of Zn, Ga, Al, Mn, Sn, Hf, and Co. For example, M may be Ga, Ga and Al, Ga and Mn, Ga and Co, or the like.

For the oxide semiconductor film 106, a material having an energy gap of 2.5 eV or higher, preferably 2.8 eV or higher, more preferably 3.0 eV or higher, is selected to lower the off-state current of the transistor.

It is noted that it is preferable that the alkali metal, the alkaline earth metal, and the like are reduced from the oxide semiconductor film 106 so that the impurity concentration is extremely low. When the oxide semiconductor film 106 contains any of the above impurities, the recombination of the energy gap occurs due to the energy level formed by the impurities, so that the open state current of the transistor is increased.

As for the alkali metal concentration in the oxide semiconductor film 106 (which is measured by SIMS), the concentration of sodium is 5 × 10 ¹⁶ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ or less. More preferably 1 × 10 ¹⁵ atoms/cm ³ or less; the concentration of lithium is 5 × 10 ¹⁵ atoms / cm ³ or less, preferably 1 × 10 ¹⁵ atoms / cm ³ or less; and the concentration of potassium is 5 ×10 ¹⁵ atoms/cm ³ or less, preferably 1 × 10 ¹⁵ atoms/cm ³ or less.

The use of the oxide semiconductor film 106 as described above makes it possible to lower the off-state current of the transistor. Specifically, for example, a circuit state current of a transistor having a channel length of 3 μm and a channel width of 1 μm may be lower than or equal to 1×10 ^-18 A, lower than or equal to 1×10 ⁻²¹ A, or lower than or equal to 1 × 10 ^-24 A.

The oxide semiconductor film 106 is a non-single-crystal oxide semiconductor film. It is particularly preferable that the oxide semiconductor film 106 has crystallinity. For example, a polycrystalline film or a CAAC-OS film is used.

Examples of the crystal structure of the CAAC-OS film will be described in detail with reference to Figs. 14A to 14E, Figs. 15A to 15C, Figs. 16A to 16C, and Figs. 17A and 17B. In FIGS. 14A to 14E, 15A to 15C, 16A to 16C, and 17A and 17B, a plane whose vertical direction corresponds to the c-axis direction and which is perpendicular to the c-axis direction corresponds to the ab plane unless otherwise Something. When the words "upper half" and "lower half" are used simply, they mean the upper half above the ab plane and the lower half below the ab plane (relative to the upper half of the ab plane) And the lower half). Further, in the maps 14A to 14E, O surrounded by a circle represents a tetracoordinate O and O surrounded by a double circle represents a tricoordinate O.

Figure 14A shows a hexa-coordinate In atom and adjacent thereto The structure of six tetracoordinate oxygen atoms of the In atom (hereinafter referred to as tetracoordinate O). Here, a structure including a metal atom and an oxygen atom adjacent to the metal atom is referred to as a small group. The structure in Fig. 14A is actually an octahedral structure, but is shown as a planar structure for simplicity. It is noted that three tetracoordinate O atoms are present in each of the upper and lower halves of Figure 14A. In the small group shown in Fig. 14A, the electric charge is zero.

Figure 14B shows a three-coordinate oxygen atom (hereinafter referred to as tricoordinate O) comprising a pentacoordinate Ga atom, adjacent to the Ga atom, and two tetracoordinate O atoms adjacent to the Ga atom. structure. All three-coordinate O atoms are present in the a-b plane. A tetracoordinate O atom is present in each of the upper and lower halves of Figure 14B. The In atom may also have the structure shown in Fig. 14B because the In atom may have five ligands. In the small group shown in Fig. 14B, the electric charge is zero.

Figure I4C shows a structure comprising a tetracoordinated Zn atom and four tetracoordinate O atoms adjacent to the Zn atom. In Figure 14C, one tetracoordinate O atom is present in the upper half and three tetracoordinate O atoms are present in the lower half. Alternatively, three tetracoordinate O atoms may be present in the upper half and a tetracoordinate O atom may be present in the lower half in Figure 14C. In the small group shown in Fig. 14C, the electric charge is zero.

Figure 14D shows a structure comprising a hexacoordinate Sn atom and six tetracoordinate O atoms adjacent to the Sn atom. In Figure 14D, three tetracoordinate O atoms are present in each of the upper and lower halves. In the small group shown in Fig. 14D, the electric charge is +1.

Figure 14E shows a small group comprising two Zn atoms. In the first In Figure 14E, a tetracoordinate O atom is present in each of the upper and lower halves. In the small group shown in Fig. 14E, the electric charge is -1.

Here, a plurality of small groups form a middle group, and a plurality of middle groups form a large group (also referred to as a unit cell).

Now, the rules for bonding between small groups will be described. The three O atoms in the upper half of the six-coordinate In atom in FIG. 14A each have three adjacent In atoms in the downward direction, and the three O atoms in the lower half have each in the upward direction. Three adjacent In atoms. In Fig. 14B, one O atom in the upper half of the five-coordinate Ga atom has one adjacent Ga atom in the downward direction, and one O atom in the lower half has one adjacent Ga atom in the upward direction. In Fig. 14C, one O atom in the upper half of the tetracoordinate Zn atom has one adjacent Zn atom in the downward direction, and three O atoms in the lower half have three adjacent sides in the upward direction. Zn atom. In this way, the number of tetracoordinate O atoms above the metal atom is equal to the number of metal atoms adjacent to each of the tetracoordinate O atoms and below each of the tetracoordinate O atoms. Similarly, the number of tetracoordinate O atoms below a metal atom is equal to the number of metal atoms above each of the tetracoordinate O atoms and above each of the tetracoordinate O atoms. Since the coordination number of the tetracoordinate O atom is 4, the sum of the number of metal atoms adjacent to the O atom and below the O atom and the number of metal atoms adjacent to the O atom and above the O atom is 4. Therefore, when the sum of the number of tetracoordinate O atoms above the metal atom and the number of tetracoordinate O atoms under the other metal atom is 4, a small group including two kinds of the metal atoms may be bonded. . For example, in a six-coordinate metal (In or Sn) atom via three tetracoordinates in the lower half In the case where the O atom is bonded, it is bonded to a pentacoordinate metal (Ga or In) atom or a tetracoordinate metal (Zn) atom.

A metal atom having a coordination number of 4, 5, or 6 is bonded to another metal atom via a tetracoordinate O atom in the c-axis direction. In addition to the above, the middle group can be formed by different ways of combining a plurality of small groups such that the total charge of the hierarchical structure is zero.

Fig. 15A shows a model of a group included in the layered structure of the In-Sn-Zn-O-based material. Figure 15B shows a large group comprising three middle groups. Note that Fig. 15C shows the atomic configuration in the case where the layered structure of Fig. 15B is observed from the c-axis direction.

In Fig. 15A, the tricoordinate O atom is omitted for simplicity, and the tetracoordinate O atom is shown by a circle; the number in the circle shows the number of tetracoordinate O atoms. For example, three tetracoordinate O atoms present in each of the upper and lower halves of the Sn atom are represented by a circle of 3. Similarly, in Fig. 15A, a tetracoordinate O atom present in each of the upper and lower halves of the In atom is represented by a circle of 1. Figure 15A also shows a Zn atom adjacent to a tetracoordinate O atom in the lower half and adjacent to three tetracoordinate O atoms in the upper half, and a tetracoordinate O atom in the upper half and below A Zn atom adjacent to three tetracoordinate O atoms in the half.

In the middle group included in the layered structure of the In-Sn-Zn-O-based material of Fig. 15A, in the order from the top, three of the upper half and the lower half are adjacent to each other. The Sn atom of the O atom is bonded to the In atom adjacent to a tetracoordinate O atom in each of the upper and lower halves, the In The atom is bonded to a Zn atom adjacent to three tetracoordinate O atoms in the upper half, the Zn atom being bonded to the upper half via a tetracoordinate O atom in the lower half of the Zn atom An In atom adjacent to three tetracoordinate O atoms in each of the lower and lower halves, the In atom being bonded to a small group comprising two Zn atoms and adjacent to a tetracoordinate O atom in the upper half, And the small group is bonded to a Sn atom adjacent to three tetracoordinate O atoms in each of the upper and lower halves via a tetracoordinate O atom in the lower half of the small group . A plurality of such groups are bonded such that a large group is formed.

Here, the charge of one bond of the tricoordinate O atom and the charge of one bond of the tetracoordinate O atom can be assumed to be -0.667 and -0.5, respectively. For example, the charge of the (hexacoordinate or pentacoordinate) In atom, the charge of the (tetracoordinate) Zn atom, and the charge of the (five-coordinate or hexa-coordinate) Sn atom are +3, +2, and +, respectively. 4. Therefore, the charge of a small group including Sn atoms is +1. Therefore, a charge of -1 (which cancels +1) is required to form a layered structure including Sn atoms. As a structure having a charge of -1, a small group including two Zn atoms as shown in Fig. 14E can be exemplified. For example, by a small group comprising two Zn atoms, the charge of a small group comprising Sn atoms can be cancelled such that the total charge of the layered structure can be zero.

Specifically, when a large group shown in FIG. 15B is repeated, crystallization of an In—Sn—Zn—O-based material (In ₂ SnZn ₃ O ₈ ) can be obtained. It is noted that the layered structure of the obtained In-Sn-Zn-O-based material can be expressed as a composition formula of In ₂ SnZnO ₆ (ZnO) _m (m is a natural number).

The above rules are also applied to the following materials: such as In-Sn-Ga-Zn-O a four-component metal oxide of a material; such as an In-Ga-Zn-O based material, an In-Al-Zn-O based material, a Sn-Ga-Zn-O based material, an Al-Ga-Zn-O based material, Sn -Al-Zn-O based material, In-Hf-Zn-O based material, In-La-Zn-O based material, In-Ce-Zn-O based material, In-Pr-Zn-O based material, In -Nd-Zn-O based material, In-Sm-Zn-O based material, In-Eu-Zn-O based material, In-Gd-Zn-O based material, In-Tb-Zn-O based material, In -Dy-Zn-O based material, In-Ho-Zn-O based material, In-Er-Zn-O based material, In-Tm-Zn-O based material, In-Yb-Zn-O based material, and Three-component metal oxide of In-Lu-Zn-O based material; such as In-Zn-O based material, Sn-Zn-O based material, Al-Zn-O based material, Zn-Mg-O based material, Sn a Mg-O based material, an In-Mg-O based material, and a two component metal oxide of an In-Ga-O based material; and the like.

For example, Figure 16A shows a model of a middle group included in the layered structure of an In-Ga-Zn-O based material.

In the middle group included in the layered structure of the In-Ga-Zn-O-based material of FIG. 16A, in the order from the top, three of the upper half and the lower half are adjacent to each other. The In atom of the O atom is bonded to a Zn atom adjacent to a tetracoordinate O atom in the upper half, the Zn atom being bonded via three tetracoordinate O atoms in the lower half of the Zn atom And a Ga atom adjacent to a tetracoordinate O atom in each of the upper half and the lower half, and the Ga atom is bonded to via a tetracoordinate O atom in a lower half of the Ga atom to The In atoms of three tetracoordinate O atoms are adjacent to each of the upper and lower halves. A plurality of such groups are bonded such that a large group is formed.

Figure 16B shows a large group comprising three middle groups. Note that Fig. 16C shows the atomic configuration in the case where the layered structure of Fig. 16B is observed from the c-axis direction.

Here, since the charge of the (six-coordinate or penta-coordinate) In atom, the charge of the (tetracoordinate) Zn atom, and the charge of the (five-coordinate) Ga atom are +3, +2, and +3, respectively. A small group including any of In atoms, Zn atoms, and Ga atoms has a charge of zero. As a result, the total charge of the middle group having the combination of such small groups is always zero.

In order to form a layered structure of the In-Ga-Zn-O-based material, a large group can be used by not only the middle group shown in FIG. 16A but also by using an In atom, a Ga atom, and a Zn atom. A middle group different from that of Fig. 16A is configured to be formed.

Specifically, when a large group shown in FIG. 16B is repeated, crystallization of an In-Ga-Zn-O-based material can be obtained. It is noted that the layered structure of the obtained In-Ga-Zn-O-based material can be expressed as a composition formula of InGaO ₃ (ZnO) _n (n is a natural number).

In the case where n is 1 (InGaZnO ₄ ), for example, a crystal structure shown in Fig. 17A can be obtained. Note that in the crystal structure shown in Fig. 17A, since Ga atoms and In atoms each have five ligands (as described in Fig. 14B), a structure in which Ga is replaced with In can be obtained.

In the case where n is 2 (InGaZn ₂ O ₅ ), for example, a crystal structure shown in Fig. 17B can be obtained. Note that in the crystal structure shown in Fig. 17B, since Ga atoms and In atoms each have five ligands (as described in Fig. 14B), a structure in which Ga is replaced with In can be obtained.

Here, the change in the crystal state in the case where one carbon atom (C) is introduced into the large group of InGaZnO ₄ of Fig. 16B is evaluated by using the first principle calculation.

It is noted that CASTEP (First Principle Computing Software produced by Accelrys Software Ltd.) is used for this first principle calculation. A super soft pseudopotential is used with a cutoff energy of 300 eV.

Figure 31A shows the position where C is introduced in a large group of InGaZnO ₄ . Figure 31B shows the crystalline state of a large group of InGaZnO ₄ after introduction of C and optimization of the structure.

Figure 31B shows that the introduction of C causes a bond between C and O, resulting in an increase in the interatomic distance between Ga and O that have been bonded to each other.

This result shows that C in the In-Ga-Zn-O-based material suppresses the maintenance of the crystal structure.

Second, the change in crystalline state in the case where a carbon dioxide molecule (CO ₂ ) is introduced into a large group of InGaZnO ₄ is evaluated by using a first principle calculation.

It is noted that CASTEP (First Principle Computing Software produced by Accelrys Software Ltd.) is used for this first principle calculation. Ultra-soft imaginary bits can be used with a cutoff energy of 300 eV.

FIG. 39A show the first position of the CO ₂ is introduced in a large group InGaZnO _4. Figures 39B to 39D show the crystallization state of a large group of InGaZnO ₄ during the optimization of the structure in the case where CO ₂ is introduced into the position shown in Fig. 39A. Here, the structure in Fig. 39D, the structure in Fig. 39C, and the structure in Fig. 39B are closer to the optimum structure in this order.

In Figure 39B, CO ₂ is replaced by a portion of a large group of InGaZnO ₄ . Next, as in the 39C chart, the interlayer distance of InGaZnO ₄ increases in the vicinity of CO ₂ . Thereafter, as in the 39D chart, CO ₂ is separated and the interlayer distance of InGaZnO ₄ is further increased.

This result shows that CO ₂ in the In-Ga-Zn-O based material suppresses the maintenance of the crystal structure.

Hereinafter, the crystal state of the oxide semiconductor film which can be applied to the transistor of the semiconductor device according to this embodiment will be described.

In order to evaluate the crystal state, X-ray diffraction (XRD) analysis of the oxide semiconductor film was performed. The XRD analysis was carried out by using an X-ray diffractometer D8 ADVANCE manufactured by Bruker AXS, and the measurement was carried out by an out-of-plane method.

Sample A and Sample B are prepared and the XRD analysis is performed on the samples. The method used to form sample A and sample B will be described below.

First, a quartz substrate that has been subjected to dehydrogenation treatment is prepared.

Next, an In-Sn-Zn-O film having a thickness of 100 nm was formed on the quartz substrate.

The In-Sn-Zn-O film was formed in an oxygen atmosphere with a sputtering apparatus having a power of 100 W (DC). An In-Sn-Zn-O target having an In:Sn:Zn atomic ratio of 1:1:1 was used as a target. It was noted that the substrate heating temperature in film formation was set at room temperature (without heating) or at 200 °C. The samples formed in this way are used as sample A.

Second, the sample formed by the method similar to the sampling A was subjected to heat treatment at 650 °C. As the heat treatment, the heat treatment in a nitrogen atmosphere was first carried out for one hour and the heat treatment in an oxygen atmosphere was further carried out for one hour without lowering the temperature. The sample formed in this way is used as the sample B.

Figure 28 shows the XRD spectra of sample A and sample B. No peaks from crystallization were observed in sample A, while peaks from crystallization were observed in sample B when 2θ was about 35 degrees and at 37 degrees to 38 degrees.

These results show that the crystalline oxide semiconductor film can be obtained by performing heat treatment at 650 ° C for the sampling.

The substrate 100 is not particularly limited as long as it has heat resistance at least sufficient to withstand the heat treatment performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, or a sapphire substrate can be used as the substrate 100. Alternatively, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of tantalum, tantalum carbide, or the like, a compound semiconductor substrate made of tantalum or the like, a silicon-on-insulator (SOI) substrate, or the like It can be used as the substrate 100. Any of these substrates further provided with semiconductor elements is preferably used as the substrate 100.

Still alternatively, a flexible substrate can be used as the substrate 100. As a method of disposing a transistor on a flexible substrate, there is a method in which a transistor is formed on a non-flexible substrate, and then the transistor is separated and transferred to a substrate 100 (which is flexible) Substrate). In this case, a separation layer is preferably disposed between the non-flexible substrate and the transistor.

By using antimony oxide, antimony oxynitride, tantalum nitride oxide, nitridation One or more of tantalum, aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, hafnium oxide, tantalum oxide, hafnium oxide, tantalum oxide, and magnesium oxide may form the base insulating film 102 to have a single layer structure or stack Layer structure.

It is preferable that the base insulating film 102 is sufficiently flat. Specifically, the film used as a substrate is set to have an average surface roughness (Ra) of 1 nm or less, preferably 0.3 nm or less, more preferably 0.1 nm or less. When Ra is less than or equal to the above value, the crystallization region is easily formed in the oxide semiconductor film 106. It is noted that Ra is obtained by three-dimensional expansion of the center line average roughness defined by JIS B 0601 for supply to the plane. Further, Ra may be expressed as an average value of absolute values of deviations from a reference surface to a specific surface and is defined by Equation 1.

Note that in Equation 1, S ₀ represents the measurement surface (four represented by coordinates ( x ₁ , y ₁ ), ( x ₁ , y ₂ ), ( x ₂ , y ₁ ), and ( x ₂ , y ₂ ) The area of the quadrilateral area defined by the points, and Z ₀ represents the average height of the measurement surface. Ra can be evaluated by using an atomic force microscope (AFM).

In this specification, arsenic oxynitride means a substance in which the oxygen content is higher than the nitrogen content. For example, bismuth oxynitride contains concentrations ranging from 50 at.% (inclusive) to 70 at.% (inclusive), from 0.5 at.% (inclusive) to 15 at.% (inclusive), and from 25 at.% (inclusive). ) to 35 at.% (inclusive), and from 0 at.% (inclusive) to 10 at.% (inclusive) of oxygen, nitrogen, helium, and hydrogen. Niobium nitride oxide means a substance in which the nitrogen content is higher than the oxygen content. For example, tantalum nitride oxide contains The concentration ranges from 5 at.% (inclusive) to 30 at.% (inclusive), from 20 at.% (inclusive) to 55 at.% (inclusive), from 25 at.% (inclusive) to 35 at.%. (including), and from 10 at.% (inclusive) to 25 at.% (inclusive) of oxygen, nitrogen, helium, and hydrogen. It is noted that the above range is obtained in the case where the measurement is carried out by using Rutherford backscattering (RBS) spectroscopy and hydrogen front scatter (HFS). In addition, the sum of the percentages of the constituent components does not exceed 100 at.%.

It is preferable that an insulating film from which oxygen is released by heat treatment is used as the base insulating film 102.

The release of oxygen by heat treatment means that the amount of oxygen released into the oxygen atom is measured by thermal desorption spectroscopy (TDS) analysis to be greater than or equal to 1.0 × 10 ¹⁸ atoms / cm ³ or greater than or equal to 3.0 × 10 ²⁰ atoms / cm ³ .

Here, a measurement method of the amount of oxygen released by using TDS analysis will be described.

The total amount of released gas in the TDS analysis is proportional to the integral value of the ionic strength of the released gas, and the total amount of released gas can be compared by the integrated value of the measured sample and the integral value of the standard sample. To calculate it.

For example, the amount of oxygen molecules (N _O2 ) released from the insulating film can be based on the TDS analysis result of the hydrogen-containing wafer containing a predetermined density (which is the standard sampling) according to Equation 2 and the TDS analysis result of the insulating film. Come and get it. Here, all gases having a mass of 32, which are obtained in the TDS analysis, are assumed to be derived from oxygen molecules. The CH ₃ OH gas, which is provided as a gas having a mass of 32, is not considered under the assumption that it is unlikely to exist. Further, an oxygen molecule including an oxygen atom having 17 or 18 mass atoms which is an isotope of an oxygen atom is not considered because the ratio of such a molecule is extremely small in nature.

The value N _H2 is obtained by converting the amount of hydrogen molecules desorbed from the standard sample to a density. The value S _H2 is the integrated value of the ionic strength in the case where the standard sample is subjected to TDS analysis. Here, the reference value of the standard sample is set to N _H2 /S _H2 . The value S _O2 is an integrated value of the ionic strength in the case where the insulating film is subjected to TDS analysis. The value α is a coefficient that affects the ionic strength in the TDS analysis. Japanese Laid-Open Patent Application No. H6-275697 can be referred to for the details of Equation 2. It is noted that the amount of oxygen released from the above insulating film is EMD-WA1000S/W (thermal desorption spectroscopy apparatus manufactured by ESCO Co., Ltd.) by using a ruthenium wafer (containing 1 × 10 ¹⁶ atoms/cm ³ of hydrogen atoms). ) is measured as the standard sample.

Further, in the TDS analysis, oxygen is partially detected as an oxygen atom. The ratio between the oxygen molecule and the oxygen atom can be calculated from the liberation rate of the oxygen molecules. It is noted that since the above α includes the liberation rate of the oxygen molecules, the amount of oxygen atoms released can also be estimated by evaluating the release amount of the oxygen molecules.

Note that N _O2 is the amount of oxygen molecules released. The amount of oxygen released in the case of being converted into an oxygen atom is twice the amount of oxygen molecules released.

In the above structure, the film from which oxygen is released by heat treatment may be an oxygen excess of cerium oxide (SiO _x (x>2)). In oxygen excess cerium oxide (SiO _x (x>2)), the number of oxygen atoms per unit volume exceeds twice the number of argon atoms per unit volume. The number of deuterium atoms per unit volume and the number of oxygen atoms were measured by a Laceford backscattering spectrum.

The supply of oxygen from the base insulating film 102 to the oxide semiconductor film 106 can reduce the interface state density between the oxide semiconductor film 106 and the base insulating film 102. As a result, carriers trapped at the interface between the oxide semiconductor film 106 and the base insulating film 102 due to the operation or the like of the transistor can be suppressed, and thus a transistor having high reliability can be obtained.

Further, in some cases, charges are generated due to oxygen vacancies in the oxide semiconductor film 106. In general, one of the oxygen vacancies in the oxide semiconductor film 106 serves as a donor and causes the release of electrons, which are carriers. As a result, the threshold voltage of the transistor is shifted in the negative direction. When oxygen is sufficiently supplied from the base insulating film 102 to the oxide semiconductor film 106 such that the oxide semiconductor film 106 preferably contains excess oxygen, the oxygen vacancies in the oxide semiconductor film 106 (which cause a negative shift of the threshold voltage) can be cut back.

The excess oxygen is mainly oxygen existing between the crystal lattices of the oxide semiconductor film 106. When the concentration of oxygen is set in the range of 1 × 10 ¹⁶ atoms / cm ³ to 2 × 10 ²⁰ atoms / cm ³ , crystal distortion or the like is not generated and thus the crystal region is not destroyed, which It is better.

Oxidation of any of these elements by using one or more of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, Ta, and W, nitride of any of these elements The object, and an alloy of any of these elements, may be formed to have the single electrode structure or a stacked layer structure. Alternatively, an oxide or oxynitride containing at least In and Zn can be used. For example, an In-Ga-Zn-O-N based material can be used.

The gate insulating film 112 can be formed by using a substrate insulating film 102 similar to Methods and materials are used to form.

The gate electrode 104 can be formed by using a method and material similar to the pair of electrodes 116.

Next, the structure of the transistor in Figs. 4A and 4B will be described. Figure 4A is a top view of the transistor. Fig. 4B is a cross-sectional view taken along the broken line A-B in Fig. 4A.

The transistor in FIG. 4B includes a base insulating film 102 over the substrate 100; a pair of electrodes 216 disposed over the base insulating film 102; and is disposed over the pair of electrodes 216 to be insulated from the pair of electrodes 216 and the substrate The oxide semiconductor film 206 at least partially in contact with the film 102; the gate insulating film 212 disposed to cover the pair of electrodes 216 and the oxide semiconductor film 206; and the gate insulating film 212 is disposed to overlap the oxide semiconductor film 206 A gate electrode 204 interposed therebetween.

Note that the pair of electrodes 216, the oxide semiconductor film 206, the gate insulating film 212, and the gate electrode 204 can be similarly used by using a pair of electrodes 116, an oxide semiconductor film 106, a gate insulating film 112, and a gate, respectively. The method and material of the electrode 112 are formed.

The structure of the transistor in Figs. 5A and 5B will be described. Figure 5A is a top view of the transistor. Fig. 5B is a cross-sectional view taken along the broken line A-B in Fig. 5A.

The transistor in FIG. 5B includes a gate electrode 304 over the substrate 100; a gate insulating film 312 disposed to cover the gate electrode 304; is disposed to overlap the gate electrode 304 and the gate insulating film 312 is interposed An oxide semiconductor film 306 therebetween; and an oxide semiconductor film 306 disposed thereon and A pair of electrodes 316 that are at least partially in contact. It is noted that the protective insulating film 318 is preferably provided to cover the oxide semiconductor film 306 and the pair of electrodes 316.

Note that the pair of electrodes 316, the oxide semiconductor film 306, the gate insulating film 312, and the gate electrode 304 can be used by using a pair of electrodes 116, an oxide semiconductor film 106, a gate insulating film 112, and a gate, respectively. The method and material of the electrode 112 are formed.

The protective insulating film 318 can be provided by using a method and material similar to the base insulating film 102.

The structure of the transistor in Figs. 6A and 6B will be described. Figure 6A is a top view of the transistor. Fig. 6B is a cross-sectional view taken along the broken line A-B in Fig. 6A.

The transistor in FIG. 6B includes a gate electrode 304 over the substrate 100; a gate insulating film 312 disposed to cover the gate electrode 304; a pair of electrodes 416 disposed over the gate insulating film 312; An oxide semiconductor film 406 is provided on the pair of electrodes 416 so as to at least partially contact the pair of electrodes 416 and the gate insulating film 312. It is noted that the protective insulating film 418 is preferably provided to cover the pair of electrodes 416 and the oxide semiconductor film 406.

Note that the pair of electrodes 416, the oxide semiconductor film 406, and the protective insulating film 418 can be formed by using methods and materials similar to the pair of electrodes 116, the oxide semiconductor film 106, and the protective insulating film 318, respectively.

Processes of the transistors shown in Figs. 7A to 7C and Figs. 8A and 8B are the crystals shown in Figs. 3A and 3B, Figs. 4A and 4B, Figs. 5A and 5B, and Figs. 6A and 6B. More complicated; however, in the first The parasitic capacitances in the transistors 7A to 7C and 8A and 8B are small and the short channel effect is unlikely. Therefore, the structures of the transistors in Figs. 7A to 7C and Figs. 8A and 8B are suitable for use in minute transistors whose electrical characteristics are required to be excellent.

The structure of the transistor in Figs. 7A and 7B will be described. Figure 7A is a top view of the transistor. Fig. 7B is a cross-sectional view taken along the broken line A-B in Fig. 7A.

The transistor in FIG. 7B includes a base insulating film 502 over the substrate 100; a protective film 520 disposed on the periphery of the base insulating film 502; and is disposed over the base insulating film 502 and the protective film 520 and includes a high resistance region. The oxide semiconductor film 506 of the 506a and the low resistance region 506b; the gate insulating film 512 provided over the oxide semiconductor film 506; the gate which is disposed to overlap the oxide semiconductor film 506 and the gate insulating film 512 interposed therebetween a pole electrode 504; a sidewall insulating film 524 disposed in contact with a side surface of the gate electrode 504; and a pair of electrodes 516 disposed on the oxide semiconductor film 506 and in contact with at least a portion thereof. It is noted that the protective insulating film 518 is preferably provided to cover the gate electrode 504, the sidewall insulating film 524, and a pair of electrodes 516. Further, the wiring 522 is preferably provided to be in contact with the pair of electrodes 516 via the opening formed in the protective insulating film 518.

Note that the pair of electrodes 516, the gate insulating film 512, the protective insulating film 518, and the gate electrode 504 can be similarly used by using a pair of electrodes 116, a gate insulating film 112, a protective insulating film 318, and a gate electrode, respectively. The method and materials of 104 are formed.

The oxide semiconductor film 506 can be disposed in such a manner that it has a drop The impurity which functions as a resistance value of the oxide semiconductor film is added via the gate insulating film 512 by using the gate electrode 504 as a mask, so that the high resistance region 506a and the low resistance region 506b are formed. As an impurity, phosphorus, nitrogen, boron, or the like can be used. After the addition of impurities, a heat treatment at 250 ° C to 650 ° C (including) is preferably carried out. It is noted that the ion implantation method is preferably employed to add impurities because a case where an impurity is added as compared with the ion doping method in this case less hydrogen enters the oxide semiconductor film. It is noted that the use of ion doping is not excluded.

The oxide semiconductor film 506 may alternatively be provided in such a manner that an impurity having a function of lowering the resistance value of the oxide semiconductor film is shielded by the gate insulating film 512 by using the gate electrode 504 and the sidewall insulating film 524. A cover is added so that the high resistance region 506a and the low resistance region 506b are formed. In this case, the region overlapping the sidewall insulating film 524 is not the low resistance region 506b but the high resistance region 506a (see FIG. 7C).

It is noted that by adding impurities through the gate insulating film 512, damage generated when impurities are added to the oxide semiconductor film 506 can be reduced. However, impurities may be implanted without passing through the gate insulating film 512.

The base insulating film 502 can be formed in such a manner that an insulating film formed by using a method and a material similar to the base insulating film 102 is processed to have a groove portion.

The protective film 520 can be formed in such a manner that the insulating film is formed to fill the groove portion formed in the base insulating film 502 and then subjected to a chemical mechanical polishing (CMP) process.

By using tantalum nitride oxide, tantalum nitride, aluminum oxide, aluminum nitride, The protective film 520 may be formed to have a single layer structure or a stacked layer structure by one or more of cerium oxide, zirconium oxide, cerium oxide, cerium oxide, cerium oxide, cerium oxide, and magnesium oxide.

It is preferred that the protective film 520 does not allow oxygen permeation even when the heat treatment at 250 ° C (inclusive) to 450 ° C (inclusive), preferably 150 ° C (inclusive) to 800 ° C (inclusive) is carried out, for example, for one hour.

When the protective film 520 having such a property is provided on the periphery of the base insulating film 502, the oxygen released from the base insulating film 502 by heat treatment can be prevented from diffusing toward the outside of the transistor. Since oxygen is held in the base insulating film 502 in this manner, the field effect mobility of the transistor can be prevented from being lowered, the variation of the threshold voltage can be reduced, and the reliability can be improved.

It is noted that the structure without the protective film 520 can be employed.

The sidewall insulating film 524 is formed in such a manner that an insulating film is provided to cover the gate electrode 504 and then etched. A highly anisotropic etch is used for this etch. The sidewall insulating film 524 can be formed by performing the highly anisotropic etching on the insulating film in a self-aligned manner. For example, a dry etching method is preferably employed. As the etching gas for the dry etching method, for example, a fluorine-containing gas such as trifluoromethane, octafluorocyclobutane, or tetrafluoromethane can be exemplified. A rare gas or hydrogen can be added to the etching gas. As the dry etching method, a reactive ion etching (RIE) method in which a high frequency voltage is applied to a substrate is preferably used.

The wiring 522 can be provided by using a method and material similar to the gate electrode 104.

The structure of the transistor in Figs. 8A and 8B will be described. Figure 8A Is a top view of the transistor. The cross-sectional view along the broken line A-B in Fig. 8A is the 8B.

The transistor shown in FIG. 8B includes a base insulating film 602 over the substrate 100; a pair of electrodes 616 disposed in the trench portion of the base insulating film 602; and includes a high resistance region 606a and a low resistance region 606b and is disposed An oxide semiconductor film 606 over the base insulating film 602 and the pair of electrodes 616; a gate insulating film 612 disposed over the oxide semiconductor film 606; and a gate insulating film disposed to overlap the oxide semiconductor film 606 612 is interposed with a gate electrode 604 therebetween. It is noted that the protective insulating film 618 is preferably provided to cover the gate insulating film 612 and the gate electrode 604. Further, the wiring 622 is preferably provided in contact with the pair of electrodes 616 via the openings formed in the protective insulating film 618, the gate insulating film 612, and the oxide semiconductor film 606.

Note that the gate insulating film 612, the protective insulating film 618, the oxide semiconductor film 606, the wiring 622, and the gate electrode 604 can be similarly used by using the gate insulating film 112, the protective insulating film 318, and the oxide semiconductor film 506, respectively. The wiring 522 and the method and material of the gate electrode 104 are formed.

The base insulating film 602 can be formed in such a manner that an insulating film formed by using a method and a material similar to the base insulating film 102 is processed to have a groove portion.

The pair of electrodes 616 can be formed in such a manner that the conductive film is formed to fill the groove portion formed in the base insulating film 602 and then subjected to CMP treatment.

The field effect mobility of the transistor will be described below with reference to Fig. 18, Figs. 19A to 19C, Figs. 20A to 20C, and Figs. 21A to 21C.

The field effect mobility of the transistor tends to be measured below its ideal field effect mobility for various reasons; this phenomenon occurs not only in the case of using an oxide semiconductor. One reason for reducing the field effect mobility is a defect inside the semiconductor or a defect in the interface between the semiconductor and the insulating film. Here, it is assumed that the field effect mobility in which no defect exists inside the semiconductor is theoretically calculated by using the Levinson model.

Assuming that the ideal field effect mobility of the transistor is μ ₀ and a potential barrier such as a grain boundary exists in the semiconductor, the measured field effect mobility μ is expressed by Equation 3.

Here, E represents the height of the potential barrier, k represents the Boltzmann constant, and T represents the absolute temperature. It is noted that according to the Li Wensen model, the height E of the potential barrier is assumed to be due to the defect and the height of the potential barrier is expressed by Equation 4.

Here, e denotes a basic charge, N denotes an average defect density per unit area in the channel, ε denotes a dielectric constant of the semiconductor, n denotes a carrier density per unit area in the channel, and C _ox denotes a gate per unit area Insulation film capacitance, V _gs represents the gate voltage, and t represents the thickness of the channel. In the case where the thickness of the semiconductor layer is less than or equal to 30 nm, the thickness of the channel can be considered to be the same as the thickness of the semiconductor layer.

The drain current I _ds in the linear region can be expressed by Equation 5.

Here, L represents the channel length and W represents the channel width, and L and W are each 10 μm here. In addition , V _ds represents the drain voltage.

Equation 6 can be obtained when the logarithm of both sides of Equation 5 is taken.

Equation 6 right as a function of V _gs; Thus, the defect density N may be from the graph (which is ln (I _ds / V _gs) as the ordinate and. 1 V _gs as abscissa to plot the actual measured value / obtained) The slope of the line in the line is obtained. That is, the defect density N in the semiconductor can be obtained from the V _gs - I _ds characteristic of the transistor.

The defect density N in the semiconductor depends on the substrate temperature in the semiconductor deposition. In the case where the semiconductor is an oxide semiconductor deposited by using an In-Sn-Zn-O target having a ratio of In:Sn:Zn of 1:1:1 [atomic ratio], in the oxide semiconductor The defect density N is about 1 × 10 ¹² /cm ² .

The ideal field effect mobility μ _{0 of the} transistor was determined to be 120 cm ² /Vs by calculating the defect density N in the above oxide semiconductor by Equations 3 and 4. Therefore, in the ideal transistor in which the inside of the oxide semiconductor and the interface between the oxide semiconductor and the gate insulating film (which is in contact with the oxide semiconductor) are free from defects, the field-effect mobility μ ₀ is found to be 120. Cm ² /Vs. In contrast, in the case of using an oxide semiconductor having many defects, the field effect mobility μ of the transistor is about 30 cm ² /Vs.

It is noted that even when no defects are present inside the semiconductor, scattering at the interface between the channel and the gate insulating film affects the transmission property of the transistor. The field effect mobility μ ₁ at a position x from the interface of the gate insulating film can be expressed by Equation 7.

Here, D represents the intensity of the electric field generated by the gate electrode, B represents a constant, and l represents the depth at which the adverse effect of scattering at the interface is generated. B and l can be obtained from the actual measurement results of the electrical characteristics of the transistor; B is 4.75 × 10 ⁷ cm / s and l is 10 nm according to the measurement results of the electrical characteristics of the transistor formed by using the oxide semiconductor above. . When D is increased (i.e., when V _gs is increased), the second term of Equation 7 is increased and thus the field effect mobility μ ₁ reduction.

The calculation result of the field effect mobility μ ₂ of an ideal transistor in which the interface between the oxide semiconductor and the gate insulating film (contact with the oxide semiconductor) is free of defects is shown in FIG. Shown in it. For this calculation, the Sentaurus Device manufactured by Synopsys Co., Ltd. was used, and the energy gap, electron affinity, relative permittivity, and thickness of the oxide semiconductor were assumed to be 2.8 eV, 4.7 eV, 15, and 15 respectively. Nm. Further, the work functions of the gate, source, and drain are assumed to be 5.5 eV, 4.6 eV, and 4.6 eV, respectively. The thickness of the gate insulating film is assumed to be 100 nm, and its relative dielectric constant is assumed to be 4.1. The channel length and channel width are each assumed to be 10 μm, and V _ds is assumed to be 0.1 V.

Figure 18 shows that the field effect mobility μ ₂ has a peak value of more than 100 cm ² /Vs at V _{gs of} about 1 V and decreases as V _gs becomes higher because the influence of interface scattering increases.

The calculation results in the case where such an ideal transistor is miniaturized are shown in Figs. 19A to 19C, Figs. 20A to 20C, and Figs. 21A to 21. It is assumed that a transistor having the structure shown in Figs. 7A to 7C is used for the calculation.

Here, the resistivity of the low resistance region 506b is assumed to be 2 × 10 ^-3 Ωcm, and the width of the gate electrode 504, the width of the sidewall insulating film 524, and the width of the channel are assumed to be 33 nm, 5 nm, and 40 nm. It is noted that although the channel region is referred to as high resistance region 506a for convenience, the channel region is assumed herein to be an intrinsic semiconductor.

For this calculation, Sentaurus Device manufactured by Synopsys Co., Ltd. was used. 19A to 19C show a second I _ds transistor having a first configuration of FIG. 7B (solid line) and a field effect mobility [mu] (dotted line) dependence of V _gs. I _{ds is obtained} by calculation under the assumption that V _ds is 1 V, and the field effect mobility μ is obtained by calculation under the assumption that V _ds is 0.1 V. Fig. 19A shows the result of the gate insulating film having a thickness of 15 nm, Fig. 19B shows the result of the gate insulating film having a thickness of 10 nm, and Fig. 19C shows the result of the gate insulating film having a thickness of 5 nm.

19A to 19C show that as the gate insulating film is thinned, the drain current I _{ds is} reduced in the open state (here, in the range of V _gs from -3 V to 0 V). On the other hand, the peak value of the field effect mobility μ and the gate current I _ds in the on state (here, in the range of V _gs from 0 V to 3 V) did not significantly change. Figures 19A through 19C show that at a V _gs of about 1 V, I _ds exceeds 10 μA, which is necessary for memory and the like, which are semiconductor devices.

Similarly, this calculation is also performed on the transistor shown in Fig. 7C. The transistor in Fig. 7C is different from the transistor in Fig. 7B in that an oxide semiconductor film 507 including a high resistance region 507a and a low resistance region 507b is provided. Specifically, in the transistor shown in FIG. 7C, a region in which the oxide semiconductor film 507 overlaps the sidewall insulating film 524 is included in the high resistance region 507a. In other words, the transistor has a compensation region whose width is the same as the width of the sidewall insulating film 524. Note that the width of the compensation zone is also referred to as the compensation length (L _off ) (see Figure 7A). Noting the sake of convenience, the same L _off L _off the right side and the left side.

20A to 20C show the I _ds (solid line) of the transistor (where L _off is 5 nm) shown in Fig. 7C and the V _gs dependence of the field effect mobility μ (dashed line). Note that I _ds is calculated assuming V _ds is 1 V, and the field effect mobility μ is calculated assuming V _ds is 0.1 V. Fig. 20A shows the result of the gate insulating film having a thickness of 15 nm, Fig. 20B shows the result of the gate insulating film having a thickness of 10 nm, and Fig. 20C shows the result of the gate insulating film having a thickness of 5 nm.

21A to 21C show the I _ds (solid line) of the transistor (where L _off is 15 nm) shown in Fig. 7C and the V _gs dependence of the field effect mobility μ (dashed line). Note that I _ds is calculated assuming V _ds is 1 V, and the field effect mobility μ is calculated assuming V _ds is 0.1 V. Fig. 21A shows the result of the gate insulating film having a thickness of 15 nm, Fig. 21B showing the result of the gate insulating film having a thickness of 10 nm, and Fig. 21C showing the result of the gate insulating film having a thickness of 5 nm.

The calculation results in Figs. 20A to 20C and Figs. 21A to 21C show that the gate is in an open state (here, in the range of V _gs from -3 V to 0 V) as the gate insulating film is thin. The current I _ds decreases, similar to the 19A to 19C map. In other words, the peak value of the field effect mobility μ and the gate current I _ds in the on state (here, in the range of V _gs from 0 V to 3 V) do not significantly change.

Peak field effect mobility μ of the first 19A to 19C in the figure is about 80 cm ² / Vs, the first 20A to 20C in the figure is about 60 cm ² / Vs, the first 21A to 21C in the figure is about 40 cm ² / Vs. These results show that the peak increases as the mobility μ of compensating length L _off is reduced and likewise applied to the I _ds in the off state. The I _ds in the on state also decreases as the compensation length L _off increases; however, the decrease in I _ds in the on state is more gentle than the decrease in I _ds in the off state. Further, all calculations show that at a V _gs of about 1 V, I _ds exceeds 10 μA, which is necessary for memory and the like.

Secondly, the transistor formed by using an oxide semiconductor Sex will be described.

22A and 22B are plan views showing the structures of the respective formed transistors (Sampling 1 and Sampling 2) and a cross-sectional view taken along the broken line A-B in Fig. 22A.

The transistor in FIG. 22B includes a base insulating film 702 over the substrate 700; an oxide semiconductor film 706 disposed over the base insulating film 702; a pair of electrodes 716 disposed in contact with the oxide semiconductor film 706; A gate insulating film 712 over the oxide semiconductor film 706 and the pair of electrodes 716; and a gate electrode 704 disposed to overlap the oxide semiconductor film 706 and with the gate insulating film 712 interposed therebetween. Further, the interlayer insulating film 718 covering the gate insulating film 712 and the gate electrode 704, the wiring 722 connected to the pair of electrodes 716 via the opening formed in the interlayer insulating film 718, and the interlayer insulating film 718 and the wiring 722 are covered. A protective insulating film 728 is provided.

As the substrate 700, a glass substrate is used. As the base insulating film 702, a ruthenium oxide film is used. As the oxide semiconductor film 706, an In-Sn-Zn-O film was used. As a pair of electrodes 716, a tungsten film is used. As the gate insulating film 712, a hafnium oxide film is used. The gate electrode 704 has a stacked layer structure of a tantalum nitride film and a tungsten film. The interlayer insulating film 718 has a stacked layer structure of a ruthenium oxynitride film and a polyimide film. The wiring 722 has a stacked layer structure in which a titanium film, an aluminum film, and a titanium film are formed in this order. As the protective insulating film 728, a polyimide film is used.

Note that in the transistor having the structure shown in Fig. 22A, the width of the portion where the gate electrode 704 overlaps with one of the pair of electrodes 716 is referred to as L _ov . Similarly, the width of a portion where the pair of electrodes 716 and the oxide semiconductor film 706 do not overlap is referred to as dW .

The method for forming the transistors (Sampling 1 and Sampling 2) each having the structure shown in Fig. 22B will be described below.

First, the plasma treatment is performed on the surface of the substrate 700 in an argon atmosphere. The plasma treatment was carried out with a sputtering apparatus by applying a bias power (RF) of 200 W to the substrate 700 for 3 minutes.

Subsequently, the ruthenium oxide film as the base insulating film 702 was formed to a thickness of 300 nm without breaking the vacuum.

The hafnium oxide film was formed in a oxygen atmosphere with a sputtering apparatus having a power of 1500 W (RF). Quartz targets were used as targets. The substrate heating temperature in the deposition was set at 100 °C.

Surface of the base insulating film 702 is subjected to CMP planarization process, such that R _a is about 0.2 nm.

Next, an In—Sn—Zn—O film as an oxide semiconductor film was formed to have a thickness of 15 nm.

The In-Sn-Zn-O film was formed by a sputtering apparatus having a power (DC) of 100 W in a mixed atmosphere having a volume ratio of argon: oxygen = 2:3. An In-Sn-Zn-O target having an atomic ratio of In:Sn:Zn = 1:1:1 was used as a target. The substrate heating temperature in the deposition was set at 200 °C.

Next, the heat treatment at 650 ° C is carried out only for the sample 2 . As the heat treatment, the heat treatment in a nitrogen atmosphere was first carried out for one hour and then heat treatment in an oxygen atmosphere was carried out for one hour while maintaining the temperature.

The oxide semiconductor film is processed through a photolithography process to make oxygen A compound semiconductor film 706 is formed.

Next, the tungsten film was formed to a thickness of 50 nm.

The tungsten film was formed in a argon atmosphere with a sputtering apparatus having a power of 1000 W (DC). The substrate heating temperature in the deposition was set at 200 °C.

The tungsten film is processed through a photolithography process such that a pair of electrodes 716 are formed.

Next, the hafnium oxide film as the gate insulating film 712 was formed to have a thickness of 100 nm. The relative dielectric constant of the hafnium oxide film was set to 3.8.

A ruthenium oxide film as the gate insulating film 712 is formed in a manner similar to the base insulating film 702.

Next, the tantalum nitride film and the tungsten film are formed in this order to have thicknesses of 15 nm and 135 nm, respectively.

The tantalum nitride film was formed by a sputtering apparatus having a power (DC) of 1000 W in a mixed atmosphere having a volume ratio of argon: oxygen = 5:1. Substrate heating was not performed in the deposition.

The tungsten film was formed in a argon atmosphere with a sputtering apparatus having a power of 400 W (DC). The substrate heating temperature in the deposition was set at 200 °C.

The tantalum nitride film and the tungsten film are processed through a photolithography process such that a gate electrode 704 is formed.

Next, a hafnium oxynitride film as a part of the interlayer insulating film 718 is formed to a thickness of 300 nm.

a ruthenium oxynitride film as a part of the interlayer insulating film 718 to have A 35 W power (RF) PCVD apparatus was formed in a mixed atmosphere having a volume ratio of monodecane: nitrous oxide = 1:200. The substrate heating temperature in the deposition was set at 325 °C.

The hafnium oxynitride film as a part of the interlayer insulating film 718 is processed through a photolithography process.

Next, a photosensitive polyimide which is a part of the interlayer insulating film 718 is deposited to a thickness of 1500 nm.

The photosensitive polyimide which is a part of the interlayer insulating film 718 is exposed by using a photomask used in a photolithography process (for arsenic oxynitride which is a part of the interlayer insulating film 718), and Development, followed by heat treatment, causes the photosensitive polyimide film to be hardened. In this manner, the interlayer insulating film 718 is formed of the yttrium oxynitride film and the photosensitive polyimide film. This heat treatment was carried out at 300 ° C in a nitrogen atmosphere.

Next, the titanium film, the aluminum film, and the titanium film are formed in the order of 50 nm, 100 nm, and 5 nm, respectively.

Two titanium films were formed in a argon atmosphere with a sputtering apparatus having a power of 1000 W (DC). Substrate heating was not performed in the deposition.

The aluminum film was formed in a argon atmosphere with a sputtering apparatus having a power of 1000 W (DC). Substrate heating was not performed in the deposition.

The titanium film, the aluminum film, and the titanium film are processed through a photolithography process such that the wiring 722 is formed.

Next, a photosensitive polyimide film as the protective insulating film 728 was formed to a thickness of 1500 nm.

The photosensitive polyimide is produced by using a photolithography process (for wiring 722) The photomask used in the implementation is exposed and developed such that the opening of the exposed wiring 722 is formed in the protective insulating film 728.

Next, heat treatment is carried out so that the photosensitive polyimide film is hardened. This heat treatment is carried out in a manner similar to the heat treatment performed on the photosensitive polyimide film as the interlayer insulating film 718.

Through the above process, a transistor having the structure shown in Fig. 22B is formed.

Next, the electrical characteristics of the transistor having the structure in Fig. 22B were evaluated.

Here, the V _gs - I _ds characteristic of the transistor having the structure in Fig. 22B is measured; the result of sampling 1 is shown in Fig. 23A, and the result of sampling 2 is shown in Fig. 23B. The transistors used for this measurement each have a channel length L of 3 μm, a channel width W of 10 μm, L _{ov of} 3 μm per side (total of 6 μm), and dW of 3 μm per side (total of 6 μm). V _ds is set to 10 V.

Comparing Sample 1 with Sample 2, it was found that the field effect mobility of the transistor was increased by performing heat treatment after forming the oxide semiconductor film. The inventors believe that the increase in the field effect mobility of the transistor may be caused by a decrease in the impurity concentration of the oxide semiconductor film (by the heat treatment). Therefore, it is understood that the impurity concentration of the oxide semiconductor film is lowered by the heat treatment performed after the oxide semiconductor film is formed, resulting in the field effect mobility of the transistor being close to the ideal field effect mobility.

Therefore, the results indicate that the impurity concentration in the oxide semiconductor film can be lowered by performing heat treatment after forming the oxide semiconductor film. The field effect mobility of the crystal is increased.

Second, the BT test is implemented for Sample 1 and Sample 2. This BT test will be described below.

First, the V _gs - I _ds characteristics of the transistor were measured at a substrate temperature of 25 ° C and a V _{ds of} 10 V. Note that V _ds means the drain voltage (potential difference between the drain and the source). Next, the substrate temperature was set to 150 ° C and V _ds was set to 0.1 V. Thereafter, V _{gs of} 20 V was applied so that the intensity of the electric field applied to the gate insulating film was 2 MV/cm, and the condition was maintained for one hour. Second, V _gs is set to 0 V. Next, the V _gs - I _ds characteristics of the transistor were measured at a substrate temperature of 25 ° C and a V _{ds of} 10 V. This program is called a positive BT test.

In a similar manner, first, V _gs of transistor - I _ds characteristics to be measured at the substrate temperature 25 ℃ and V _ds 10 V is. Next, the substrate temperature was set to 150 ° C and V _ds was set to 0.1 V. Thereafter, V _{gs of} -20 V was applied so that the intensity of the electric field applied to the gate insulating film was -2 MV/cm, and the condition was maintained for one hour. Second, V _gs is set to 0 V. Next, the V _gs - I _ds characteristics of the transistor were measured at a substrate temperature of 25 ° C and a V _{ds of} 10 V. This program is called a negative BT test.

Figures 24A and 24B show the positive BT test result for sample 1 and the negative BT test result for sample 1, respectively. Figures 25A and 25B show the positive BT test results for sample 2 and the negative BT test results for sample 2, respectively. Noting arrow in the graph is used to clearly show V _gs between before and after the BT test such - I _ds characteristics change.

Sampling 1 due to positive BT test and limited power due to negative BT test The offsets of the pressure are 1.80 V and -0.42 V, respectively. Sampling 2 due to the positive BT test and the offset voltage due to the negative BT test are 0.79 V and 0.76 V, respectively.

It was found that in each of Sample 1 and Sample 2, the offset of the threshold voltage between before and after the BT test was small and the samples were highly reliable transistors.

Next, the relationship between the substrate temperature and the electrical characteristics of the sample 2 transistor was evaluated.

Measured for the transistor having a channel length of 3 μm L, 10 μm channel width W, a side L _ov 3 μm (for a total of 6 μm L _ov), and 0 μm of dW. Note that V _ds is set to 10 V. The substrate temperatures were -40 ° C, -25 ° C, 25 ° C, 75 ° C, 125 ° C, and 150 ° C.

Fig. 26A shows the relationship between the substrate temperature and the threshold voltage, and Fig. 26B shows the relationship between the substrate temperature and the field effect mobility.

From Fig. 26A, it is found that the threshold voltage becomes lower as the substrate temperature increases. Note that the threshold voltage is reduced from 0.38 V to -1.08 V in the range from -40 ° C to 150 ° C.

From Fig. 26B, it was found that the field effect mobility became lower as the substrate temperature increased. It is noted that the mobility is reduced from 37.4 cm ² /Vs to 33.4 cm ² /Vs in the range from -40 ° C to 150 ° C.

Therefore, it was found that the change in the electrical characteristics to the sample 2 was small in the above temperature range.

It has also been found that the transistors described above have high field effect mobility and are therefore highly reliable.

Similarly, the off-state current of the per-micron channel width of the transistor applicable to the semiconductor device in accordance with one embodiment of the present invention is evaluated.

Sampling is formed by a method similar to Sampling 2. Note that the transistor used for this measurement has L of 3 μm, W of 10 cm, L _{ov of} 2 μm, and dW of 0 μm.

Fig. 27 shows the relationship between the open state current of the transistor and the reciprocal of the substrate temperature (absolute temperature) when the current in the open state is measured. In Fig. 27, for the sake of simplicity, the horizontal axis represents a value (1000/T) obtained by multiplying the inverse of the measured substrate temperature by 1000.

A method for measuring the off-state current of a transistor will be briefly described below. Here, for the sake of convenience, the transistor used for this measurement is referred to as a first transistor.

The drain of the first transistor is connected to the floating gate FG, and the floating gate FG is connected to the gate of the second transistor.

First, the first transistor is turned off and then a charge is applied to the floating gate FG. It is noted that a constant drain voltage is applied to the second transistor.

At this time, the charge of the floating gate FG gradually leaks through the first transistor. When the charge of the floating gate FG is leaked, the potential of the source of the second transistor is changed. The amount of charge leakage from the first transistor is estimated from the amount of change in the potential of the source with respect to time; therefore, the off-state current can be measured.

Fig. 27 shows that the off-state current per micrometer channel width of the formed transistor was 2 × 10 ^-21 /μm (2 zA/μm) when the measured substrate temperature was 85 °C.

Therefore, the results show that the open state current of the formed transistor is remarkably small.

As described above, the high reliability transistor can be formed by using an oxide semiconductor film containing a small amount of impurities.

Further, a transistor having excellent electrical characteristics can be obtained.

This embodiment can be implemented in a suitable combination with the structure described in any of the other embodiments.

(Example 2)

In this embodiment, a liquid crystal display device manufactured by using the transistor described in Embodiment 1 will be described. Note that although an example in which a transistor according to an embodiment of the present invention is applied to the liquid crystal display device is described in this embodiment, an embodiment of the present invention is not limited thereto. For example, application of a transistor in accordance with one embodiment of the present invention to an electroluminescent (EL) display device will be readily apparent to those skilled in the art.

Figure 9 is a circuit diagram of an active matrix liquid crystal display device. The liquid crystal display device includes source lines SL_1 to SL_a, gate lines GL_1 to GL_b, and a plurality of pixels 2200. The pixels 2200 each include a transistor 2230, a capacitor 2220, and a liquid crystal element 2210. The pixel portion in the liquid crystal display device includes pixels 2200 arranged in a matrix. Note that "source line SL" and "gate line GL" only mean the source line and the gate line, respectively.

As the transistor 2230, the transistor described in Embodiment 1 can be used. By using a transistor according to an embodiment of the present invention, a liquid crystal display device having high display quality and high reliability can be obtained.

The gate line GL is connected to the gate of the transistor 2230, the source line SL is connected to the source of the transistor 2230, and the drain of the transistor 2230 is connected to one of the capacitor electrodes of the transistor 2220 and the liquid crystal element One of the 2210 pixel electrodes. The other capacitor electrode of the transistor 2220 and the other pixel electrode of the liquid crystal element 2210 are connected to the common electrode. Note that the common electrode can be formed in the same layer as the gate line GL by using the same material as the gate line GL.

Further, the gate line GL is connected to the gate driver circuit. The gate driver circuit can include the transistor described in Embodiment 1.

The source line SL is connected to the source driver circuit. The source driver circuit can include the transistor described in Embodiment 1.

It is noted that either or both of the gate driver circuit and the source driver circuit can be formed on separately prepared substrates and by using, for example, glass flip-chip (COG), wire bonding, or tape-and-reel Automatic bonding (TAB) methods are connected.

Since the transistor is easily destroyed by static electricity or the like, the protection circuit is preferably provided. The protection circuit is preferably formed by using a non-linear element.

When a potential is applied to the gate line GL and is higher than or equal to the threshold voltage of the transistor 2230, the charge supplied from the source line SL flows with the gate current of the transistor 2230 and is stored in the capacitor 2220. . In charge After one column is energized, the transistor 2230 in the column is turned off and the voltage application from the source line SL is stopped; however, the necessary voltage can be maintained by the charge accumulated in the capacitor 2220. Next, the capacitor 2220 in the next column is charged. In this way, the capacitors in the first column to the second column are charged.

Since the current in the open state of the transistor 2230 is low, the charge stored in the capacitor 2220 is not easily lost and the capacitance of the capacitor 2220 can be lowered, so that the power consumption required for charging can be reduced.

Therefore, by using the transistor according to one embodiment of the present invention, a liquid crystal display device having low power consumption, high display quality, and high reliability can be obtained.

This embodiment can be implemented in a suitable combination with the structure described in any of the other embodiments.

(Example 3)

In this embodiment, an example in which a memory (which is a semiconductor device) is manufactured by using the transistor described in Embodiment 1 will be described.

Typical examples of volatile memory include dynamic random access memory (DRAM, which stores data by selecting a transistor included in a memory element and accumulating charges in a capacitor) and static random access memory (SRAM) It maintains the stored data by using a circuit such as a flip-flop.

The transistor described in Example 1 can be applied to a portion of the transistor included in the memory.

An example of a memory cell included in the semiconductor device to which the transistor described in Embodiment 1 is applied will be described with reference to Figs. 10A to 10C.

Figure 10A is a cross-sectional view of the memory cell. The transistor 3340 includes a base insulating film 3102 over the substrate 3100, a protective film 3120 disposed on the periphery of the base insulating film 3102, and an oxide semiconductor film 3106 disposed over the base insulating film 3102 and the protective film 3120. A high resistance region 3106a and a low resistance region 3106b are provided; a gate insulating film 3112 disposed over the oxide semiconductor film 3106; and the oxide semiconductor film 3106 is overlapped with the gate electrode 3104 and the gate insulating film 3112 is located therebetween a gate electrode 3104; a sidewall insulating film 3124 disposed in contact with a side surface of the gate electrode 3104; and a pair of electrodes 3116 disposed in contact with at least the oxide semiconductor film 3106.

Here, the substrate 3100, the base insulating film 3102, the protective film 3120, the oxide semiconductor film 3106, the gate insulating film 3112, the gate electrode 3104, the sidewall insulating film 3124, and the pair of electrodes 3116 may be similarly used by using a substrate, respectively. 100, a method of providing a base insulating film 502, a protective film 520, an oxide semiconductor film 506, a gate insulating film 512, a gate electrode 504, a sidewall insulating film 524, and a pair of electrodes 516.

Further, the transistor 3340 includes an interlayer insulating film 3328 disposed to cover the transistor 3340, and an electrode 3326 disposed over the interlayer insulating film 3328. The capacitor 3330 includes one of a pair of electrodes 3116, an interlayer insulating film 3328, and an electrode 3326. Although parallel plate capacitors are shown in the drawings, stacked capacitors or trench capacitors may alternatively Used to increase capacitance. The interlayer insulating film 3328 can be provided by using a method and material similar to the protective insulating film 518. Electrode 3326 can be provided by using a method and material similar to a pair of electrodes 516.

Further, the transistor 3340 includes an interlayer insulating film 3118 provided to cover the interlayer insulating film 3328 and the electrode 3326, and the other connected to the pair of electrodes 3116 via the opening formed in the interlayer insulating film 3118 and the interlayer insulating film 3328. Wiring 3122. Although not shown, the protective film may be disposed to cover the interlayer insulating film 3118 and the wiring 3122. With the protective film, a small amount of leakage current due to surface conductivity of the interlayer insulating film 3118 can be reduced and thus the off-state current of the transistor can be reduced. The wiring 3122 can be provided by using a method and material similar to the wiring 522.

Fig. 10B is a circuit diagram of the memory cell in Fig. 10A. The memory cell includes a transistor Tr and a capacitor C connected to one of a source and a drain of the transistor Tr. It is noted that the electrode of the capacitor C which is not connected to one of the source and the drain of the transistor Tr is grounded. The gate of the transistor Tr is connected to the word line WL, and the one of the source and the drain of the transistor Tr is connected to the bit line BL. The bit line BL is connected to the sense amplifier SAmp. It is noted that the transistor Tr and the capacitor C correspond to the transistor 3340 and the capacitor 3330, respectively.

It is known that the potential held in the capacitor C gradually decreases with time as shown in Fig. 10C due to the off-state current of the transistor Tr. This potential changes from V0 to V1 by charging down to VA over time (this is the limit for reading data 1). This period is called the hold period T_1. Therefore, in the case of the second-order DRAM, the re-new operation needs to be performed in the sustain period T_1.

Here, when the transistor 3340 is used as the transistor Tr, the off-state current of the transistor Tr may be remarkably small, so that the sustain period T_1 is long. In other words, the interval between the re-operations can be extended; therefore, the power consumption of the memory cell can be reduced. Further, since the transistor Tr is highly reliable, the memory cell can have high reliability.

For example, in the memory cell, the current is 1 × 10 ^-18 A or lower, preferably 1 × 10 ^-21 A or lower, more preferably 1 × 10 ^-24 A or lower by using the off-state current. In the case where crystals are formed, the interval between the re-operations may be several tens of seconds to several tens of years.

As described above, the use of a transistor according to an embodiment of the present invention allows a semiconductor device having high reliability and low power consumption to be formed.

Next, an example of a memory cell included in the semiconductor device to which the transistor described in Embodiment 1 is applied (which is different from the examples in Figs. 10A to 10C) will be described with reference to Figs. 11A to 11C.

Figure 11A is a cross-sectional view of the memory cell. The transistor 3350 includes a base insulating film 3382 over the substrate 3100, a semiconductor film 3384 disposed over the base insulating film 3382 and including a first resistive region 3384a, a second resistive region 3384b, and a third resistive region 3384c. a gate insulating film 3386 over the film 3384; a gate electrode 3392 disposed to overlap the first resistive region 3384a with the gate insulating film 3386 therebetween; and a sidewall insulating film disposed to be in contact with the side surface of the gate electrode 3392 3394. The order of decreasing resistance in the semiconductor film 3384 is as follows: A resistor region 3384a, a second resistor region 3384b, and a third resistor region 3384c. In the first resistance region 3384a, the channel is formed when a voltage higher than or equal to the threshold voltage of the transistor 3350 is applied to the gate electrode 3392. Although not shown, a pair of electrodes in contact with the third resistance region 3384c may be provided.

As the transistor 3350, a method is formed by using a semiconductor film which is different from the oxide semiconductor film and which contains a Group 14 element such as a polycrystalline germanium film, a single crystal germanium film, a polycrystalline germanium film, or a single crystal germanium film. A transistor, or a transistor formed by using the oxide semiconductor film described in Embodiment 1, can be used.

Further, the interlayer insulating film 3396 is disposed in contact with the transistor 3350. It is noted that the surface of the interlayer insulating film 3396 is the surface on which the transistor 3340 is formed; therefore, the surface of the interlayer insulating film 3396 is planarized as much as possible. Specifically, the Ra of the surface of the interlayer insulating film 3396 is preferably 1 nm or less, preferably 0.3 nm or less, and more preferably 0.1 nm or less.

The interlayer insulating film 3396 may have a single layer structure or a stacked layer structure, and a layer in contact with the oxide semiconductor film 3106 is preferably an insulating film from which oxygen is released by heat treatment.

The transistor 3340 is disposed over the interlayer insulating film 3396. One of the pair of electrodes 3116 of the transistor 3340 is electrically connected to the gate electrode 3392 of the transistor 3350. The capacitor 3330 includes one of a pair of electrodes 3116 included in the transistor 3340, an interlayer insulating film 3328, and an electrode 3326. Although parallel plate capacitors are shown in the figure, stacked type A container or trench type capacitor can alternatively be used to increase the capacitance.

Figure 11B is a circuit diagram of the memory cell in Figure 11A. The memory unit cell includes a transistor Tr_1, a transistor Tr_2, a capacitor C, and a drain connected to the capacitor C, the transistor Tr_1, and a floating gate FG of the gate of the transistor Tr_2. The gate of the transistor Tr_1 is connected to the gate line GL_1. The source of the transistor Tr_1 is connected to the source line SL_1. The source of the transistor Tr_2 is connected to the source line SL_2. The drain of the transistor Tr_2 is connected to the drain line DL_2. The electrode of the capacitor C not connected to the floating gate FG is connected to the capacitor line CL. It is noted that the transistor Tr_1, the transistor Tr_2, and the capacitor C correspond to the transistor 3340, the transistor 3350, and the capacitor 3330, respectively.

The memory cell described in this embodiment utilizes a threshold variation of the transistor Tr_2 depending on the potential of the floating gate FG. For example, the FIG. 11C shows the relationship between the drain current flowing through the electric potential V _CL Tr_2 crystal capacitor line CL I _ds _2.

Here, the potential of the floating gate FG can be adjusted via the transistor Tr_1. For example, the potential of the source line SL_1 is set to VDD. In this case, when the potential of the gate line GL_1 is set to be higher than or equal to the potential obtained by adding VDD to the threshold voltage Vth of the transistor Tr_1, the potential of the floating gate FG may be HIGH. Further, when the potential of the gate line GL_1 is set to be lower than or equal to the threshold voltage Vth of the transistor Tr_1, the potential of the floating gate FG may be LOW.

Therefore, a V _CL -I _ds _2 curve (FG=LOW) or a V _CL -I _ds _2 curve (FG=HIGH) can be obtained. That is, when the potential of FG is LOW, I _ds _2 is small at V _CL of 0 V; therefore, data 0 is stored. Further, when the potential of the FG is HIGH, I _ds _2 is large at V _CL of 0 V; therefore, the data 1 is stored. In this way, the data can be stored.

Since the off-state current of the transistor Tr_1 can be made extremely small when the transistor 3340 is used as the transistor Tr_1, the unintentional leakage of the charge accumulated in the floating gate FG of the 11Bth diagram of the transistor Tr_1 can be suppressed. . Therefore, the information can be kept for a long time. Further, the field effect mobility of the transistor Tr_1 is high; therefore, the memory cell can be operated at a high speed.

As described above, the use of the transistor according to one embodiment of the present invention allows a semiconductor device having high reliability and low power consumption and capable of high speed operation to be formed.

This embodiment can be combined with any of the other embodiments.

(Example 4)

A central processing unit (CPU) can be formed by using at least a portion of the CPU using the transistor described in Embodiment 1 and the semiconductor device described in Embodiment 3.

Fig. 12A is a block diagram showing a specific configuration of the CPU. The CPU in FIG. 12A includes an arithmetic logic unit (ALU) 1191 on the substrate 1190, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, and a register control. 1197, bus interface (Bus I/F) 1198, rewritable ROM 1199, and ROM interface (ROM I / F) 1189. A semiconductor substrate, an SOI substrate, a glass substrate, or the like is used as the substrate 1190. ROM 1199 and ROM interface 1189 can be placed over separate wafers. It is needless to say that the CPU shown in Fig. 12A is an example in which only the configuration is simplified, and the actual CPU has various configurations depending on the application.

An instruction input to the CPU via the bus interface 1198 is input to the instruction decoder 1193 and decoded in the instruction decoder, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timely Sequence controller 1195.

The ALU controller 1192, the interrupt controller 1194, the scratchpad controller 1197, and the timing controller 1195 perform various control fingers in accordance with the decoded instructions. In particular, ALU controller 1192 generates signals to control the operation of ALU 1191. While the CPU is executing the program, the interrupt controller 1194 processes the interrupt request from the external input/output device or peripheral circuits depending on its priority or mask state. The scratchpad controller 1197 generates the address of the scratchpad 1196 and reads data/write data from the scratchpad 1196 to the scratchpad 1196 depending on the state of the CPU.

The timing controller 1195 generates instructions for controlling the operational timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the scratchpad controller 1197. For example, the timing controller 1195 includes an internal clock generator (to generate the internal clock signal CLK2 according to the reference clock signal CLK1), and supplies the clock signal CLK2 to the above circuit.

In the CPU shown in FIG. 12A, the semiconductor according to Embodiment 3 The device is placed in the register 1196.

In the CPU shown in Fig. 12A, the register controller 1197 selects the operation of holding the data in the register 1196 in response to an instruction from the ALU 1191. That is, the semiconductor device in the register 1196 determines which of the opposite-turning elements and capacitors to retain the data. The power supply voltage is applied to the semiconductor device in the register 1196 when the data is selected by the reverse-rotating element. When the hold data is selected by the capacitor, the data is rewritten into the capacitor, and the power supply voltage can be stopped from being supplied to the semiconductor memory device in the register 1196.

The power supply can be stopped by a switching element provided between the semiconductor device group and the node (the power supply potential VDD or the power supply potential VSS is supplied) as shown in FIG. 12B or FIG. 12C. The circuits shown in Figures 12B and 12C will be described below.

12B and 12C each show a memory circuit including the transistor described in Embodiment 1 (the switching state current is remarkably small, which is used to control the switching element supplied to the power supply potential of the semiconductor device) Configure the instance.

The storage device shown in FIG. 12B includes a switching element 1141 and a semiconductor device group 1143 (including a plurality of semiconductor devices 1142). Specifically, as each of the semiconductor devices 1142, the semiconductor device described in Embodiment 3 can be used. The high level power supply potential VDD is supplied to each of the semiconductor devices 1142 included in the semiconductor device group 1143 via the switching element 1141. Further, the potential of the signal IN and the low level power supply potential VSS are supplied to the semiconductor device group. Each of the semiconductor devices 1142 included in 1143.

In Fig. 12B, as the switching element 1141, the transistor described in Embodiment 1 can be used. The switching of the transistor is controlled by a signal SigA input to its gate.

Note that Fig. 12B shows a configuration in which the switching element 1141 includes only one transistor; however, one embodiment of the present invention is not limited thereto. Switching element 1141 can include a plurality of transistors. In the case where the switching element 1141 includes a plurality of transistors used as switching elements, the plurality of transistors may be interconnected by a combination of parallel, series, or parallel connections and series connections.

FIG. 12C illustrates an example of a storage device in which the low-level power supply potential VSS is supplied to each of the semiconductor devices 1142 included in the semiconductor device group 1143 via the switching element 1141. The supply of the low level power supply potential VSS to each of the semiconductor devices 1142 included in the semiconductor device group 1143 can be controlled by the switching element 1141.

When the switching element is disposed between the semiconductor device group and the node (the power supply potential VDD or the power supply potential VSS is supplied), the data can be held even when the operation of the CPU is temporarily stopped and the supply of the power supply voltage is stopped; Therefore, power consumption can be reduced. For example, when a user of a personal computer does not input data to an input device such as a keyboard, the operation of the CPU can be stopped, so that power consumption can be reduced.

Further, when the transistor described in Embodiment 1 and the semiconductor device described in Embodiment 3 are used, the CPU can operate at high speed while consuming less power.

Although the CPU is provided herein as an example, an embodiment of the present invention can also be applied to an LSI such as a digital signal processor (DSP), a custom LSI, or a field programmable gate array (FPGA).

This embodiment can be implemented in a suitable combination with any of the other embodiments.

(Example 5)

In this embodiment, an example of an electronic device to which any of Embodiments 1 to 4 can be applied will be described.

Figure 13A shows a portable information terminal. The portable information terminal includes a housing 4300, a button 4301, a microphone 4302, a display portion 4303, a speaker 4304, and a camera 4305, and has the function of a mobile phone.

Figure 13B shows a display. The display includes a housing 4310 and a display portion 4311.

Figure 13C shows a digital still camera. The digital still camera includes a housing 4320, a button 4321, a microphone 4322, and a display portion 4323.

By using a transistor according to an embodiment of the present invention, an electronic device having low power consumption and good quality can be obtained.

This embodiment can be implemented in a suitable combination with any of the other embodiments.

[Example 1]

In this case, the pressure and the leak rate in the deposition chamber of the sputtering apparatus to which one embodiment of the present invention is applied will be described.

The deposition chamber has a volumetric capacity of 1.40 m ³ and is provided with a turbomolecular pump and a cryopump in parallel with each other. As an auxiliary pump, a rough vacuum pump is also provided.

After the air in the deposition chamber was released, the deposition chamber was evacuated by using the turbomolecular pump for 6 hours.

When the total pressure in the deposition chamber reaches 5 × 10 ^-4 Pa, the low temperature well is operated. Thereafter, the baking of the chamber was carried out at 400 ° C for 12 hours.

Next, dummy film formation was carried out in the deposition chamber until the film was deposited to 10 μm (until the complete power consumption reached 50 kWh). It is noted that the dummy film formation is carried out under the following conditions: substrate temperature of 250 ° C, deposition pressure of 0.3 Pa, deposition power of 9 kW (AC), deposition gas of 50 sccm of argon and 50 sccm of oxygen, target and The distance between the substrates was 150 mm and the deposition rate was 920 s/film. For the formation of the dummy film, an In-Ga-Zn-O target having an atomic ratio of In:Ga:Zn=1:1:1 was used.

In the deposition chamber from which the impurities are sufficiently reduced, the total pressure is 2.16 × 10 ^-5 Pa; the partial pressure of the gas having the mass-to-charge ratio (m/z) 2 is 8.63 × 10 ^-6 Pa; and the mass-to-charge ratio (m) /z) The partial pressure of the gas of 18 is 8.43 × 10 ^-6 Pa; the partial pressure of the gas having the mass-to-charge ratio (m/z) 28 is 1.66 × 10 ^-5 Pa; and the mass-to-charge ratio (m/z) 40 The partial pressure of the gas (for example, an argon atom) is 3.87 × 10 ^-7 Pa; and the partial pressure of the gas having a mass-to-charge ratio (m/z) 44 is 5.33 × 10 ^-6 Pa.

Figure 29 shows the total pressure and partial pressure of the molecules in the deposition chamber. The white circle indicates the total pressure; the black circle indicates the partial pressure of the gas having the mass-to-charge ratio (m/z) 2; the white triangle indicates the partial pressure of the gas having the mass-to-charge ratio (m/z) 18; the black triangle indicates the mass charge a partial pressure of a gas of (m/z) 28; a white square represents a partial pressure of a gas having a mass-to-charge ratio (m/z) of 40; and a black square represents a fraction of a gas having a mass-to-charge ratio (m/z) of 44. Pressure. Note that Fig. 29 shows the relationship between the pressure in the deposition chamber and the elapsed time after the evacuation (with the vacuum pump) is stopped. These pressures were measured by using a Qulee CGM-051 (a quadrupole mass analyzer (also known as Q-mass) manufactured by ULVAC Ltd.).

The leak rate estimated from the obtained pressure is as follows. The total leak rate of the deposition chamber is 9.84×10 ^-6 Pa. m ³ /s. The gas leakage rate with a mass-to-charge ratio (m/z) 2 is 3.24×10 ^-6 Pa. m ³ /s. The gas leakage rate with mass-to-charge ratio (m/z) 18 is 4.46×10 ^-9 Pa. m ³ /s. The gas leakage rate with mass-to-charge ratio (m/z) 28 is 7.74×10 ^-6 Pa. m ³ /s. The gas leakage rate with mass-to-charge ratio (m/z) 40 is 8.72×10 ^-8 Pa. m ³ /s. The gas leakage rate with mass-to-charge ratio (m/z) 44 is 7.89×10 ^-7 Pa. m ³ /s.

These leak rates are calculated from the relationship between the pressure in the deposition chamber and the elapsed time after evacuation (by vacuum pump) is stopped. Specifically, the leak rate is obtained by dividing the difference between the pressure after one minute of vacuuming (with a vacuum pump) and the pressure of 15 minutes after stopping the vacuum (by vacuum pump) by the time, and multiplying the result by Take the volumetric capacity of the deposition chamber.

[Example 2]

In this example, a heated inert gas such as a heated rare gas is supplied to increase the pressure in the deposition chamber, and after a certain period of time, a heat treatment for evacuating the deposition chamber is performed to further reduce the implementation. The impurities present in the deposition chamber of the sputtering apparatus described in Example 1.

Specifically, argon gas at 70 ° C was supplied to the deposition chamber for more than one hour, so that the pressure therein became 20 Pa, and then 10 minutes was performed by evacuation by a vacuum pump. Here, this process is repeated 10 times.

In the deposition chamber from which the impurities are further reduced, the total pressure is 1.34 × 10 ^-5 Pa; the partial pressure of the gas having the mass-to-charge ratio (m/z) 2 is 7.58 × 10 ^-6 Pa; and the mass-to-charge ratio (m) The partial pressure of the gas of /z)18 is 5.79×10 ^-6 Pa; the partial pressure of the gas having the mass-to-charge ratio (m/z) 28 is 8.40×10 ^-6 Pa; and the mass-to-charge ratio (m/z) 40 The partial pressure of the gas (for example, an argon molecule) is 1 × 10 ^-7 Pa or lower (measured lower limit or lower); and the partial pressure of the gas having a mass-to-charge ratio (m/z) 44 is 1 × 10 ^-7 Pa or lower (lower limit of measurement or lower).

Figure 37 shows the relationship between the pressure in the deposition chamber and the elapsed time after the evacuation (with the vacuum pump) is stopped. These pressures were measured by using a Qulee CGM-051 (a quadrupole mass analyzer manufactured by ULVAC Ltd.). As a gauge head, M-11 (a gauge head manufactured by ULVAC Co., Ltd.) was used.

The leak rate estimated from the obtained pressure is as follows. The total leak rate of the deposition chamber is 6.94×10 ^-6 Pa. m ³ /s. The gas leakage rate of mass-to-charge ratio (m/z) 2 is 3.13×10 ^-6 Pa. m ³ /s. The gas leakage rate with mass-to-charge ratio (m/z) 18 is 3.20×10 ^-9 Pa. m ³ /s. The gas leakage rate with mass-to-charge ratio (m/z) 28 is 3.12×10 ^-6 Pa. m ³ /s. The gas leakage rate with mass-to-charge ratio (m/z) 40 is 7.27×10 ^-8 Pa. m ³ /s. The gas leakage rate with mass-to-charge ratio (m/z) 44 is 3.20×10 ^-7 Pa. m ³ /s.

These leak rates are calculated from the relationship between the pressure in the deposition chamber and the elapsed time after evacuation (by vacuum pump) is stopped. Specifically, the leak rate is obtained by dividing the difference between the pressure after one minute of vacuuming (with a vacuum pump) and the pressure of 15 minutes after stopping the vacuum (by vacuum pump) by the time, and multiplying the result by Take the volumetric capacity of the deposition chamber.

Table 1 shows the comparison between the pressures in Examples 1 and 2 and the comparison between the leak rates.

As described above, heated argon is supplied to increase the pressure in the deposition chamber, and after a certain period of time, the heat treatment for evacuating the deposition chamber is performed so that it exists in the deposition chamber as compared with Example 1. Impurity energy Can be further reduced. This result shows that the release of impurities is reduced, resulting in a decrease in pressure and leakage rate in the deposition chamber.

[Example 3]

In this example, TDS analysis, SIMS, and XRD analysis were performed on the samples formed in the deposition chambers of the sputtering apparatus described in Example 1.

Each of the samples was obtained by forming an In-Ga-Zn-O film on a substrate having a thickness of 100 nm.

The conditions for forming the In-Ga-Zn-O film are as follows.

The substrate temperature was 250 ° C; the deposition pressure was 0.3 Pa; the deposition power was 9 kW (AC); the deposition gas was 50 sccm of argon and 50 sccm of oxygen; the distance between the target and the substrate was 150 mm. As the target, an In-Ga-Zn-O target having an atomic ratio of In:Ga:Zn=1:1:1 was used.

First, TDS analysis is performed.

For TDS analysis, EMD-WA1000S/W (a thermal desorption spectrometer manufactured by ESCO Co., Ltd.) was used.

Figures 32A through 32C show the results of TDS analysis of these samples. Here, Fig. 32A shows the ionic strength of a gas having a mass-to-charge ratio (m/z) 18; Fig. 32B shows the ionic strength of a gas having a mass-to-charge ratio (m/z) 28; and Fig. 32C shows the quality The ionic strength of the gas with a charge ratio (m/z) of 44. In the graphs 32A to 32C, the solid line indicates the ionic strength in the case where the heat treatment is not performed, and the broken line indicates that the heat treatment is performed at 350 ° C for one hour in the nitrogen atmosphere after the film formation and then the heat treatment in the oxidizing atmosphere (containing 80 One hour in vol.% nitrogen and 20 vol.% oxygen) The ionic strength in the case.

Depending on the obtained ionic strength, a gas having a mass-to-charge ratio (m/z) of 18, a gas having a mass-to-charge ratio (m/z) of 28, and a mass-to-charge ratio are necessary in the In-Ga-Zn-O film. The gas release amount of m/z) 44 is reduced by performing heat treatment after forming the In-Ga-Zn-O film.

Second, SIMS implements these samples.

An IMS 7fR manufactured for SIMS, CAMECA, Société par Actions Simplifiée (SAS) was used.

Figure 33 shows the SIMS depth data for hydrogen.

Figure 34 shows the SIMS depth data for carbon.

Figure 35 shows the SIMS depth data for nitrogen.

In the graphs 33 to 35, the solid line indicates the depth data in the case where the heat treatment is not carried out, and the broken line indicates that the heat treatment is performed at 450 ° C for one hour in the nitrogen atmosphere after the film formation and then the heat treatment in the oxidizing atmosphere (containing 80 Depth data in the case of one hour of vol.% nitrogen and 20 vol.% oxygen).

The obtained depth data indicates that the concentrations of carbon and nitrogen are lowered by performing heat treatment after forming the In-Ga-Zn-O film.

Second, XRD analysis is performed on these samples.

The XRD analysis was carried out by using an X-ray diffractometer D8 ADVANCE manufactured by Bruker AXS, and the measurement was carried out by an out-of-plane method.

Figure 36 XRD results of the In-Ga-Zn-O film.

In Figure 36, the solid line indicates that in the case where the heat treatment is not implemented XRD results, and the dotted line indicates that the heat treatment was carried out at 450 ° C for one hour in a nitrogen atmosphere after the film formation and then heat treatment was carried out for one hour in an oxidizing atmosphere (containing 80 vol.% of nitrogen and 20 vol.% of oxygen). The XRD results in .

Fig. 36 shows that each sample has a plurality of crystallographic peaks and the intensity indicating the crystallinity peak is increased by performing heat treatment after film formation.

It was found that each of the In-Ga-Zn-O films (which are described in Example 1) formed in the deposition chamber of the sputtering apparatus had a low impurity concentration and included a crystalline region.

The application is based on the Japanese Patent Application No. 2011-117354 filed on May 25, 2011, and the Japanese Patent Application Serial No. 2011-147189 filed on Jan. This is incorporated herein by reference.

10, 10a, 10b, 10c‧‧‧ deposition room

11‧‧‧Substrate supply room

12a, 12b‧‧‧ load lock room

13‧‧‧Transfer room

14‧‧‧Card gate

15‧‧‧Substrate heating room

20a, 20b‧‧‧ deposition room

22a, 22b‧‧‧ load lock room

25‧‧‧Substrate heating room

32‧‧‧ Target

34‧‧‧ Target bracket

42‧‧‧Substrate bracket

44‧‧‧Based heater

46‧‧‧Baffle shaft

48‧‧ ‧ baffle

50‧‧‧RF power supply

52‧‧‧ Matching box

54‧‧‧ purifier

55‧‧‧mass flow controller

56‧‧‧ gas supply

57‧‧‧Gas heating system

58‧‧‧Vacuum pump

59‧‧‧Vacuum pump

68‧‧‧ counter electrode

100‧‧‧Substrate

102‧‧‧Base insulating film

104‧‧‧gate electrode

106‧‧‧Oxide semiconductor film

112‧‧‧gate insulating film

116‧‧‧A pair of electrodes

204‧‧‧gate electrode

206‧‧‧Oxide semiconductor film

212‧‧‧Gate insulation film

216‧‧‧A pair of electrodes

304‧‧‧gate electrode

306‧‧‧Oxide semiconductor film

312‧‧‧gate insulating film

316‧‧‧A pair of electrodes

318‧‧‧Protective insulation film

406‧‧‧Oxide semiconductor film

416‧‧‧A pair of electrodes

418‧‧‧Protective insulation film

502‧‧‧Base insulating film

504‧‧‧gate electrode

506‧‧‧Oxide semiconductor film

506a‧‧‧High resistance zone

506b‧‧‧low resistance zone

507‧‧‧Oxide semiconductor film

507a‧‧‧High resistance zone

507b‧‧‧low resistance zone

512‧‧‧gate insulating film

516‧‧‧A pair of electrodes

518‧‧‧Protective insulation film

520‧‧‧Protective film

522‧‧‧Wiring

524‧‧‧Sidewall insulation film

700‧‧‧Substrate

702‧‧‧Base insulating film

704‧‧‧gate electrode

706‧‧‧Oxide semiconductor film

712‧‧‧gate insulating film

716‧‧‧A pair of electrodes

718‧‧‧Interlayer insulating film

722‧‧‧Wiring

728‧‧‧Protective insulation film

1141‧‧‧Switching components

1142‧‧‧Semiconductor device

1143‧‧‧Semiconductor device group

1189‧‧‧ROM interface

1190‧‧‧Substrate

1191‧‧‧Arithmetic logic unit

1192‧‧‧ALU controller

1193‧‧‧ instruction decoder

1194‧‧‧Interrupt controller

1195‧‧‧ Timing controller

1196‧‧‧ register

1197‧‧‧ register controller

1198‧‧‧ bus interface

1199‧‧‧Rewritable ROM

2200‧‧ ‧ pixels

2210‧‧‧Liquid crystal components

2220‧‧‧ capacitor

2230‧‧‧Optoelectronics

3340‧‧‧Optoelectronics

3100‧‧‧Substrate

3102‧‧‧Base insulating film

3104‧‧‧Gate electrode

3106‧‧‧Oxide semiconductor film

3106a‧‧‧High resistance zone

3106b‧‧‧Low resistance zone

3112‧‧‧gate insulating film

3116‧‧‧A pair of electrodes

3118‧‧‧Interlayer insulating film

3120‧‧‧Protective film

3122‧‧‧Wiring

3326‧‧‧Electrode

3328‧‧‧Interlayer insulating film

3330‧‧‧ capacitor

3350‧‧‧Optoelectronics

3382‧‧‧Base insulating film

3384‧‧‧Semiconductor film

3384a‧‧‧First resistance zone

3384b‧‧‧second resistance zone

3384c‧‧‧ Third resistance zone

3386‧‧‧gate insulating film

3392‧‧‧Gate electrode

3394‧‧‧Sidewall insulation film

3396‧‧‧Interlayer insulating film

4300‧‧‧Shell

4301‧‧‧ button

4302‧‧‧Microphone

4303‧‧‧Display section

4304‧‧‧Speakers

4305‧‧‧Photographer

4310‧‧‧Shell

4311‧‧‧Display section

4320‧‧‧Shell

4321‧‧‧ button

4322‧‧‧Microphone

4323‧‧‧Display section

In the accompanying drawings: FIGS. 1A and 1B are plan views showing an example of a deposition apparatus; FIGS. 2A and 2B are diagrams showing a deposition chamber and a substrate heating chamber, respectively; FIGS. 3A and 3B are diagrams showing an example of a transistor; 4A and 4B are top and cross-sectional views showing an example of a transistor; FIGS. 5A and 5B are a plan view and a cross-sectional view showing an example of a transistor; FIGS. 6A and 6B are diagrams showing A top view and a cross-sectional view of an example of a transistor; FIGS. 7A to 7C are plan views and cross-sectional views showing an example of a transistor; FIGS. 8A and 8B are a plan view and a cross-sectional view showing an example of a transistor; A circuit diagram showing an example of a display device; FIG. 10A is a cross-sectional view showing an example of a semiconductor device, FIG. 10B is a circuit diagram, and FIG. 10C is a graph showing electrical characteristics; and FIG. 11A is a view showing a semiconductor device; FIG. 11B is a circuit diagram, and FIG. 11C is a graph showing electrical characteristics; FIG. 12A is a block diagram showing a specific example of a CPU according to an embodiment of the present invention, and FIGS. 12B and 12C The figure shows a circuit diagram of a part of the CPU; Figures 13A to 13C A perspective view showing an example of an electronic device according to an embodiment of the present invention; FIGS. 14A to 14E are diagrams showing a crystal structure of an oxide semiconductor according to an embodiment of the present invention; and FIGS. 15A to 15C are diagrams showing A crystalline structure of an oxide semiconductor according to an embodiment of the invention; FIGS. 16A to 16C illustrate a crystal structure of an oxide semiconductor according to an embodiment of the present invention; and FIGS. 17A and 17B illustrate an oxide according to an embodiment of the present invention. The crystal structure of the semiconductor; Figure 18 is a graph showing the V _gs dependence of field-effect mobility (which is obtained by calculation); Figures 19A to 19C are the V _gs dependence of each showing I _ds and field-effect mobility. Graph of the properties (which are obtained by calculation); Figures 20A to 20C are graphs showing the V _gs dependence of the I _ds and the field effect mobility (which is obtained by calculation); 21A to 21C The graphs show the V _gs dependence of the I _ds and the field effect mobility (which is obtained by calculation); the 22A and 22B are the top view and the cross-sectional view of the transistor; the 23A and 23B are the display samples of each display. V _gs -I _ds characteristics of the crystals of 1 and 2 and the field mobility Line graph; Figures 24A and 24B are graphs showing _Vgs - _Ids between before and after the BT test of each of the crystals of Sample 1; Figures 25A and 25B are BT tests of the transistors showing Sample 2 A graph of _Vgs - _Ids between the front and the back; a 26A is a graph showing the relationship between the substrate temperature of the transistor of Sample 2 and the threshold voltage, and FIG. 26B is a substrate showing the transistor of Sample 2. A graph showing the relationship between the temperature and the field effect mobility; FIG. 27 is a graph showing the open state current of the transistor formed by using the oxide semiconductor film; and FIG. 28 is a graph showing the XRD result of the oxide semiconductor film. FIG. 29 is a graph showing the relationship between the pressure in the deposition chamber and the elapsed time after the operation of the vacuum pump is stopped; and FIG. 30 is a view showing the oxide semiconductor according to an embodiment of the present invention. A pattern of a crystal structure; FIGS. 31A and 31B are diagrams showing a crystal structure of an oxide semiconductor according to an embodiment of the present invention; and FIGS. 32A to 32C are graphs showing TDS analysis results of each oxide semiconductor film. Figure 33 shows the oxide A graph of the SIMS result of the conductor film; Fig. 34 is a graph showing the SIMS result of the oxide semiconductor film; Fig. 35 is a graph showing the SIMS result of the oxide semiconductor film; and Fig. 36 is a graph showing the oxide semiconductor film A graph of the XRD results; FIG. 37 is a graph showing the relationship between the pressure in the deposition chamber and the elapsed time after the operation of the vacuum pump is stopped; FIGS. 38A to 38C are diagrams showing the connection method of each of the gas heating systems. Figure 39A to 39D are diagrams showing a crystal structure of an oxide semiconductor according to an embodiment of the present invention;

10a, 10b, 10c‧‧‧ deposition room

11‧‧‧Substrate supply room

12a, 12b‧‧‧ load lock room

13‧‧‧Transfer room

14‧‧‧Card gate

15‧‧‧Substrate heating room

Claims (14)

A method of forming an oxide semiconductor film, comprising: supplying a gas containing one or more selected from the group consisting of a rare gas and oxygen into a deposition chamber, wherein the measurement is performed by a quadrupole mass analyzer in the deposition chamber a gas having a mass-to-charge ratio of 18, a gas having a mass-to-charge ratio of 28, and a gas having a mass-to-charge ratio of 44 each having a partial pressure of 3 × 10 ^-5 Pa or less; and being formed in the deposition chamber by sputtering An oxide semiconductor film. A method of forming an oxide semiconductor film, comprising: supplying a gas containing one or more selected from the group consisting of a rare gas and oxygen into a deposition chamber, wherein the measurement is performed by a quadrupole mass analyzer in the deposition chamber The gas-to-charge ratio 44 gas, the gas having a mass-to-charge ratio of 18, and the gas having a mass-to-charge ratio of 28 have a leakage rate of 3 × 10 ^-6 Pa, respectively. m ³ /s or lower, 1 × 10 ^-7 Pa. m ³ /s or lower, and 1 × 10 ^-5 Pa. m ³ /s or lower: and an oxide semiconductor film is formed in the deposition chamber by sputtering. A semiconductor device comprising: an oxide crystal comprising: an oxide semiconductor film; a gate insulating film in contact with the oxide semiconductor film; and a gate electrode interposed between the gate insulating film and the gate insulating film The electrode, wherein the carbon concentration in the oxide semiconductor film measured by secondary ion mass spectrometry is less than 5 × 10 ¹⁹ atoms/cm ³ . The semiconductor device according to claim 3, wherein the concentration of hydrogen in the oxide semiconductor film measured by secondary ion mass spectrometry is less than 5 × 10 ¹⁹ atoms/cm ³ . The semiconductor device according to claim 3, wherein the nitrogen concentration in the oxide semiconductor film measured by secondary ion mass spectrometry is less than 5 × 10 ¹⁹ atoms/cm ³ . A method of manufacturing a semiconductor device, comprising: forming an oxide semiconductor film, a gate insulating film adjacent to the oxide semiconductor film, and a gate electrode interposed between the gate insulating film and the gate insulating film An electrode, wherein the oxide semiconductor film is formed by supplying a gas containing one or more selected from the group consisting of a rare gas and oxygen into a deposition chamber, and a quadrupole mass analyzer in the deposition chamber The partial pressure of the gas having a mass-to-charge ratio of 44 measured is 3 × 10 ^-5 Pa or lower; and a sputtering method in which electric power is applied to the target is performed in the deposition chamber. A method of manufacturing a semiconductor device according to claim 6, wherein the gate electrode is formed over the oxide semiconductor film. A method of manufacturing a semiconductor device according to claim 6, wherein the oxide semiconductor film is formed over the gate electrode. A method of manufacturing a semiconductor device according to claim 6, wherein a partial pressure of a gas having a mass-to-charge ratio of 18 measured by a quadrupole mass spectrometer in the deposition chamber is 3 × 10 ^-5 Pa or less. A method of manufacturing a semiconductor device according to claim 6, wherein a gas having a mass-to-charge ratio of 28 measured by a quadrupole mass spectrometer in the deposition chamber has a partial pressure of 3 × 10 ^-5 Pa or less. The method of manufacturing a semiconductor device according to claim 6, wherein a gas having a mass-to-charge ratio 18 and a gas having a mass-to-charge ratio 28 measured by a quadrupole mass spectrometer in the deposition chamber are each 3 ×10 ^-5 Pa or lower. A method of manufacturing a semiconductor device, comprising: forming a transistor including an oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, and overlapping the oxide semiconductor film and inserting the gate insulating film a gate electrode interposed therebetween, wherein the oxide semiconductor film is formed by supplying a gas containing one or more selected from the group consisting of a rare gas and oxygen into a deposition chamber, in the deposition chamber The gas leakage rate of the gas having a mass-to-charge ratio of 44 measured by a quadrupole mass spectrometer is 3×10 ^-6 Pa. m ³ /s or lower; and sputtering is carried out in the deposition chamber. The method of manufacturing a semiconductor device according to claim 12, wherein a gas having a mass-to-charge ratio of 18 measured by a quadrupole mass spectrometer in the deposition chamber has a leak rate of 1 × 10 ^-7 Pa. m ³ /s or lower. The method of manufacturing a semiconductor device according to claim 12, wherein a gas having a mass-to-charge ratio of 28 measured by a quadrupole mass spectrometer in the deposition chamber has a leak rate of 1 × 10 ^-5 Pa. m ³ /s or lower.