TW201308401A - 藉由固相擴散形成超淺硼摻雜區域之方法 - Google Patents
藉由固相擴散形成超淺硼摻雜區域之方法 Download PDFInfo
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- TW201308401A TW201308401A TW101111467A TW101111467A TW201308401A TW 201308401 A TW201308401 A TW 201308401A TW 101111467 A TW101111467 A TW 101111467A TW 101111467 A TW101111467 A TW 101111467A TW 201308401 A TW201308401 A TW 201308401A
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- boron dopant
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- 229910052796 boron Inorganic materials 0.000 title claims abstract description 90
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 title claims abstract description 88
- 238000000034 method Methods 0.000 title claims abstract description 83
- 238000009792 diffusion process Methods 0.000 title description 5
- 239000007790 solid phase Substances 0.000 title description 5
- 239000002019 doping agent Substances 0.000 claims abstract description 306
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- 239000000376 reactant Substances 0.000 claims abstract description 21
- 150000004767 nitrides Chemical class 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 19
- 239000002243 precursor Substances 0.000 claims abstract description 18
- -1 boron amide Chemical class 0.000 claims abstract description 12
- 238000000059 patterning Methods 0.000 claims abstract description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 37
- 239000007789 gas Substances 0.000 claims description 30
- 238000010438 heat treatment Methods 0.000 claims description 24
- 229910052785 arsenic Inorganic materials 0.000 claims description 13
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 12
- 229910052787 antimony Inorganic materials 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
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- 238000007669 thermal treatment Methods 0.000 abstract 1
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- 229960002594 arsenic trioxide Drugs 0.000 description 3
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- 230000008021 deposition Effects 0.000 description 3
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- 229910052582 BN Inorganic materials 0.000 description 2
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 2
- 239000002879 Lewis base Substances 0.000 description 2
- 125000004183 alkoxy alkyl group Chemical group 0.000 description 2
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- 229910052782 aluminium Inorganic materials 0.000 description 2
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- 125000003118 aryl group Chemical group 0.000 description 2
- 150000001639 boron compounds Chemical class 0.000 description 2
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- 125000003709 fluoroalkyl group Chemical group 0.000 description 2
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- 229910052746 lanthanum Inorganic materials 0.000 description 2
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 2
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- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910052761 rare earth metal Inorganic materials 0.000 description 2
- VSAISIQCTGDGPU-UHFFFAOYSA-N tetraphosphorus hexaoxide Chemical compound O1P(O2)OP3OP1OP2O3 VSAISIQCTGDGPU-UHFFFAOYSA-N 0.000 description 2
- 229910052716 thallium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 1
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- 229910004143 HfON Inorganic materials 0.000 description 1
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 229910052777 Praseodymium Inorganic materials 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
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- 229910010282 TiON Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910006252 ZrON Inorganic materials 0.000 description 1
- 229910052784 alkaline earth metal Inorganic materials 0.000 description 1
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- 229910052786 argon Inorganic materials 0.000 description 1
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- 229910052791 calcium Inorganic materials 0.000 description 1
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- 229910000420 cerium oxide Inorganic materials 0.000 description 1
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- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
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- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
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- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 1
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- 230000001590 oxidative effect Effects 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- PUDIUYLPXJFUGB-UHFFFAOYSA-N praseodymium atom Chemical compound [Pr] PUDIUYLPXJFUGB-UHFFFAOYSA-N 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
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- H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
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- H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
- H01L21/2256—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides through the applied layer
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/31111—Etching inorganic layers by chemical means
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
Abstract
提出一種在基板中形成超淺硼摻雜物區域之方法。在一實施例中,該方法包括利用原子層沉積(ALD)沉積一硼摻雜物層與該基板直接接觸,其中該硼摻雜物層包含藉由硼胺前驅物或有機硼前驅物及反應物氣體之交替氣體暴露所形成之氧化物、氮化物、或氮氧化物。該方法更包括圖案化該硼摻雜物層、以及藉由熱處理使硼從該硼摻雜物層擴散至該基板中,在該基板中形成該超淺硼摻雜物區域。
Description
本申請案係關於審查中之美國專利申請案第13/077,721號,其發明名稱為「METHOD FOR FORMING ULTRA-SHALLOW DOPING REGIONS BY SOLID PHASE DIFFUSION」,且此申請案之全部內容係合併於此做為參考文獻。
一般而言,本發明關於半導體元件及其形成方法;具體而言,本發明關於超淺摻雜物區域之形成,其係藉由固相擴散從摻雜物層進入基板層中。
半導體工業的特徵為,具有在既定的半導體晶片上製造更大、更複雜的電路之趨勢。更大、更複雜的電路係藉由將電路內個別元件之尺寸縮小、以及使元件彼此排列更接近而達成。當例如金氧半導體(MOS)或雙載子電晶體等元件內之個別構件之尺寸縮小、且元件構件彼此更接近時,可獲得改善的電性。然而,必須注意在基板中摻雜區域的形成,以確保有害的電場環境不會生成。
當減少元件構件(例如在MOS元件中之電晶體閘極、及雙載子元件中之射極區域)之尺寸時,也必須減少在半導體基板中所形成之摻雜區域之接面深度。具有均勻摻雜輪廓及高表面濃度之淺接面之形成已經證明是非常困難的。常用的技術是,利用離子植入設備將摻雜物原子植入至基板中。利用離子植入,高能摻雜物原子以高速撞擊基板表面並且被驅入基板中。雖然此方法對於具有中等深度接面之摻雜區域之形成已經證明是有效的,但利用離子植入以形成超淺接面是非常困難的。在形成淺植入接面所需之低能量下,基板內之能量化的摻雜物原子之路徑及植入均勻
度均是難以控制的。能量化的摻雜物原子之植入對基板中之晶格造成損害,其是難以修復的。由晶格損害所造成之錯位可能輕易地刺穿淺接面,造成穿過接面之漏電流。此外,p型摻雜物(例如硼,其快速地在矽中擴散)之植入,在被引入至基板中之後,造成摻雜物原子之過度分散。於是,在基板之特定區域中(特別是在基板表面處)形成高局限濃度的p型摻雜物原子變得困難。
此外,電晶體及記憶體裝置之新元件結構正被實施,其使用摻雜的三維結構。此類元件之例子包括,但不限於,鰭式場效電晶體(FinFET)、三閘極場效電晶體、凹陷通道電晶體(RCAT)、及嵌入式動態隨機存取記憶體(EDRAM)溝槽。為了均勻地摻雜這些結構,希望擁有保形的(conformal)摻雜方法。離子植入製程實際上是直線對傳的(line of site),因此需要特別的基板定向,以均勻地摻雜鰭式及溝槽式結構。此外,在高元件密度下,遮蔽效應使得利用離子植入技術進行鰭式結構的均勻摻雜變得非常困難、或甚至不可能。習知的電漿摻雜及原子層摻雜是已經展現三維半導體結構之保形摻雜之技術,但其每一者受限於在理想條件下可以使用之摻雜物密度及深度之範圍。本發明之實施例提出用於形成超淺摻雜區域之方法,其克服了數個上述的問題。
描述用於超淺硼摻雜物區域形成之複數實施例,其係藉由固相擴散從硼摻雜物層進入基板層之中。摻雜物區域可形成在平面基板中、在基板上之凸出特徵部中、或在基板中之凹陷特徵部中。
根據一實施例,提出在基板中形成超淺硼(B)摻雜物區域之方法。該方法包括利用原子層沉積(ALD)沉積硼摻雜物層與基板直接接觸,該硼摻雜物層包含藉由硼胺前驅物或有機硼前驅物及反應物氣體之交替氣體暴露所形成之氧化物、氮化物或氮氧化物。該方法更包括圖案化該硼摻雜物層、及藉由熱處理使硼從經圖案化的硼摻雜物層擴散至基板中,以在基板中形成超淺硼摻
雜物區域。
根據某些實施例,提出在基板之凸出特徵部或凹陷特徵部中形成超淺硼(B)摻雜物區域之方法。
根據另一實施例,提出在基板中形成超淺硼(B)摻雜物區域之方法。該方法包括利用原子層沉積(ALD)沉積硼摻雜物層與基板直接接觸,該硼摻雜物層具有4 nm或更小之厚度,並且包含藉由硼胺前驅物或有機硼前驅物及反應物氣體之交替氣體暴露所形成之氧化物、氮化物或氮氧化物;及在經圖案化的硼摻雜物層上沉積頂蓋層。該方法更包括圖案化該硼摻雜物層及該頂蓋層;藉由熱處理使硼從經圖案化的硼摻雜物層擴散至基板中,以在基板中形成超淺硼摻雜物區域;及從基板移除經圖案化的硼摻雜物層及經圖案化的頂蓋層。
在數個實施例中揭示在半導體元件中形成超淺摻雜物區域之方法,其係藉由固相擴散從摻雜物層進入基板層之中。摻雜物區域可包括,例如,平面電晶體、FinFET、或三閘極場效電晶體之超淺源極-汲極延伸。超淺摻雜物區域形成之其它應用可包括通道摻雜代替閘極製程流程、及用於FinFET、或極薄絕緣層上矽(ET-SOI)元件。具有極薄替代半導體通道之元件也可使用所揭示的方法加以摻雜,例如絕緣層上鍺元件(GeOI)或Ge FinFET及III-V族通道元件,例如GaAs、InGaAs、或InGaSb FinFET。此外,形成在非晶Si或多晶Si層中之元件,例如EDRAM元件,可使用所揭示的方法以調整Si摻雜程度。
熟悉此相關領域者將了解,各種實施例可在缺少一或多個特定細節、或使用其它替代物及/或額外方法、材料或構件之情況下加以實施。在其它例子中,熟知的結構、材料或操作並未詳細地顯示或描述,以避免模糊了本發明各種實施例之樣態。類似地,為解釋之目的,特定的數目、材料或組態被提出,以提供對於本發明之徹底了解。此外,應當了解,在圖式中所示之各種實
施例係例示性的表示,不必然按照比例繪製。
在整個說明書中之「一實施例」表示,與該實施例有關的特定特徵、結構、材料或特性係包含在本發明之至少一實施例中,但不表示其出現在每一實施例中。因此,在整個說明書之各個地方出現之詞組「在一實施例中」,並不必然涉及本發明之相同實施例。
圖1A至1E顯示,根據本發明之實施例,在基板中形成超淺摻雜物區域之製程流程之概要橫剖面圖。圖1A顯示基板100之概要橫剖面圖。基板100可以是任何尺寸,例如200 mm基板、300 mm基板、或甚至更大的基板。根據一實施例,基板100可包含Si,例如結晶Si、多晶Si、或非晶Si。在一例子中,基板100可以是拉伸應變Si層。根據另一實施例,基板100可包含Ge或SixGe1-x化合物,其中x是Si的原子分率,1-x是Ge的原子分率,且0<x<1。例示性的SixGe1-x化合物包括Si0.1Ge0.9、Si0.2Ge0.8、Si0.3Ge0.7、Si0.4Ge0.6、Si0.5Ge0.5、Si0.6Ge0.4、Si0.7Ge0.3、Si0.8Ge0.2、及Si0.9Ge0.1。在一例子中,基板100可以是沉積在鬆弛Si0.5Ge0.5緩衝層上之拉伸應變SixGe1-x(x>0.5)或壓縮應變Ge層。根據某些實施例,基板100可包括絕緣層上矽(SOI)。
圖1B顯示可利用原子層沉積(ALD)加以沉積並且與基板100直接接觸之摻雜物層102、及隨後可沉積在摻雜物層102上之頂蓋層104。在某些例子中,頂蓋層104可能在圖1B至1D之膜結構中被省略。摻雜物層102可包括氧化物層(例如SiO2)、氮化物層(例如SiN)、或氮氧化物層(例如SiON)、或其兩者以上之組合。摻雜物層102可包括一或多個摻雜物,其來自元素週期表之:IIIA族的硼(B)、鋁(Al)、鎵(Ga)、銦(In)及鉈(Tl);及VA族的氮(N)、磷(P)、砷(As)、銻(Sb)及鉍(Bi)。根據某些實施例,摻雜物層102可包括低摻雜物程度,例如在約0.5至約5原子百分率摻雜物。根據其它實施例,摻雜物層102可包括中摻雜物程度,例如在約5至約20原子百分率摻雜物。再根據其它實施例,摻雜物層可包括高摻雜物程度,例如大於20原子百
分率摻雜物。在某些例子中,摻雜物層102之厚度可能是4奈米(nm)或更小,例如在1 nm至4 nm之間、在2 nm至4 nm之間、或在3 nm至4 nm之間。然而,可使用其它厚度。
根據其它實施例,摻雜物層102可包括氧化物層、氮化物層、或氮氧化物層形式之摻雜高介電常數介電材料,或由其所組成。在高介電常數介電材料中之摻雜物可選自於上述所列舉的摻雜物。高介電常數介電材料可包括一或多個金屬元素,選自於鹼土元素、稀土元素、元素週期表之IIIA族、IVA族、及IVB族元素。鹼土金屬元素包括鈹(Be)、鎂(Mg)、鈣(Ca)、鍶(Sr)及鋇(Ba)。例示性的氧化物包括氧化鎂、氧化鈣、氧化鋇、及其組合。稀土金屬元素可選自於下列群組:鈧(Sc)、釔(Y)、鎦(Lu)、鑭(La)、鈰(Ce)、鐠(Pr)、釹(Nd)、釤(Sm)、銪(Eu)、釓(Gd)、鋱(Tb)、鏑(Dy)、鈥(Ho)、鉺(Er)、銩(Tm)、及鐿(Yb)。IVB族元素包括鈦(Ti)、鉿(Hf)、及鋯(Zr)。根據本發明之某些實施例,高介電常數介電材料可包括HfO2、HfON、HfSiON、ZrO2、ZrON、ZrSiON、TiO2、TiON、Al2O3、La2O3、W2O3、CeO2、Y2O3、或Ta2O5、或其兩者以上之組合。然而,其它介電材料被考慮且可以被使用。可使用在高介電常數介電材料之ALD中之前驅物氣體係描述在美國專利第7,772,073號之中,其全部內容係合併於此做為參考資料。
頂蓋層104可能是氧化物層、氮化物層、或氮氧化物層,並且可包括Si及/或上述之高介電常數介電材料之一或多者。頂蓋層104可利用,例如,化學氣相沉積(CVD)或ALD加以沉積。在某些例子中,頂蓋層104之厚度可能在1 nm至100 nm之間、在2 nm至50 nm之間、或在2 nm至20 nm之間。
根據本發明之實施例,圖1B所示之膜結構可被圖案化,以形成經圖案化的膜結構,其概要地顯示在圖1C中。例如,可使用習知的光微影圖案化及蝕刻方法,以形成經圖案化的摻雜物層106及經圖案化的頂蓋層108。
然後,圖1C中之經圖案化的膜結構可以被熱處理,以使摻
雜物110(例如B、Al、Ga、In、Tl、N、P、As、Sb、或Bi)從經圖案化的摻雜物層106擴散至基板100中,並且在經圖案化的摻雜物層106之下形成超淺摻雜物區域112於基板100中(圖1D)。熱處理可包括在惰性氛圍(例如,氬(Ar)、或氮氣(N2))或在氧化氛圍(例如氧氣(O2)或水(H2O))下將基板100加熱至介於100℃及1000℃之間的溫度10秒至10分鐘。某些熱處理例子包括基板溫度在100℃至500℃之間、在200℃至500℃之間、在300℃至500℃之間、及在400℃至500℃之間。其它例子包括基板溫度在500℃及1000℃之間、在600℃至1000℃之間、在700℃至1000℃之間、在800℃至1000℃之間、及在900℃至1000℃之間。在某些例子中,熱處理可包括快速熱退火(RTA)、尖波退火、或雷射尖波退火。
在某些例子中,超淺摻雜物區域112之厚度可能在1 nm至10 nm之間、或在2 nm及5 nm之間。然而,熟悉此項技術者將輕易得知,在基板100中之超淺摻雜物區域112之下邊界可能不是遽變的,而是具有摻雜物濃度逐漸減少之特性。
在熱處理及超淺摻雜物區域112之形成後,可使用乾式蝕刻製程或溼式蝕刻製程以移除經圖案化的摻雜物層106及經圖案化的頂蓋層108。產生的結構係描繪在圖1E中。此外,在熱處理之後,可實施乾式或溼式清潔製程,以從基板100移除任何蝕刻殘留物。
根據本發明之另一實施例,在基板100上沉積摻雜物層102之後,摻雜物層102可被圖案化以形成經圖案化的摻雜物層106,之後,可將頂蓋層保形地沉積在經圖案化的摻雜物層106上。接著,可進一步處理該膜結構,如圖1D至1E所示,以形成超淺摻雜物區域112於基板100中。
圖6A顯示凸出特徵部601之概要橫剖面圖,本發明之實施例可被應用於此。例示性的凸出特徵部601係形成在基板600上。基板600及凸出特徵部601之材料可包括圖1A之基板100之上述材料之一或多者。在一例子中,基板600及凸出特徵部601可包
含相同的材料(例如Si)或由相同的材料所組成。熟悉此項技術者將輕易得知,本發明之實施例可應用於基板上之其它簡單或複雜的凸出特徵部。
圖6B顯示沉積在圖6A之凸出特徵部601上之保形摻雜物層602之概要橫剖面圖。保形摻雜物層602之材料可包括圖1B之摻雜物層102之上述材料之一或多者。隨後,類似於圖1C至1E所述之膜結構,圖6B之膜結構可被處理,包括,例如,沉積頂蓋層(未顯示)在摻雜物層602上,圖案化摻雜物層602(未顯示)及頂蓋層(未顯示)如所需,熱處理經圖案化的摻雜物層(未顯示)以使摻雜物從經圖案化的摻雜物層(未顯示)擴散至基板600中及/或至凸出特徵部601中,及移除經圖案化的摻雜物層(未顯示)及經圖案化的頂蓋層(未顯示)。
圖7A顯示凹陷特徵部701之概要橫剖面圖,本發明之實施例可被應用於此。例示性的凹陷特徵部701係形成在基板700中。基板700之材料可包括圖1A之基板100之上述材料之一或多者。在一例子中,基板700可包含Si或由Si所組成。熟悉此項技術者將輕易得知,本發明之實施例可應用於基板上之其它簡單或複雜的凹陷特徵部。
圖7B顯示沉積在圖7A之凹陷特徵部701中之保形摻雜物層702之概要橫剖面圖。保形摻雜物層702之材料可包括圖1B之摻雜物層102之上述材料之一或多者。隨後,類似於圖1C至1E所述之膜結構,圖7B之膜結構可被處理,包括,例如,沉積頂蓋層(未顯示)在摻雜物層702上,圖案化摻雜物層702(未顯示)及頂蓋層(未顯示)如所需,熱處理經圖案化的摻雜物層(未顯示)以使摻雜物從經圖案化的摻雜物層(未顯示)擴散至凹陷特徵部701之基板700中,及移除經圖案化的摻雜物層(未顯示)及經圖案化的頂蓋層(未顯示)。
圖2A至2E顯示,根據本發明之另一實施例,在基板中形成超淺摻雜物區域之製程流程之概要橫剖面圖。在圖1A至1E所述之材料(例如,基板、摻雜物層、摻雜物、及頂蓋層組成)、處
理條件(例如沉積方法及熱處理條件)、及層厚度之一或多者可輕易地被使用在圖2A至2E所圖示之實施例中。
圖2A顯示基板200之概要橫剖面圖。圖2B顯示在基板200上形成之經圖案化的遮罩層202,以在基板200上定義在經圖案化的遮罩層202中之摻雜物窗(井)203。經圖案化的遮罩層202可能是,例如,氮化物硬遮罩(例如SiN硬遮罩),其可使用習知的光微影圖案化及蝕刻方法加以形成。
圖2C顯示由ALD所沉積之摻雜物層204,其在摻雜物窗203中與基板200直接接觸,並且在經圖案化的遮罩層202上,且頂蓋層206被沉積在摻雜物層204上。摻雜物層204可包含n型摻雜物或p型摻雜物。在某些實施例中,頂蓋層206可從圖2C至2D之膜結構中被省略。
然後,圖2C中之膜結構可以被熱處理,以使摻雜物208從摻雜物層204擴散至基板200中,並且在摻雜物窗203中之摻雜物層204之下形成超淺摻雜物區域210於基板200中(圖2D)。在某些例子中,超淺摻雜物區域210之厚度可能在1 nm至10 nm之間、或在2 nm及5 nm之間。然而,熟悉此項技術者將輕易得知,在基板200中之超淺摻雜物區域210之下邊界可能不是遽變的,而是具有摻雜物濃度逐漸減少之特性。
在熱處理及超淺摻雜物區域210之形成後,可使用乾式蝕刻製程或溼式蝕刻製程以移除經圖案化的遮罩層202、摻雜物層204、及頂蓋層206(圖2E)。此外,在熱處理之後,可實施乾式或溼式清潔製程,以從基板200移除任何蝕刻殘留物。
圖3A至3D顯示,根據本發明之又另一實施例,在基板中形成超淺摻雜物區域之製程流程之概要橫剖面圖。圖3A至3D所示之製程流程可,例如,包括在平面SOI、FinFET、或ET SOI中之通道摻雜。此外,該製程流程可被應用於形成自對準超淺源極/汲極延伸。在圖1A至1E所述之材料(例如,基板、摻雜物層、摻雜物、及頂蓋層組成)、處理條件(例如沉積方法及熱處理條件)、及層厚度之一或多者可輕易地被使用在圖3A至3D所圖示
之實施例中。
圖3A顯示類似於圖1C之膜結構之概要橫剖面圖,並且包括與基板300直接接觸之經圖案化的第一摻雜物層302、及在該經圖案化的第一摻雜物層302上之經圖案化的頂蓋層304。經圖案化的第一摻雜物層302可包含n型摻雜物或p型摻雜物。
圖3B顯示第二摻雜物層306及第二頂蓋層308,第二摻雜物層306可保形地沉積在經圖案化的頂蓋層304上、並且鄰接於經圖案化的第一摻雜物層302直接在基板300上,第二頂蓋層308係沉積在第二摻雜物層306上。在某些例子中,第二頂蓋層308可從圖3B至3C之膜結構中被省略。第二摻雜物層306可包含n型摻雜物或p型摻雜物,附帶條件為第二摻雜物層306不包含與經圖案化的第一摻雜物層302相同的摻雜物,且經圖案化的第一摻雜物層302及第二摻雜物層306之中只有一者包含p型摻雜物,經圖案化的第一摻雜物層302及第二摻雜物層306之中只有一者包含n型摻雜物。
然後,圖3B中之膜結構可以被熱處理,以使第一摻雜物310從經圖案化的第一摻雜物層302擴散至基板300中,以在經圖案化的第一摻雜物層302之下形成第一超淺摻雜物區域312於基板300中。此外,熱處理使第二摻雜物314從第二摻雜物層306擴散至基板300中,以在第二摻雜物層306下之基板300中形成第二超淺摻雜物區域316(圖3C)。
在熱處理之後,可使用乾式蝕刻製程或溼式蝕刻製程以移除經圖案化的第一摻雜物層302、經圖案化的頂蓋層304、第二摻雜物層306、及第二頂蓋層308(圖3D)。此外,在熱處理之後,可實施清潔製程,以從基板300移除任何蝕刻殘留物。
圖4A至4F顯示,根據本發明之再另一實施例,在基板中形成超淺摻雜物區域之製程流程之概要橫剖面圖。圖4A至4E所示之製程流程可,例如,被應用在用於形成具有自對準源極/汲極延伸之閘極最終虛擬電晶體之製程。在圖1A至1F所述之材料(例如,基板、摻雜物層、摻雜物、及頂蓋層組成)、處理條件(例
如沉積方法及熱處理條件)、及層厚度之一或多者可輕易地被使用在圖4A至4F所圖示之實施例中。
圖4A顯示膜結構之概要橫剖面圖,該膜結構包括在基板400上之經圖案化的第一摻雜物層402、在經圖案化的第一摻雜物層402上之經圖案化的頂蓋層404、及在經圖案化的頂蓋層404上之經圖案化的虛擬閘極電極層406(例如,多晶矽)。經圖案化的第一摻雜物層402可包含n型摻雜物或p型摻雜物。在某些例子中,經圖案化的頂蓋層404可從圖4A至4E之膜結構中被省略。
圖4B概要地顯示緊靠著經圖案化的虛擬閘極電極層406、經圖案化的頂蓋層404、及經圖案化的第一摻雜物層402之第一側壁間隔物層408。第一側壁間隔物層408可包含氧化物(例如SiO2)或氮化物(例如SiN),並且可利用沉積保形層在圖4A之膜結構上及非等向性蝕刻該保形層而加以形成。
圖4C顯示第二摻雜物層410,其可保形地沉積在圖4B所示的膜結構上,包括鄰接於第一側壁間隔物層408與基板400直接接觸。此外,第二頂蓋層420係保形地沉積在第二摻雜物層410上。第二摻雜物層410可包含n型摻雜物或p型摻雜物,附帶條件為第二摻雜物層410不包含與經圖案化的第一摻雜物層402相同的摻雜物,且經圖案化的第一摻雜物層402及第二摻雜物層410之中只有一者包含p型摻雜物,經圖案化的第一摻雜物層402及第二摻雜物層410之中只有一者包含n型摻雜物。在某些例子中,第二頂蓋層420可從圖4C至4D之膜結構中被省略。
然後,圖4C中之膜結構可以被熱處理,以使第一摻雜物412從經圖案化的第一摻雜物層402擴散至基板400中,並且在經圖案化的第一摻雜物層402下之基板400中形成第一超淺摻雜物區域414。此外,熱處理使第二摻雜物416從第二摻雜物層410擴散至基板400中,以在第二摻雜物層410下之基板400中形成第二超淺摻雜物區域418。
在熱處理之後,可使用乾式蝕刻製程或溼式蝕刻製程以移除第二摻雜物層410及第二頂蓋層420,以形成圖4E所概要顯示
的膜結構。此外,在熱處理之後,可實施清潔製程,以從基板400移除任何蝕刻殘留物。
接著,可形成緊靠著第一側壁間隔物層408之第二側壁間隔物層422。其係概要地顯示在圖4F中。第二側壁間隔物層422可包含氧化物(例如SiO2)或氮化物(例如SiN),並且可利用沉積保形層在膜結構上及非等向性蝕刻該保形層而加以形成。
然後,可進一步處理圖4F所示之膜結構。此進一步處理可包括形成額外的源極/汲極延伸或實施包括離子植入、襯墊沉積等之替代閘極製程流程。
圖5A至5E顯示,根據本發明之另一實施例,在基板中形成超淺摻雜物區域之製程流程之概要橫剖面圖。圖5A至5E所示之製程流程可,例如,被應用在用於形成能帶間穿隧電晶體之由間隔物所界定的P-i-N接面之製程。在圖1A至1E所述之材料(例如,基板、摻雜物層、摻雜物、及頂蓋層組成)、處理條件(例如沉積方法及熱處理條件)、及層厚度之一或多者可輕易地被使用在圖5A至5E所圖示之實施例中。
圖5A顯示膜結構之概要橫剖面圖,該膜結構包括在基板500上之經圖案化層502(例如氧化物、氮化物、或氮氧化物層)、在經圖案化層502上之經圖案化的頂蓋層504(例如,多晶矽)。圖5A更顯示緊靠著基板500、經圖案化的頂蓋層504、及經圖案化層502之側壁間隔物層506。側壁間隔物層506可包含氧化物(例如SiO2)或氮化物(例如SiN),並且可利用沉積保形層及非等向性蝕刻該保形層而加以形成。
圖5B顯示第一摻雜物層508及第一頂蓋層510之概要橫剖面圖,包含第一摻雜物之第一摻雜物層508由ALD所沉積、鄰接於側壁間隔物層506與基板500直接接觸,第一頂蓋層510(例如,氧化物層)係沉積在第一摻雜物層508上。產生的膜結構可被平坦化(例如,利用化學機械研磨,CMP)以形成圖5B所示的膜結構。
然後,可使用乾式蝕刻製程或溼式蝕刻製程以移除經圖案
化層502及經圖案化的頂蓋層504。接著,可沉積包含第二摻雜物之第二摻雜物層512與基板500直接接觸,及沉積第二頂蓋層514(例如,氧化物層)在第二摻雜物層512上。產生的膜結構可被平坦化(例如,利用CMP)以形成圖5C所示之經平坦化的膜結構。第一摻雜物層508及第二摻雜物層512可包含n型摻雜物或p型摻雜物,附帶條件為第一摻雜物層508及第二摻雜物層512不包含相同的摻雜物,且第一摻雜物層508及第二摻雜物層512之中只有一者包含p型摻雜物,第一摻雜物層508及第二摻雜物層512之中只有一者包含n型摻雜物。
然後,圖5C中之膜結構可以被熱處理,以使第一摻雜物516從第一摻雜物層508擴散至基板500中,並且在第一摻雜物層508下之基板500中形成第一超淺摻雜物區域518。此外,熱處理使第二摻雜物520從第二摻雜物層512擴散至基板500中,以在第二摻雜物層512下之基板500中形成第二超淺摻雜物區域522(圖5D)。圖5E顯示在基板500中、由間隔物所界定的第一及第二超淺摻雜物區域518及522。
在此,將根據本發明之數個實施例描述用於在基板上沉積摻雜物層之範例方法。
根據一實施例,硼摻雜物層可包括硼氧化物、硼氮化物、或硼氮氧化物。根據其它實施例,硼摻雜物層可包括氧化物層、氮化物層或氮氧化物層之形式之硼摻雜高介電常數材料,或由其所組成。在一例子中,可藉由ALD以沉積硼氧化物摻雜層,其係藉由:a)提供一基板在用於實施ALD製程之處理腔室中,b)使基板暴露至氣相硼胺或有機硼前驅物,c)將處理腔室沖淨/抽真空,d)使基板暴露至包含H2O、O2、或O3、或其組合之反應物氣體,e)將處理腔室沖淨/抽真空,及f)重複步驟b)至e)若干次數,直至硼氧化物摻雜物層具有所需的厚度。根據其它實施例,可以在步驟d)中使用包含NH3之反應物氣體以沉積硼氮化物摻雜物層、或可以在步驟d)中使用包含1)H2O、O2、或O3、及NH3、或2)NO、NO2、或N2O、及選擇性的H2O、O2、O3、及NH3之
一或多者之反應物氣體以沉積硼氮氧化物摻雜物層。
根據本發明之實施例,硼胺可包括LnB(NR1R2)3形式之硼化合物,其中L是中性的路易士鹼,n是0或1,R1及R2每一者可選自於烷基、芳基、氟烷基、氟芳基、烷氧烷基、及胺烷基(aminoalkyl)。硼胺之例子包括B(NMe2)3、(Me3)B(NMe2)3及B[N(CF3)2]3。根據本發明之實施例,有機硼可包括LnBR1R2R3形式之硼化合物,其中L是中性的路易士鹼,n是0或1,R1、R2及R3每一者可選自於烷基、芳基、氟烷基、氟芳基、烷氧烷基、及胺烷基。硼胺之例子包括BMe3、(Me3N)BMe3、B(CF3)3及(Me3N)B(C6F3)。
根據一實施例,砷摻雜物層可包括砷氧化物、砷氮化物、或砷氮氧化物。根據其它實施例,砷摻雜物層可包括氧化物層、氮化物層或氮氧化物層之形式之砷摻雜高介電常數材料,或由其所組成。在一例子中,可藉由ALD以沉積砷氧化物摻雜物層,其係藉由:a)提供一基板在用於實施ALD製程之處理腔室中,b)使基板暴露至氣相的含砷前驅物,c)將處理腔室沖淨/抽真空,d)使基板暴露至H2O、O2、或O3、或其組合,e)將處理腔室沖淨/抽真空,及f)重複步驟b)至e)若干次數,直至砷氧化物摻雜物層具有所需的厚度。根據其它實施例,可以在步驟d)中使用NH3以沉積砷氮化物摻雜物層、或在步驟d)中使用1)H2O、O2、或O3、及NH3、或2)NO、NO2、或N2O、及選擇性的H2O、O2、O3、及NH3之一或多者以沉積砷氮氧化物摻雜物層。根據本發明之某些實施例,氣相的含砷前驅物可包括砷鹵化物,例如AsCl3、AsBr3、或AsI3。
根據一實施例,磷摻雜物層可包括磷氧化物、磷氮化物、或磷氮氧化物。根據其它實施例,磷摻雜物層可包括氧化物層、氮化物層或氮氧化物層之形式之磷摻雜高介電常數材料,或由其所組成。在一例子中,可藉由ALD以沉積磷氧化物摻雜物層,其係藉由:a)提供一基板在用於實施ALD製程之處理腔室中,b)使基板暴露至氣相的含磷前驅物,c)將處理腔室沖淨/抽真空,d)
使基板暴露至包含H2O、O2、或O3、或其組合之反應物氣體,e)將處理腔室沖淨/抽真空,及f)重複步驟b)至e)若干次數,直至磷氧化物摻雜物層具有所需的厚度。根據其它實施例,可以在步驟d)中使用包含NH3之反應物氣體以沉積磷氮化物摻雜物層、或在步驟d)中使用包含1)H2O、O2、或O3、及NH3、或2)NO、NO2、或N2O、及選擇性的H2O、O2、O3、及NH3之一或多者之反應物氣體以沉積磷氮氧化物摻雜物層。根據本發明之某些實施例,氣相的含磷前驅物可包括[(CH3)2N]3PO、P(CH3)3、PH3、OP(C6H5)3、OPCl3、PCl3、PBr3、[(CH3)2N]3P、P(C4H9)3。
已經描述藉由來自摻雜物層之固相擴散進入基板、以形成超淺摻雜物區域之複數實施例。為了說明及描述之目的,本發明之實施例之上述說明已經被提出。不打算是詳盡的或將本發明限定於所揭露的精確形式。此發明說明及下述的申請專利範圍包括僅用於記述之目的、而不應被解釋為限制之用語。例如,本文(包括申請專利範圍)中所使用之用語「在...上」不需要「在基板上」之一膜是直接在該基板上並且直接與該基板接觸;可能有第二膜或其它結構在該膜與該基板之間。
熟悉此相關技藝者可了解,根據上述教示,許多修改及變化是可能的。對於圖式中所顯示之各種組成,熟悉此項技藝者將認識各種等效的結合及替代。因此,本發明之範圍不應被限定於此發明說明,而應被隨附之申請專利範圍所界定。
100‧‧‧基板
102‧‧‧摻雜物層
104‧‧‧頂蓋層
106‧‧‧經圖案化的摻雜物層
108‧‧‧經圖案化的頂蓋層
110‧‧‧摻雜物
112‧‧‧超淺摻雜物區域
200‧‧‧基板
202‧‧‧遮罩層
203‧‧‧摻雜物窗(井)
204‧‧‧摻雜物層
206‧‧‧頂蓋層
208‧‧‧摻雜物
210‧‧‧超淺摻雜物區域
300‧‧‧基板
302‧‧‧第一摻雜物層
304‧‧‧頂蓋層
306‧‧‧第二摻雜物層
308‧‧‧第二頂蓋層
310‧‧‧第一摻雜物
312‧‧‧第一超淺摻雜物區域
314‧‧‧第二摻雜物
316‧‧‧第二超淺摻雜物區域
400‧‧‧基板
402‧‧‧第一摻雜物層
404‧‧‧頂蓋層
406‧‧‧虛擬閘極電極層
408‧‧‧第一側壁間隔物層
410‧‧‧第二摻雜物層
412‧‧‧第一摻雜物
414‧‧‧第一超淺摻雜物區域
416‧‧‧第二摻雜物
418‧‧‧第二超淺摻雜物區域
420‧‧‧第二頂蓋層
422‧‧‧第二側壁間隔物層
500‧‧‧基板
502‧‧‧經圖案化層
504‧‧‧經圖案化的頂蓋層
506‧‧‧側壁間隔物層
508‧‧‧第一摻雜物層
510‧‧‧第一頂蓋層
512‧‧‧第二摻雜物層
514‧‧‧第二頂蓋層
516‧‧‧第一摻雜物
518‧‧‧第一超淺摻雜物區域
520‧‧‧第二摻雜物
522‧‧‧第二超淺摻雜物區域
600‧‧‧基板
601‧‧‧凸出特徵部
602‧‧‧摻雜物層
700‧‧‧基板
701‧‧‧凹陷特徵部
702‧‧‧摻雜物層
在隨附的圖式中:
圖1A至1E顯示,根據本發明之實施例,在基板中形成超淺摻雜物區域之製程流程之概要橫剖面圖。
圖2A至2E顯示,根據本發明之另一實施例,在基板中形成超淺摻雜物區域之製程流程之概要橫剖面圖。
圖3A至3D顯示,根據本發明之又另一實施例,在基板中形成超淺摻雜物區域之製程流程之概要橫剖面圖。
圖4A至4F顯示,根據本發明之再另一實施例,在基板中形成超淺摻雜物區域之製程流程之概要橫剖面圖。
圖5A至5E顯示,根據本發明之另一實施例,在基板中形成超淺摻雜物區域之製程流程之概要橫剖面圖。
圖6A顯示凸出特徵部之概要橫剖面圖,本發明之實施例可被應用於此。
圖6B顯示沉積在圖6A之凸出特徵部上之保形摻雜物層之概要橫剖面圖。
圖7A顯示凹陷特徵部之概要橫剖面圖,本發明之實施例可被應用於此。
圖7B顯示沉積在圖7A之凹陷特徵部中之保形摻雜物層之概要橫剖面圖。
100‧‧‧基板
102‧‧‧摻雜物層
104‧‧‧頂蓋層
106‧‧‧經圖案化的摻雜物層
108‧‧‧經圖案化的頂蓋層
110‧‧‧摻雜物
112‧‧‧超淺摻雜物區域
Claims (20)
- 一種在基板中形成超淺硼摻雜物區域之方法,該方法包括:利用原子層沉積(ALD)沉積一硼摻雜物層與該基板直接接觸,該硼摻雜物層包含藉由硼胺前驅物或有機硼前驅物及反應物氣體之交替氣體暴露所形成之氧化物、氮化物、或氮氧化物;圖案化該硼摻雜物層;及藉由熱處理使硼從該經圖案化的硼摻雜物層擴散至該基板中,在該基板中形成該超淺硼摻雜物區域。
- 如申請專利範圍第1項之在基板上形成超淺硼摻雜物區域之方法,更包括:由該基板移除該經圖案化的硼摻雜物層。
- 如申請專利範圍第1項之在基板上形成超淺硼摻雜物區域之方法,更包括:沉積一頂蓋層在該硼摻雜物層上或在該經圖案化的硼摻雜物層上。
- 如申請專利範圍第1項之在基板上形成超淺硼摻雜物區域之方法,其中該硼摻雜物層包含氧化物,該反應物氣體包括H2O、O2、或O3、或其兩者以上之組合。
- 如申請專利範圍第1項之在基板上形成超淺硼摻雜物區域之方法,其中該硼摻雜物層包含氮化物,該反應物氣體包括NH3。
- 如申請專利範圍第1項之在基板上形成超淺硼摻雜物區域之方法,其中該硼摻雜物層包含氮氧化物,該反應物氣體包括a)H2O、O2、或O3、及NH3、或b)NO、NO2、或N2O、及選擇性的H2O、O2、O3、及NH3之一或多者。
- 如申請專利範圍第1項之在基板上形成超淺硼摻雜物區域之方法,其中該硼摻雜物層之厚度係4 nm或更小。
- 如申請專利範圍第1項之在基板上形成超淺硼摻雜物區域之方法,其中該基板包括一經圖案化的遮罩層,該經圖案化的遮罩層在該基板上定義一摻雜物窗,其中該硼摻雜物層係沉積在該摻雜物窗中與該基板直接接觸。
- 如申請專利範圍第1項之在基板上形成超淺硼摻雜物區域之方法,其中該基板包括Si、Ge、In、Ga、As、Sb、GaAs、InGaAs、InGaSb、或SixGe1-x,其中0<x<1。
- 一種在基板中形成超淺硼摻雜物區域之方法,該方法包括:利用原子層沉積(ALD)沉積一硼摻雜物層與該基板直接接觸,該硼摻雜物層之厚度係4 nm或更小,該硼摻雜物層包含藉由硼胺前驅物或有機硼前驅物及反應物氣體之交替氣體暴露所形成之氧化物、氮化物、或氮氧化物;沉積一頂蓋層在該經圖案化的硼摻雜物層上;圖案化該硼摻雜物層及該頂蓋層;藉由熱處理使硼從該經圖案化的硼摻雜物層擴散至該基板中,在該基板中形成該超淺硼摻雜物區域;及由該基板移除該經圖案化的硼摻雜物層及該經圖案化的頂蓋層。
- 如申請專利範圍第10項之在基板中形成超淺硼摻雜物區域之方法,其中該硼摻雜物層包含氧化物,該反應物氣體包括H2O、O2、或O3、或其兩者以上之組合。
- 如申請專利範圍第10項之在基板中形成超淺硼摻雜物區域之方法,其中該硼摻雜物層包含氮化物,該反應物氣體包括NH3。
- 如申請專利範圍第10項之在基板中形成超淺硼摻雜物區域之方法,其中該硼摻雜物層包含氮氧化物,該反應物氣體包括a)H2O、O2、或O3、及NH3、或b)NO、NO2、或N2O、及選擇性的H2O、O2、O3、及NH3之一或多者。
- 如申請專利範圍第10項之在基板中形成超淺硼摻雜物區域之方法,其中該基板包括一經圖案化的遮罩層,該經圖案化的遮罩層在該基板上定義一摻雜物窗,該硼摻雜物層係沉積在該摻雜物窗中與該基板直接接觸。
- 一種形成超淺硼摻雜物區域之方法,該方法包括:提供包含凸出特徵部或凹陷特徵部之一基板;保形地沉積一硼摻雜物層與該凸出特徵部或與該凹陷特徵部之內部直接接觸;圖案化該硼摻雜物層;及藉由熱處理使硼從該經圖案化的硼摻雜物層擴散至該凸出特徵部中或至該凹陷特徵部中之該基板中,在該凸出特徵部或該凹陷特徵部中形成該超淺硼摻雜物區域。
- 如申請專利範圍第15項之形成超淺硼摻雜物區域之方法,其中該硼摻雜物層包含藉由使用硼胺前驅物或有機硼前驅物及反應物氣體之交替氣體暴露之原子層沉積(ALD)所沉積之氧化物、氮化物、或氮氧化物。
- 如申請專利範圍第15項之形成超淺硼摻雜物區域之方法,更包括:由該基板移除該經圖案化的硼摻雜物層。
- 如申請專利範圍第15項之形成超淺硼摻雜物區域之方法,其 中該硼摻雜物層包含氧化物,該反應物氣體包括H2O、O2、或O3、或其兩者以上之組合。
- 如申請專利範圍第15項之形成超淺硼摻雜物區域之方法,其中該硼摻雜物層包含氮化物,該反應物氣體包括NH3。
- 如申請專利範圍第15項之形成超淺硼摻雜物區域之方法,其中該硼摻雜物層包含氮氧化物,該反應物氣體包括a)H2O、O2、或O3、及NH3、或b)NO、NO2、或N2O、及選擇性的H2O、O2、O3、及NH3之一或多者。
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2011
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- 2013-11-12 US US14/078,247 patent/US9012316B2/en active Active
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US9899224B2 (en) | 2015-03-03 | 2018-02-20 | Tokyo Electron Limited | Method of controlling solid phase diffusion of boron dopants to form ultra-shallow doping regions |
TWI631603B (zh) * | 2015-03-03 | 2018-08-01 | 東京威力科創股份有限公司 | 控制硼摻質之固相擴散以形成超淺摻雜區域的方法 |
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US20150072510A1 (en) | 2015-03-12 |
US8580664B2 (en) | 2013-11-12 |
US20120252197A1 (en) | 2012-10-04 |
US20140073122A1 (en) | 2014-03-13 |
TWI533357B (zh) | 2016-05-11 |
US9012316B2 (en) | 2015-04-21 |
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