TW201307187A - 薄膜電晶體 - Google Patents

薄膜電晶體 Download PDF

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TW201307187A
TW201307187A TW101121259A TW101121259A TW201307187A TW 201307187 A TW201307187 A TW 201307187A TW 101121259 A TW101121259 A TW 101121259A TW 101121259 A TW101121259 A TW 101121259A TW 201307187 A TW201307187 A TW 201307187A
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Taiwan
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channel layer
thin film
film transistor
self
oxide semiconductor
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TW101121259A
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Edsger Smits
Harmannus Franciscus Maria Schoo
Ashutosh Tripathi
Gerwin Hermanus Gelinck
Der Putten Bas Van
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Tno
Imec
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Publication of TW201307187A publication Critical patent/TW201307187A/zh

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Abstract

本發明揭露一種薄膜電晶體之製造方法，包括：於基板上形成厚度小於20奈米之氧化物半導體通道層；於通道層之對側上形成源極及汲極電極；及於通道層上施加氧化劑。另一方面，本發明揭露一種薄膜電晶體之製造方法，包括：於基板上形成氧化物半導體通道層；於通道層之對側上形成源極及汲極電極；於通道層上施加氧化劑；及於通道層上形成自聚性單層膜(SAM)，其中，自聚性單層膜包括一無反應鏈，係具有對該氧化物半導體無氧化性之一末端基。

Description

薄膜電晶體
本發明係有關於具有氧化物半導體通道層之薄膜電晶體(TFT)之製造。
(金屬)氧化物薄膜電晶體之一重要參數為臨界電壓(threshold voltage)，即將裝置切換至導通之閘極電壓。臨界電壓容易受到製造過程中氧化所造成之氧化物半導體通道層缺陷影響。氧化物半導體通道層之氧化(氧氣不足)會使通道層留有過多之自由正電荷載子，其結果導致關閉狀態(off-state)之漏電流及負臨界電壓高。
習知方法係於製造過程之高溫(通常為400℃)含氧環境(在空氣中)下執行一退火(annealing)步驟來抑制此一結果，以使氧氣擴散並消除通道層中過多之正電荷載子。然而，此方法之缺點在於，運作需要的最低溫度約為250℃，無法與低成本基板相容，像是PEN(聚乙烯萘，polyethylene naphthalate)或PET(聚乙烯對苯二甲酸酯，polyethylene terephthalate)所製成之箔片(foils)。
美國專利US 7767505係揭示製造具有氧化物半導體通道層之薄膜電晶體，其中，於製造過程中，一氧化二氮電漿(nitrous oxide plasma)流程用以提供氧離子至通道層表面，然後退火步驟活化所提供之氧離子以於通道層內形成氧鍵(oxygen bonds)，從而減少過多之自由正電荷載 子。此方法之缺點在於需使用昂貴之電漿設備(plasma equipment)及危險的一氧化二氮氣體。
美國專利US 2009/0140243係揭示製造具有氧化物半導體通道層之薄膜電晶體，其中，於製造過程中，透過氧化劑之氧化處理來控制通道層表面之載子密度。三種方法係被揭露。根據第一種方法，係設置液體氧化劑以接觸通道層表面。液體氧化劑可包括：過錳酸鹽(permanganate)、過氯酸鹽(perchlorate)及過氧化物(peroxide compounds)。根據第二種方法，氧化處理包括於通道層表面上形成具有氧化劑之SAM(自聚性單層膜，self-assembled monolayer)。SAM可為含有SAM之磷酸基(phosphonic acid group)。除了第一或第二種方法之外，第三種方法所利用之一保護層(passivation layer)係由有機絕緣材料形成，並具有能夠氧化通道層之官能基(functional group)。可能需要將該保護層退火。
本發明之第一方面係提供一種薄膜電晶體之製造方法，包括：於基板上形成厚度小於20奈米之氧化物半導體通道層；於通道層之對側上形成源極及汲極電極；及於通道層上施加氧化劑。習知上，薄膜電晶體之通道層厚度通常為50-60奈米(nm)。於本發明中，透過限制通道層厚度所製造之薄膜電晶體，係可具有大幅減少之負臨界電壓，甚至是正臨界電壓。儘管目前尚不清楚此機制，當通道層 厚度小於20奈米時，效果變得顯著，且如第3(a)-3(c)圖所示，隨著通道層變薄，會更加明顯。通道層厚度小於15奈米較佳，小於12奈米更好，最好小於10奈米。
可將通道層依原先所需厚度沈積。除此之外，可將通道層以大於所需厚度沈積，接著蝕刻至所需厚度。
於一較佳實施例中，氧化劑為液態。氧化劑最好為過氧化氫(hydrogen peroxide)。過氧化氫為中立狀態(neutral form)，換言之，不與酸或催化劑結合。施加之步驟可包括：將通道層浸入最好為25-35%，或至少為15-45%，之過氧化氫水溶液中。施加之步驟產生具有既定臨界電壓之半導體層。
進一步，該方法最好包括：於該通道層上形成自聚性單層膜(SAM)，其中，自聚性單層膜包括一無反應鏈，係具有對該氧化物半導體無氧化性之一末端基。末端基可為與通道層之表面進行酸氧化反應之酸基。透過自聚性單層膜來穩定電晶體，可使臨界電壓維持在既定位準。
於一較佳實施例中，自聚性單層膜包括具有磷酸末端基之無反應烷烴十八烷基鏈。除此之外，可將碳酸、硫酸、或矽烷酸作為末端基。可將線性或支鏈烷烴分子、或芳香化合物作為無反應鏈之一部分。這些分子對氧化物半導體皆無氧化性。
本發明之第二方面係提供一種薄膜電晶體，包括：一氧化物半導體通道層，係於一基板上；以及源極及汲極電極，係於該通道層之對側上，其中，該通道層之厚度小於 20奈米。
本發明之第三方面系提供一種薄膜電晶體之製造方法，包括：於基板上形成氧化物半導體通道層；於該通道層之對側上形成源極及汲極電極；於該通道層上施加氧化劑；以及於該通道層形成自聚性單層膜(SAM)，其中，該自聚性單層膜包括一無反應鏈，係具有對該氧化物半導體無氧化性之一末端基。
該自聚性單層膜包括一無反應鏈，係具有對該氧化物半導體無氧化性之一末端基，用以穩定已氧化通道層之特徵並未揭示於習知技術中。特別地，於前述之美國專利US 2009/0140243中，所使用之自聚性單層膜具體地包括執行通道層氧化之官能基。
末端基可為與通道層之表面進行酸氧化反應之酸基。於一較佳實施例中，自聚性單層膜包括一無反應烷鏈，像是具有磷酸末端基之烷烴十八烷基鏈。除此之外，可將碳酸、硫酸、或矽烷酸作為末端基。可將線性或支鏈烷烴分子、或芳香化合物作為無反應鏈。這些分子對氧化物半導體皆無氧化性。由於磷酸及單氯矽烷(monochlorosilanes)為基底之自聚性單層膜之形成過程中會產生明顯缺陷，因此，一初始氧化步驟可於表面產生過氧化/氧化緩衝。
自聚性單層膜最好不與自身反應，即在表面不會發生聚合反應。為此，於正常大氣條件下不會聚合之磷酸為首選。基於同樣原因，三官能基矽烷(trifunctional silanes)並不適合。
本發明之第三方面係為：可單獨使用本發明之第一方面。
本發明之第四方面係提供一種薄膜電晶體，包括：一氧化物半導體通道層，係於一基板上；源極及汲極電極，係於該通道層之對側上；以及一自聚性單層膜(SAM)，係於該通道層上，其中，該自聚性單層膜包括一無反應鏈，係有對該氧化物半導體無氧化性之一末端基。
於說明書中，將“或”用於非互斥(non mutually exclusive)之情況下。
下文中相同或對應之部分係以相同或對應之參考標號表示之。
第1(a)-1(e)圖係顯示底接觸式(bottom contact)類型薄膜電晶體10之製造。
參考第1(a)圖，於基板15上形成閘極20。基板15最好包括PEN或PET箔片。於基板15上形成覆蓋閘極20之閘極絕緣層22。閘極絕緣層22可為氧化矽(SiOx)(例如：二氧化矽)或氮化矽(SiNx)層。形成閘極絕緣層22後，選擇性地執行濕洗(wet washing)流程，用以消除(或除去)閘極絕緣層22上表面之雜質。濕洗流程可將異丙醇(isopropyl alcohol,IPA)、去離子水、丙酮(acetone)等至少其中一作為清洗液。
參考第1(b)圖，於閘極絕緣層22上形成導電材料層 (未圖示)。可圖案化該導電材料層以形成源極電極26及汲極電極28。一般而言，可用乾或濕的方法來圖案化源極電極26及汲極電極28。濕方法可用具有磷酸(phosphoric acid)、硝酸(nitric acid)、醋酸(acetic acid)等之蝕刻液(etchant)來作為主要(或基本)元件。已圖案化之導電材料層，或電極26、28，可由鉬(Mo)單金屬層、具有一鉬層之多金屬層、具有鈦(Ti)之一金屬層、及具有鉻(Cr)之一金屬層製成。一導電材料，係包括鉬、鈦、鉑(Pt)、銅(Cu)、鋁(Al)、鎢(W)、鎢化鉬(MoW)、鋁釹(AlNd)、鎳(Ni)、銀(Ag)、金(Au)、銦鋅氧化物(IZO)、銦錫氧化物(ITO)及其組合至少其中之一，並可用以形成導電材料層，或電極26、28。一矽化物(silicide)，係包括鉬、鈦、鉑、銅、鋁、鎢、鎢化鉬、鋁釹、鎳、銀、金、銦鋅氧化物、銦錫氧化物及其組合至少其中之一，並可用以形成導電材料層，或電極26、28。用來形成導電材料層，或電極26、28，之導電材料，或矽化物，係可包括銅、鉬、鋁及其組合至少其中之一。可用PVD(物理氣相沉積，physical vapour deposition)方法來形成導電材料層。
參考第1(c)圖，係於閘極絕緣層22上將通道層24形成於源極電極26及汲極電極28之間，以對應於閘極20。可用具有一般濺鍍(sputtering)與蒸鍍(evaporation)之PVD方法來形成通道層24。
於一較佳實施例中，通道層24係由氧化鋅(ZnO)基材製成，像是GIZO(氧化鋅鎵銦，Ga-In-Zn-O)。GIZO可由 a(In203，三氧化二銦).b(Ga203，三氧化二鎵).c(ZnO，氧化鋅)形成，其中，a、b及c之實際值係分別滿足下式：a>=0、b>=0及c>0。GIZO可由a(In203).b(Ga203).c(ZnO)形成，其中，a、b及c之值係分別滿足下式：a>=1、b>=1及0<c<=1。於其他實施例中，可使用其他半導體材料系統。
通道層24之形成厚度係小於或等於10奈米(nm)。於較少之較佳實施例中，通道層24之形成厚度係從10奈米到20奈米。
由於通道層24特別容易受到製造過程中氧化所造成之缺陷影響，如第1(d)圖所示，係使用氧化劑來執行氧化處理。於一較佳實施例中，其處理包括將晶圓浸入70℃之30%過氧化氫溶液(hydrogen peroxide solution)10-15分鐘。過氧化氫溶液為正常狀態(normal form)，即不存在酸或催化劑(catalyst)。此處理產生具有既定臨界電壓之(微量)P型摻雜表面/半導體。
於其他實施例中，可使用其他氧化劑。過氧化氫由於其可用性與低毒性仍為較佳。
參考第1(e)圖，為穩定氧化表面以維持既定臨界電壓，係於通道層上形成SAM(自聚性單層膜，self-assembledmonolayer)30。於一較佳實施例中，係使用十八烷基磷酸(octadecyl phosphonic acid)SAM。如第2圖所示，通常SAM 30進一步包括無反應鏈(unreactive chain)30a，係具有對氧化物半導體材料無氧化性(但對其他材料具氧化性)之末端基(end group)30b，舉例而言，末端基30b可為 與通道層24之氧化表面進行酸氧化反應後接枝於其上之酸基(acid group)。可使用其他SAMs。
進一步參考第1(e)圖，係利用已知之沉積方法將一保護層(passivation layer)32選擇性地形成於SAM 30、源極與汲極電極26、28、及絕緣層22上。保護層24可由氮化矽(SiNx)或氧化矽(SiOx)形成。
依據上述之較佳實施例，第3(a)-3(c)圖係顯示所製造之電晶體之臨界電壓如何根據通道層厚度而改變。如第3(a)圖所示，通道層厚度為10奈米之電晶體之導通(switch-on)電壓由-2V轉移至+7V。如第3(b)圖所示，通道層厚度為15奈米之電晶體之導通電壓由-5V轉移至0V。當電晶體之通道層厚度大於20奈米時，導通電壓之轉移明顯要少得多。舉例來說，如第3(c)圖所示，於25奈米之情況下，只有從-12V些微地轉移至-10V。
於其他實施例中，電晶體可具有不同架構，舉例來講，可為上接觸式(top contact)類型電晶體。
本發明之每一特徵及任二或以上之特徵組合係已揭露如上，所屬領域中具有通常知識者能夠根據本說明書整體實現這些特徵或其組合，不論這些特徵或特徵之組合是否解決本文所揭示之問題，且非用以限定本發明之保護範圍。本發明可包括任一特徵或其組合。如上所述，所屬領域中具有通常知識者，在不脫離本發明之範圍內，當可做各種更動。
10‧‧‧薄膜電晶體
15‧‧‧基板
20‧‧‧閘極
22‧‧‧閘極絕緣層
24‧‧‧通道層
26‧‧‧源極電極
28‧‧‧汲極電極
30‧‧‧自聚性單層膜(SAM)
32‧‧‧保護層
第1(a)-1(e)圖係顯示底接觸式類型薄膜電晶體之製造。
第2圖係顯示依據本發明較佳實施例之SAM(自聚性單層膜，self-assembled monolayer)。
第3(a)-3(c)圖係說明於薄膜電晶體中，不同通道層厚度經由過氧化氫之氧化處理後，臨界電壓之轉移。
10‧‧‧薄膜電晶體
15‧‧‧基板
20‧‧‧閘極
22‧‧‧閘極絕緣層
24‧‧‧通道層
26‧‧‧源極電極
28‧‧‧汲極電極

Claims (12)

  1. 一種薄膜電晶體之製造方法，包括：於一基板上形成一氧化物半導體通道層；於該通道層之對側上形成源極及汲極電極；於該通道層上施加一氧化劑；以及於已施加該氧化劑之該通道層表面上形成一自聚性單層膜(SAM)，其中，該自聚性單層膜包括與該氧化物半導體相關之一無反應鏈，係具有對該氧化物半導體無氧化性之一末端基。
  2. 如申請專利範圍第1項所述之薄膜電晶體之製造方法，其中，該末端基係為與該通道層表面進行酸氧化反應之一酸基。
  3. 如申請專利範圍第1或2項所述之薄膜電晶體之製造方法，其中，該無反應鏈為一烷鏈(aliphatic chain)。
  4. 如申請專利範圍第1至3項中任一項所述之薄膜電晶體之製造方法，其中，該自聚性單層膜包括烷烴十八烷基鏈(alkane octadecyl chain)、線性烷烴分子(linear alkane molecules)、支鏈烷烴分子(branched alkane molecules)、或芳香化合物(aromatic compounds)其中之一，用以作為該無反應鏈。
  5. 如申請專利範圍第4項所述之薄膜電晶體之製造方法，其中，該自聚性單層膜包括磷酸、碳酸、硫酸、或矽烷酸其中之一，用以作為該末端基。
  6. 一種薄膜電晶體之製造方法，包括： 於一基板上形成厚度小於20奈米之一氧化物半導體通道層；於該通道層之對側上形成源極及汲極電極；以及於該通道層上施加一氧化劑。
  7. 如申請專利範圍第6項所述之薄膜電晶體之製造方法，其中，該通道層之厚度係小於15奈米，較佳為小於12奈米，最好為小於10奈米。
  8. 如申請專利範圍第6或7項所述之薄膜電晶體之製造方法，其中，該氧化劑為正常狀態之液態過氧化氫。
  9. 如申請專利範圍第1至8項中任一項所述之薄膜電晶體之製造方法，更包括：於該通道層上形成一自聚性單層膜(SAM)，其中，該自聚性單層膜包括一無反應鏈，係具有對該氧化物半導體無氧化性之一末端基。
  10. 一種薄膜電晶體，包括：一氧化物半導體通道層，係於一基板上；源極及汲極電極，係於該通道層之對側上，其中，該通道層之厚度小於20奈米。
  11. 一種薄膜電晶體，包括：一氧化物半導體通道層，係於一基板上；源極及汲極電極，係於該通道層之對側上；以及一自聚性單層膜(SAM)，係於該通道層上，其中，該自聚性單層膜包括與該氧化物半導體相關之一無反應鏈，其具有對該氧化物半導體無氧化性之一末端基。
  12. 如申請專利範圍第11項所述之薄膜電晶體，其中，該自聚性單層膜為以磷酸(phosphoric acid)或單氯矽烷(monochlorosilanes)為基底之自聚性單層膜。
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JP2014517540A (ja) 2014-07-17
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KR20140043753A (ko) 2014-04-10
KR102004555B1 (ko) 2019-07-26
EP2535929A1 (en) 2012-12-19
WO2012171727A1 (en) 2012-12-20
CN103597595A (zh) 2014-02-19
US20140110844A1 (en) 2014-04-24
TW201305396A (zh) 2013-02-01
US9076773B2 (en) 2015-07-07
JP2017123466A (ja) 2017-07-13

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