TW201304083A - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

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TW201304083A
TW201304083A TW101104583A TW101104583A TW201304083A TW 201304083 A TW201304083 A TW 201304083A TW 101104583 A TW101104583 A TW 101104583A TW 101104583 A TW101104583 A TW 101104583A TW 201304083 A TW201304083 A TW 201304083A
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semiconductor
semiconductor wafer
semiconductor device
resin
underfill
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TW101104583A
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TWI484601B (zh
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Masatoshi Fukuda
Hiroshi Watabe
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Toshiba Kk
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    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Abstract

本發明之半導體裝置包括：配線基板；半導體晶片積層體，其搭載於該配線基板上；底部填充層，其填充於半導體晶片積層體之各半導體晶片之間之間隙中；及密封層，其包含被覆、形成於半導體晶片積層體等之外側之模製樹脂。底部填充層包含含有胺系硬化劑之樹脂材料之硬化物，且該硬化物具有65℃以上100℃以下之Tg。

Description

半導體裝置及半導體裝置之製造方法
本發明之實施形態係關於一種半導體裝置及半導體裝置之製造方法。
[關聯申請案之參照]
本申請案享有於2011年3月11日申請之日本專利申請案號2011-54534之優先權之利益，且該日本專利申請案之全部內容引用於本申請案中。
近年來，伴隨著電子機器之高功能化及小型化之要求，進行半導體積體電路之高密度安裝技術之開發。作為此種安裝技術之一，有以面朝下之方式將其他半導體晶片搭載於半導體晶片上之晶片堆疊型系統級封裝。此種晶片堆疊構造因對於半導體封裝之小型化、動作之高速化、省電化方面有效故備受矚目。
於晶片堆疊型之構造中，半導體晶片間之連接通常係以經由微小之凸塊之倒裝晶片方式而進行。而且，為了保護連接部以避免濕度等周圍之環境之影響，且確保機械性強度，而向半導體晶片之間注入樹脂材料形成底部填充層。
然而，於自先前之晶片堆疊型之半導體裝置中，若反覆進行低溫-高溫之溫度循環，則於上段之半導體晶片之側面與構成底部填充層之底部填充樹脂之間容易產生剝離。而且，存在產生以下不良：該剝離自底部填充樹脂內成為龜裂並傳播，會切斷下段之半導體晶片之內部配線等。
本發明所欲解決之問題在於提供一種於溫度循環等之施加時，能夠抑制底部填充樹脂之剝離，且可防止半導體晶片之斷線不良等之半導體裝置及半導體裝置之製造方法。
實施形態之半導體裝置包括：配線基板，其於至少一主面具有配線層；半導體晶片積層體，其安裝於上述配線基板之上述主面，將2個以上之半導體晶片隔開特定之間隔而重疊配置，且各半導體晶片相互經由凸塊電性地連接；底部填充層，其包含填充於上述半導體晶片積層體之各半導體晶片之間之間隙中的樹脂；及密封層，其包含被覆、形成於上述半導體晶片積層體之外側之模製樹脂；且 上述底部填充層包含含有胺系硬化劑之樹脂材料之硬化物，且上述硬化物之玻璃轉移溫度(Tg)為65℃以上100℃以下。
另一實施形態之半導體裝置之製造方法包括下述之步驟：準備於至少一主面具有配線層之配線基板；將2個以上之半導體晶片隔開特定之間隔而重疊配置於上述配線基板之主面，且將各半導體晶片相互經由凸塊而電性連接地安裝；向上述半導體晶片積層體之各半導體晶片之間之間隙中注入並填充熱硬化性樹脂材料；藉由使上述熱硬化性樹脂材料熱硬化，而於上述間隙中形成包含底部填充樹脂之底部填充層；及以被覆上述半導體晶片積層體之外側之 方式形成包含模製樹脂之密封層；且 上述底部填充樹脂含有胺系硬化劑，且具有65℃以上100℃以下之玻璃轉移溫度(Tg)。
根據上述構成之半導體裝置及半導體裝置之製造方法，可於溫度循環等之施加時，抑制底部填充樹脂之剝離，並可防止半導體晶片之斷線不良等。
根據1實施形態，提供一種半導體裝置，其包括：配線基板，其於至少一主面具有配線層；半導體晶片積層體，其安裝於上述配線基板之上述主面，將2個以上之半導體晶片隔開特定之間隔而重疊配置，且各半導體晶片相互經由凸塊電性地連接；底部填充層，其包含填充於上述半導體晶片積層體之各半導體晶片之間之間隙中的樹脂；及密封層，其包含被覆、形成於上述半導體晶片積層體之外側之模製樹脂。於此種半導體裝置中，上述底部填充層包含含有胺系硬化劑之樹脂材料之硬化物，且該上述硬化物之玻璃轉移溫度(Tg)為65℃以上100℃以下。
又，根據一實施形態，提供一種半導體裝置之製造方法，其包括下述步驟：準備於至少一主面具有配線層之配線基板；將2個以上之半導體晶片隔開特定之間隔而重疊配置於上述配線基板之主面，且將各半導體晶片相互經由凸塊而電性連接地安裝；向上述半導體晶片積層體之各半導體晶片間之間隙中注入並填充熱硬化性樹脂材料；藉由使上述熱硬化性樹脂材料熱硬化，而於上述間隙中形成包 含底部填充樹脂之底部填充層；及以被覆上述半導體晶片積層體之外側之方式形成包含模製樹脂之密封層。於此種半導體裝置之製造方法中，上述底部填充樹脂含有胺系硬化劑，且具有65℃以上100℃以下之玻璃轉移溫度(Tg)。
(第1實施形態)
圖1係表示第1實施形態之半導體裝置之剖面圖。
圖1所示之半導體裝置10包括：配線基板1，其於作為一主面之表面(於圖1中為上表面)具有配線電路(省略圖示)；半導體晶片積層體2，其搭載於該配線基板1之上述表面，且電性地連接。該半導體裝置10具有FBGA(Fine pitch Ball Grid Array，細線距球閘陣列)封裝之形態。
半導體晶片積層體2具有下述構造：將主平面之面積小於第1半導體晶片2a之第2半導體晶片2b以各自之電路面(元件電路面)相對向之方式，配置於面朝上地配置之第1半導體晶片2a之上，且經由凸塊3連接。第1及第2半導體晶片2a、2b之厚度均為350 μm以下。
凸塊3包含：Sn-Ag焊料(熔點221℃)或Sn-Cu焊料(熔點227℃)等Sn系焊料，或者Au、Sn(熔點232℃)、Cu、Ni、Ag、Pd等金屬材料。凸塊直徑為5~50 μm，排列之間距為10~100 μm。於第1及第2半導體晶片2a、2b與凸塊3之連接中使用熱壓接合或回焊等。
於半導體晶片積層體2中，第1半導體晶片2a與第2半導體晶片2b之間之間隙較佳為5~50 μm，更佳為20~30 μm。將熱硬化性樹脂材料填充於第1半導體晶片2a與第2半導體 晶片2b之間之間隙中，並使其硬化，而形成包含底部填充樹脂之底部填充層4。此處，構成底部填充層4之底部填充樹脂包含含有胺系硬化劑之環氧系樹脂之硬化物。底部填充樹脂之Tg為65℃以上100℃以下。底部填充樹脂之較佳之Tg為65℃以上95℃以下，更佳之Tg為65℃以上90℃以下。
於使用除了胺系以外之例如調配有酸酐系化合物之樹脂材料作為硬化劑，而形成底部填充層4之情形時，無法於溫度循環施加時，抑制於半導體晶片側面底部填充樹脂之剝離。又，於底部填充樹脂之Tg超過100℃之情形時，亦同樣地，無法抑制溫度循環施加時之底部填充樹脂之剝離。再者，就底部填充樹脂之剝離抑制之觀點而言，硬化物之Tg越低則越有效。
底部填充樹脂之Tg之測定可藉由TMA(熱機械分析，Thermo mechanical analysis)而進行。TMA為一面藉由一定之程式使試樣之溫度變化，一面施加壓縮、拉伸、彎曲等非振動性負載，並將該物質之變形作為溫度或時間之函數而測定之方法。若對應於溫度變化而引起試樣之熱膨脹或軟化等變形，則伴隨著變形之位移量係作為探針之位置變化量而由位移檢測部測量。實施形態所記載之Tg係藉由TMA法而測定者。
再者，Tg之測定亦可藉由DMA(動態黏彈性測定，Dynamic mechanical analysis)而進行。
又，為了使熱膨脹係數接近於矽晶片之熱膨脹係數，而 使底部填充樹脂中含有二氧化矽粉末等無機填充材。於實施形態中，含於底部填充樹脂中之無機填充材較佳為平均粒徑未達0.5 μm且最大粒徑為3.0 μm以下者。無機填充材之平均粒徑更佳為未達0.4 μm，進而較佳為未達0.3 μm。再者，平均粒徑係藉由雷射繞射型散射法而測定者。
於含於底部填充樹脂中之無機填充材之平均粒徑為0.5 μm以上之情形時，會因無機填充材而妨礙用於形成底部填充樹脂之樹脂材料之流動。因此，於實施形態之晶片堆疊型之半導體裝置中，難以將底部填充樹脂材料填充於半導體晶片2a、2b之間之狹窄間隙(5~50 μm)中。因此，難以無空隙且無偏析地形成均勻之組成之底部填充層4。再者，將用於形成底部填充樹脂之硬化前之材料稱作底部填充樹脂材料。
底部填充層並不限定設置於晶片堆疊型之半導體裝置中，亦可設置於在基板上搭載晶片之覆晶BGA(Ball Grid Array，球狀柵格陣列)(以下，表示為FC-BGA)中。而且，作為構成上述FC-BGA之底部填充層之樹脂，亦使用含有胺系硬化劑且硬化物之Tg為100℃以下之環氧系樹脂。然而，於FC-BGA中使用之樹脂(以下，表示為FC-BGA用樹脂)，與實施形態中使用之底部填充樹脂相比，含有粒徑較大(平均粒徑0.5 μm以上，最大粒徑3 μm以上)之無機填充材(例如二氧化矽粉末)。因此，FC-BGA用樹脂與實施形態中使用之底部填充樹脂相比，硬化前之流動性較差。因此，先前之用於形成FC-BGA用樹脂之材料雖可填充於 基板與半導體晶片之間之相對較大之間隙(50~70 μm)中，但難以將其填充於實施形態之半導體裝置10中之半導體晶片2a、2b之間之狹窄間隙(5~50 μm)中，而導致產生未填充。再者，將用於形成FC-BGA用樹脂之硬化前之材料表示為FC-BGA用樹脂材料。
以下，記載對實施形態中使用之底部填充樹脂材料與先前之FC-BGA用樹脂材料之流動性進行調查之結果。再者，實施形態之底部填充樹脂材料為如下之樹脂材料，即，以50質量%之比例計含有平均粒徑為0.3 μm且最大粒徑為3.0 μm之二氧化矽粉末，且用於形成下述之底部填充樹脂G。又，作為FC-BGA用樹脂材料，使用含有胺系硬化劑且以50質量%之比例計含有平均粒徑為0.6 μm且最大粒徑為3.0 μm之二氧化矽粉末且硬化物之Tg為100℃之環氧系樹脂材料。
(流動性之比較實驗)
以形成20 μm之間隙之方式固定2塊玻璃板，且使實施形態之底部填充樹脂材料與先前之FC-BGA用樹脂材料分別滲透於該間隙。接下來，測定僅滲透特定之距離(20 mm)所需之時間。再者，將玻璃板加熱至110℃。
測定之結果為，實施形態之底部填充樹脂材料與FC-BGA用樹脂材料之填充時間均為300秒，為相同。然而，於FC-BGA用樹脂材料中，於滲透後可觀察到流痕。所謂流痕係指因樹脂中之填充料或其他成分之偏析等，而使不均勻之部分於觀察時呈筋狀者，且於樹脂之流動性差之情 形時產生。若產生流痕，則因流動之前端形狀紊亂，且滲透時混入空氣而易產生空隙故不佳。藉由該實驗，可確定：實施形態之用於形成底部填充樹脂之樹脂材料與FC-BGA用樹脂材料相比，流動性為良好。
於第1實施形態之半導體裝置10中，半導體晶片積層體2如以下般搭載於配線基板1之上，且電性地連接。藉由晶粒黏著材5將半導體晶片積層體2之下段側之第1半導體晶片2a之下表面固定於配線基板1上。
上述構造可藉由如下方法而形成，該方法包含形成半導體晶片積層體2之步驟、及將該半導體晶片積層體2安裝於配線基板1之上之步驟。又，亦可藉由其他方法而形成，該方法包含將第1半導體晶片2a配置於配線基板1上之第1步驟、及將第2半導體晶片2b配置於第1半導體晶片2a上且經由凸塊3連接該等之第2步驟。
而且，配置於該第1半導體晶片2a之上表面(元件電路面)之周邊部之連接墊21a、與配線基板1之連接端子1a係藉由金線等接線6而連接。於配線基板1之背面配設有藉由焊料球等而形成之外部連接用端子7。
以覆蓋半導體晶片積層體2、及半導體晶片積層體2與配線基板1之上述連接部之外側之方式，形成包含模製樹脂之密封層8。密封層8之側端面係相對於配線基板1之主面垂直地形成。
作為構成密封層8之模製樹脂，使用環氧系樹脂。較佳為使用物性值處於以下所示之範圍內之模製樹脂。再者， 該等之物性值為藉由上述TMA之測定所得之值。
Tg：130~200℃
未達Tg之溫度時之熱膨脹係數(CTE(Coefficient of thermal expansion)1)：0.8~1.4 ppm/℃
Tg以上之溫度時之熱膨脹係數(CTE2)：3.0~4.9 ppm/℃
彈性模數：15~30 GPa
於使用具有上述物性值之模製樹脂之情形時，密封層8之熱應力之緩和效果較高，尤其具有減少封裝全體之翹曲之優異效果。
於第1實施形態中，藉由為含有胺系硬化劑之樹脂材料之硬化物，且Tg為65℃以上100℃以下之底部填充樹脂而構成底部填充層4，故可抑制於溫度循環施加時之第2半導體晶片2b側面底部填充樹脂之剝離，且可防止第1半導體晶片2a之內部配線之切斷等斷線不良。
一般可認為：溫度循環施加時之底部填充樹脂之剝離係因作用於半導體晶片(第2半導體晶片2b)之側面與底部填充樹脂之間之剝離應力而產生。將底部填充樹脂之Tg降低至100℃以下之方法對於上述剝離應力之降低具有效果。又，使底部填充樹脂中含有胺系硬化劑之方法具有使底部填充樹脂對半導體晶片側面之密接力增大之效果。於實施形態中，以綜合該等2種效果，可防止底部填充樹脂之剝離。
再者，於圖1所示之第1實施形態中，亦可於半導體晶片積層體2之上，進一步積層其他半導體晶片(記憶體晶片 等)。即，亦可採用如下形態，即，於半導體晶片積層體2之第2半導體晶片2b之上，面朝上(使元件電路面為上側)地積層第3半導體晶片，並由晶粒黏著材等固定，進而藉由接線連接。
其次，對此種第1實施形態之具體之實施例進行說明。
實施例1~11、比較例1~6 (底部填充樹脂A~L)
首先，將表1所示之粒徑(平均粒徑及最大粒徑)之無機填充材(二氧化矽粉末)以成為該表所示之調配比例(質量%)之方式混合於環氧系樹脂中，進一步添加、混合表1所示之硬化劑，而製備底部填充樹脂材料AA~LL。
對於如此所獲得之作為底部填充樹脂材料AA~LL之硬化物之底部填充樹脂A~L，藉由TMA求得Tg、熱膨脹係數(CTE1、CTE2)及彎曲彈性模數(25℃)。將該等測定結果分別示於表1。再者，於TMA測定中使用MAC SCIENCE公司製造之熱機械分析裝置。
(半導體裝置之製造)
其次，將用以形成表1所示之底部填充樹脂A~L之樹脂材料AA~LL填充於第1半導體晶片2a與第2半導體晶片2b之間之間隙中，並使其熱硬化，而形成包含底部填充樹脂A~L之底部填充層。又，使用a及b之2種模製樹脂而形成密封層8，並製造圖1所示之半導體裝置10。模製樹脂a及b之物性值示於以下。
第1半導體晶片2a之尺寸為7.5 mm×7.1 mm，第2半導體晶片2b之尺寸為5.9 mm×5.2 mm，且厚度均為150 μm。又，連接該等半導體晶片之間之凸塊3為Sn-Cu焊料凸塊，且凸塊直徑為30 μm，間距為60 μm。模製樹脂a之物性值中，Tg為130℃，CTE1為0.8 ppm/℃，CTE2為3.0 ppm/℃，且25℃時之彎曲彈性模數為30 GPa。又，模製樹脂b之物性值中，Tg為200℃，CTE1為1.4 ppm/℃，CTE2為4.9 ppm/℃，且25℃時之彎曲彈性模數為15 GPa。再者，模製樹脂之物性值與上述底部填充樹脂同樣地為藉由TMA法並使用MAC SCIENCE公司製造之熱機械分析裝置而測定之值。
(可靠性試驗)
利用溫度循環試驗(-55℃/125℃)，對以實施例1~11及比較例1~6所得之半導體裝置10之可靠性進行確認。於對該等半導體裝置10施加500循環之-55℃/125℃之溫度循環後，進行剖面解析而調查第2半導體晶片2b之側面與底部填充樹脂之間之剝離之有無。結果示於表2。
根據表2之結果可確認：因於實施例1~11中，使用包含胺系硬化劑，且硬化物之Tg為65℃以上100℃以下之底部填充樹脂材料BB~II而形成包含底部填充樹脂B~I之底部填充層4，故可獲得於溫度循環試驗(TCT)中未產生底部填充層4之剝離，而可靠性較高之半導體裝置10。
(第2實施形態)
圖2係表示第2實施形態之半導體裝置之剖面圖。
圖2所示之第2實施形態之半導體裝置10包含配線基板1，其於為一主面之表面(於圖2中為上表面)具有配線電路，且於背面具有藉由鍍金等而形成之外部連接用端子7。而且，於該配線基板1之表面安裝有將自第1至第4為止之4個半導體晶片2a、2b、2c、2d相互隔開特定之間隔而配置之半導體晶片積層體2。再者，第1半導體晶片2a、第2半導體晶片2b、第3半導體晶片2c及第4半導體晶片2d均具有大致相同之主面之面積。又，厚度均為50 μm以下。
於配線基板1之表面形成有包含鍍金層之連接端子1a，且作為最下段之半導體晶片之第1半導體晶片2a經由第1凸塊連接部3a連接於該連接端子1a之上。又，於該第1半導 體晶片2a之上配置有第2半導體晶片2b，且第2半導體晶片2b與第1半導體晶片2a係經由第2凸塊連接部3b而連接。又，於第2半導體晶片2b之上配置有第3半導體晶片2c，且第2半導體晶片2b與第3半導體晶片2c係經由第3凸塊連接部3c而連接，進而於第3半導體晶片2c之上配置有第4半導體晶片2d，且該等半導體晶片係藉由第4凸塊連接部3d而連接。自第1至第4半導體晶片2a、2b、2c、2d之間之間隙均為5~50 μm。
第1凸塊連接部3a中，將第1半導體晶片2a之下表面側之例如焊料凸塊與配線基板1之包含鍍金層之連接端子1a連接。又，第2凸塊連接部3b、第3凸塊連接部3c、及第4凸塊連接部3d中，於各半導體晶片之下段側分別形成有Sn-Ag焊料(熔點221℃)或Sn-Cu焊料(熔點227℃)等Sn系焊料或Sn之凸塊，而於上段側分別形成有Sn-Ag焊料或Sn-Cu焊料等之Sn系焊料，或Sn、Au、Ag、Pd、Ni、Cu等凸塊，並將該等凸塊接合一體化。凸塊直徑為5~50 μm且排列之間距為10~100 μm。
又，於第1半導體晶片2a、第2半導體晶片2b及第3半導體晶片2c中設置有分別貫通正反面之稱作TSV(Through Silicon Via，矽穿孔)之通孔(省略圖示)，且將自積層之第1半導體晶片2a至第4半導體晶片2d為止相互地電性連接。
接下來，將熱硬化性樹脂材料分別填充於如此般經由凸塊而連接之第1半導體晶片2a與配線基板1之間隙中、及自第1半導體晶片2a至第4半導體晶片2d為止之各半導體晶片 之間之間隙中，而形成底部填充層4。底部填充層4與第1實施形態同樣地，藉由作為含有無機填充材及胺系硬化劑之環氧系樹脂之硬化物的底部填充樹脂而構成。底部填充樹脂之Tg為65℃以上100℃以下。底部填充樹脂之較佳Tg為65℃以上95℃以下，更佳之Tg為65℃以上90℃以下。底部填充樹脂較佳含有平均粒徑未達0.5 μm且最大粒徑為3.0 μm以下之二氧化矽粉末作為無機填充材。
用於形成底部填充樹脂之樹脂材料(底部填充樹脂材料)之填充亦可於對自第1半導體晶片2a至第4半導體晶片2d為止之4個半導體晶片全部進行積層、配置後，一次性地對配線基板1與第1半導體晶片2a之間隙、及各半導體晶片之間之間隙進行填充。又，亦可自下段側依序積層半導體晶片，並依序將底部填充樹脂材料填充於形成之間隙中。
半導體晶片積層體2經由第1凸塊連接部3a連接於配線基板1連接端子1a，進而通過配線基板1之配線電路，連接於形成於背面之外部連接用端子7。
接下來，以覆蓋半導體晶片積層體2及半導體晶片積層體2與配線基板1之上述連接部之外側之方式，形成包含模製樹脂之密封層8。密封層8之側端面相對於配線基板1之主面垂直地形成。作為模製樹脂，較佳為使用具有與第1實施形態相同之物性值之環氧系樹脂。
於如此般構成之第2實施形態中，可抑制於溫度循環施加時，於半導體晶片側面之底部填充樹脂之剝離。
根據以上說明之至少一實施形態，於晶片堆疊型之半導 體裝置中，藉由以含有胺系硬化劑之環氧系樹脂之硬化物(Tg為65℃以上100℃以下)構成底部填充層4，可抑制於溫度循環施加時，於上段側之半導體晶片側面之底部填充樹脂之剝離，且可使可靠性提高。
已對本發明之一些實施形態進行了說明，但該等實施形態係作為示例而提示者，並不意欲對發明之範圍進行限定。該等新穎之實施形態可由其他各種形態而實施，且可於不脫離發明之主旨之範圍內進行各種省略、置換、變更。該等實施形態或其變形包含於發明之範圍或主旨中，並且包含於申請專利範圍所記載之發明及其均等之範圍內。
1‧‧‧配線基板
1a‧‧‧連接端子
2‧‧‧半導體晶片積層體
2a‧‧‧第1半導體晶片
2b‧‧‧第2半導體晶片
2c‧‧‧第3半導體晶片
2d‧‧‧第4半導體晶片
3‧‧‧凸塊
3a‧‧‧第1凸塊連接部
3b‧‧‧第2凸塊連接部
3c‧‧‧第3凸塊連接部
3d‧‧‧第4凸塊連接部
4‧‧‧底部填充層
5‧‧‧晶粒黏著材
6‧‧‧接線
7‧‧‧外部連接用端子
8‧‧‧密封層
10‧‧‧半導體裝置
21a‧‧‧連接墊
G‧‧‧底部填充樹脂
圖1係表示第1實施形態之半導體裝置之剖面圖。
圖2係表示第2實施形態之半導體裝置之剖面圖。
1‧‧‧配線基板
1a‧‧‧連接端子
2‧‧‧半導體晶片積層體
2a‧‧‧第1半導體晶片
2b‧‧‧第2半導體晶片
3‧‧‧凸塊
4‧‧‧底部填充層
5‧‧‧晶粒黏著材
6‧‧‧接線
7‧‧‧外部連接用端子
8‧‧‧密封層
10‧‧‧半導體裝置
21a‧‧‧連接墊

Claims (20)

  1. 一種半導體裝置，其包括：配線基板，其於至少一主面具有配線層；半導體晶片積層體，其安裝於上述配線基板之上述主面，將2個以上之半導體晶片隔開特定之間隔而重疊配置，且各半導體晶片相互經由凸塊而電性地連接；底部填充層，其包含填充於上述半導體晶片積層體之各半導體晶片之間之間隙中的樹脂；及密封層，其包含被覆、形成於上述半導體晶片積層體之外側之模製樹脂；且上述底部填充層包含：包含胺系硬化劑樹脂材料之硬化物；且上述硬化物之玻璃轉移溫度(Tg)為65℃以上100℃以下。
  2. 如請求項1之半導體裝置，其中上述半導體晶片積層體包含：第1半導體晶片，其面朝上地配置於上述配線基板之上述主面；及第2半導體晶片，其以元件電路面相對向之方式配置於上述第1半導體晶片之上，且主面之面積較上述第1半導體晶片小。
  3. 如請求項1之半導體裝置，其中構成上述底部填充層之樹脂為環氧系樹脂。
  4. 如請求項1之半導體裝置，其中上述底部填充層含有平均粒徑未達0.5 μm之無機填充材。
  5. 如請求項4之半導體裝置，其中上述無機填充材為二氧 化矽粉末。
  6. 如請求項1之半導體裝置，其中上述凸塊包含選自如Sn-Ag焊料及Sn-Cu焊料之Sn系焊料、Au、Sn、Cu、Ag、Pd及Ni中之至少1種金屬材料。
  7. 如請求項1之半導體裝置，其中上述凸塊之直徑為5~50 μm，排列之間距為10~100 μm。
  8. 如請求項1之半導體裝置，其中構成上述半導體晶片積層體之各半導體晶片之間之間隙為5~50 μm。
  9. 如請求項1之半導體裝置，其中構成上述半導體晶片積層體之2個以上之半導體晶片之厚度均為350 μm以下。
  10. 如請求項1之半導體裝置，其中上述模製樹脂中，Tg為130~200℃，未達Tg之溫度時之熱膨脹係數(CTE1)為0.8~1.4 ppm/℃，Tg以上之溫度時之熱膨脹係數(CTE2)為3.0~4.9 ppm/℃，且彎曲彈性模數為15~30 GPa。
  11. 如請求項1之半導體裝置，其中上述模製樹脂為環氧系樹脂。
  12. 如請求項1之半導體裝置，其中上述密封層之側端面相對於上述配線基板之主面垂直地形成。
  13. 如請求項1之半導體裝置中，其中上述半導體晶片積層體具有主面之面積大致相同之2個以上之半導體晶片相互隔開特定之間隔而配置，且經由上述凸塊連接之構造。
  14. 如請求項13之半導體裝置中，其中構成上述半導體晶片積層體之2個以上之半導體晶片之厚度均為50 μm以下。
  15. 一種半導體裝置之製造方法，其包括下述之步驟：準備於至少一主面具有配線層之配線基板；將2個以上之半導體晶片隔開特定之間隔而重疊配置於上述配線基板之主面，且將各半導體晶片相互經由凸塊而電性連接地安裝；向上述半導體晶片積層體之各半導體晶片間之間隙中注入並填充熱硬化性樹脂材料；藉由使上述熱硬化性樹脂材料熱硬化，而於上述間隙中形成包含底部填充樹脂之底部填充層；及以被覆上述半導體晶片積層體之外側之方式形成包含模製樹脂之密封層；且上述底部填充樹脂包含胺系硬化劑，且具有65℃以上100℃以下之玻璃轉移溫度(Tg)。
  16. 如請求項15之半導體裝置之製造方法，其中上述熱硬化性樹脂材料為將環氧系樹脂作為主體之材料。
  17. 如請求項15之半導體裝置之製造方法，其中上述熱硬化性樹脂材料含有平均粒徑未達0.5 μm之無機填充材。
  18. 如請求項15之半導體裝置之製造方法，其中構成上述半導體晶片積層體之各半導體晶片之間之間隙為5~50 μm。
  19. 如請求項15之半導體裝置之製造方法，其中構成上述半導體晶片積層體之2個以上之半導體晶片之厚度均為350 μm以下。
  20. 如請求項15之半導體裝置之製造方法，其中上述模製樹 脂中，Tg為130~200℃，未達Tg之溫度時之熱膨脹係數(CTE1)為0.8~1.4 ppm/℃，Tg以上之溫度時之熱膨脹係數(CTE2)為3.0~4.9 ppm/℃，且彎曲彈性模數為15~30 GPa。
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101719636B1 (ko) * 2011-01-28 2017-04-05 삼성전자 주식회사 반도체 장치 및 그 제조 방법
JP2013168577A (ja) * 2012-02-16 2013-08-29 Elpida Memory Inc 半導体装置の製造方法
KR102000678B1 (ko) * 2012-10-26 2019-07-16 삼성전자주식회사 반도체 장치 및 이를 제조하는 방법
JP5853944B2 (ja) * 2012-12-25 2016-02-09 住友ベークライト株式会社 半導体装置の製造方法
CN103137611A (zh) * 2013-01-22 2013-06-05 日月光半导体制造股份有限公司 晶片堆迭构造及其制造方法
JP2014152302A (ja) * 2013-02-13 2014-08-25 Sumitomo Bakelite Co Ltd 半導体封止用エポキシ樹脂組成物、半導体装置の製造方法及び半導体装置
KR102053349B1 (ko) * 2013-05-16 2019-12-06 삼성전자주식회사 반도체 패키지
KR102147354B1 (ko) * 2013-11-14 2020-08-24 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
KR102107961B1 (ko) 2013-11-14 2020-05-28 삼성전자 주식회사 반도체 장치 및 이의 제조 방법
CN104795334B (zh) * 2015-03-05 2018-01-05 浙江中控研究院有限公司 模块化封装的集成电路芯片及其制作方法
JP2017112325A (ja) * 2015-12-18 2017-06-22 Ｔｏｗａ株式会社 半導体装置及びその製造方法
KR102579876B1 (ko) * 2016-02-22 2023-09-18 삼성전자주식회사 반도체 패키지
JP6718837B2 (ja) * 2016-04-01 2020-07-08 スカイワークスフィルターソリューションズジャパン株式会社 電子部品とその製造方法、及び電子装置とその製造方法
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10529637B1 (en) 2018-10-31 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method of forming same
KR20210022321A (ko) * 2019-08-20 2021-03-03 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
JP2021129083A (ja) * 2020-02-17 2021-09-02 キオクシア株式会社 半導体装置およびその製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6670430B1 (en) * 1999-12-17 2003-12-30 Henkel Loctite Corporation Thermosetting resin compositions comprising epoxy resins, adhesion promoters, and curatives based on the combination of nitrogen compounds and transition metal complexes
JP2003297873A (ja) * 2002-03-29 2003-10-17 Hitachi Ltd 半導体装置，構造体及び電子装置
WO2003091338A1 (en) * 2002-04-26 2003-11-06 Kaneka Corporation Hardenable composition, hardening product, process for producing the same and light emitting diode sealed with the hardening product
KR20060123285A (ko) * 2003-11-10 2006-12-01 헨켈 코포레이션 저-ｋ 유전재료-함유 반도체 소자와 함께 사용되는 전자패키징 재료
US7279359B2 (en) * 2004-09-23 2007-10-09 Intel Corporation High performance amine based no-flow underfill materials for flip chip applications
JP4757070B2 (ja) * 2006-03-27 2011-08-24 富士通株式会社 半田付け用フラックス及び半導体素子の接合方法
TWI414580B (zh) 2006-10-31 2013-11-11 Sumitomo Bakelite Co 黏著帶及使用該黏著帶而成之半導體裝置
JP5388341B2 (ja) * 2009-03-31 2014-01-15 ナミックス株式会社 アンダーフィル用液状樹脂組成物、フリップチップ実装体およびその製造方法
JP5658436B2 (ja) * 2009-04-16 2015-01-28 株式会社東芝 半導体装置
US8828806B2 (en) * 2009-06-01 2014-09-09 Shin-Etsu Chemical Co., Ltd. Dam composition for use with multilayer semiconductor package underfill material, and fabrication of multilayer semiconductor package using the same
JP5577640B2 (ja) * 2009-07-24 2014-08-27 日立化成株式会社 半導体装置の製造方法
JP5508802B2 (ja) 2009-09-30 2014-06-04 株式会社東芝 半導体装置の製造方法
US8536718B2 (en) * 2010-06-24 2013-09-17 Stats Chippac Ltd. Integrated circuit packaging system with trenches and method of manufacture thereof
JP2012015398A (ja) 2010-07-02 2012-01-19 Toshiba Corp 半導体装置

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