TW201216414A - Methods for in-situ passivation of silicon-on-insulator wafers - Google Patents

Methods for in-situ passivation of silicon-on-insulator wafers Download PDF

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Publication number
TW201216414A
TW201216414A TW100123193A TW100123193A TW201216414A TW 201216414 A TW201216414 A TW 201216414A TW 100123193 A TW100123193 A TW 100123193A TW 100123193 A TW100123193 A TW 100123193A TW 201216414 A TW201216414 A TW 201216414A
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TW
Taiwan
Prior art keywords
wafer
chamber
insulating layer
split surface
split
Prior art date
Application number
TW100123193A
Other languages
English (en)
Chinese (zh)
Inventor
Michael J Ries
Dale A Wittle
Anca Stefanescu
Andrew M Jones
Original Assignee
Memc Electronic Materials
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Memc Electronic Materials filed Critical Memc Electronic Materials
Publication of TW201216414A publication Critical patent/TW201216414A/zh

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
TW100123193A 2010-06-30 2011-06-30 Methods for in-situ passivation of silicon-on-insulator wafers TW201216414A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US35999810P 2010-06-30 2010-06-30

Publications (1)

Publication Number Publication Date
TW201216414A true TW201216414A (en) 2012-04-16

Family

ID=44653366

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100123193A TW201216414A (en) 2010-06-30 2011-06-30 Methods for in-situ passivation of silicon-on-insulator wafers

Country Status (8)

Country Link
US (1) US8859393B2 (OSRAM)
EP (1) EP2589075A2 (OSRAM)
JP (1) JP5989642B2 (OSRAM)
KR (3) KR20190087668A (OSRAM)
CN (1) CN102959697A (OSRAM)
SG (1) SG186853A1 (OSRAM)
TW (1) TW201216414A (OSRAM)
WO (1) WO2012001659A2 (OSRAM)

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US8747598B2 (en) * 2012-04-25 2014-06-10 Gtat Corporation Method of forming a permanently supported lamina
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US9899499B2 (en) 2014-09-04 2018-02-20 Sunedison Semiconductor Limited (Uen201334164H) High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss
US9853133B2 (en) * 2014-09-04 2017-12-26 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity silicon-on-insulator substrate
WO2016081367A1 (en) 2014-11-18 2016-05-26 Sunedison Semiconductor Limited HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED BY He-N2 CO-IMPLANTATION
JP6726180B2 (ja) 2014-11-18 2020-07-22 グローバルウェーハズ カンパニー リミテッドGlobalWafers Co.,Ltd. 高抵抗率半導体・オン・インシュレータウエハおよび製造方法
EP3221884B1 (en) 2014-11-18 2022-06-01 GlobalWafers Co., Ltd. High resistivity semiconductor-on-insulator wafers with charge trapping layers and method of manufacturing thereof
US10283402B2 (en) 2015-03-03 2019-05-07 Globalwafers Co., Ltd. Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
US9881832B2 (en) 2015-03-17 2018-01-30 Sunedison Semiconductor Limited (Uen201334164H) Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof
US10290533B2 (en) 2015-03-17 2019-05-14 Globalwafers Co., Ltd. Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures
JP6592534B2 (ja) 2015-06-01 2019-10-16 サンエディソン・セミコンダクター・リミテッドSunEdison Semiconductor Limited 多層構造体及びその製造方法
JP6533309B2 (ja) 2015-06-01 2019-06-19 サンエディソン・セミコンダクター・リミテッドSunEdison Semiconductor Limited 多層構造体の製造方法
JP6749394B2 (ja) 2015-11-20 2020-09-02 グローバルウェーハズ カンパニー リミテッドGlobalWafers Co.,Ltd. 滑らかな半導体表面の製造方法
US10622247B2 (en) 2016-02-19 2020-04-14 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a buried high resistivity layer
US10468294B2 (en) 2016-02-19 2019-11-05 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface
US9831115B2 (en) 2016-02-19 2017-11-28 Sunedison Semiconductor Limited (Uen201334164H) Process flow for manufacturing semiconductor on insulator structures in parallel
EP3758050A1 (en) 2016-03-07 2020-12-30 GlobalWafers Co., Ltd. Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof
US11114332B2 (en) 2016-03-07 2021-09-07 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof
WO2017155804A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment
US10573550B2 (en) 2016-03-07 2020-02-25 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof
CN116314384A (zh) 2016-06-08 2023-06-23 环球晶圆股份有限公司 具有经改进的机械强度的高电阻率单晶硅锭及晶片
US10269617B2 (en) 2016-06-22 2019-04-23 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising an isolation region
WO2018080772A1 (en) 2016-10-26 2018-05-03 Sunedison Semiconductor Limited High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency
EP4009361B1 (en) 2016-12-05 2025-02-19 GlobalWafers Co., Ltd. High resistivity silicon-on-insulator structure
KR102306730B1 (ko) 2016-12-28 2021-09-30 썬에디슨 세미컨덕터 리미티드 고유 게터링 및 게이트 산화물 무결성 수율을 갖도록 규소 웨이퍼들을 처리하는 방법
FR3061988B1 (fr) * 2017-01-13 2019-11-01 Soitec Procede de lissage de surface d'un substrat semiconducteur sur isolant
EP3993018B1 (en) 2017-07-14 2024-09-11 Sunedison Semiconductor Limited Method of manufacture of a semiconductor on insulator structure
US10916416B2 (en) * 2017-11-14 2021-02-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor wafer with modified surface and fabrication method thereof
EP3785293B1 (en) 2018-04-27 2023-06-07 GlobalWafers Co., Ltd. Light assisted platelet formation facilitating layer transfer from a semiconductor donor substrate
JP7123182B2 (ja) 2018-06-08 2022-08-22 グローバルウェーハズ カンパニー リミテッド シリコン箔層の移転方法
US11296277B2 (en) 2018-10-16 2022-04-05 Samsung Electronics Co., Ltd. Variable resistance memory device having an anti-oxidation layer and a method of manufacturing the same

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Also Published As

Publication number Publication date
US8859393B2 (en) 2014-10-14
WO2012001659A2 (en) 2012-01-05
EP2589075A2 (en) 2013-05-08
KR20180037326A (ko) 2018-04-11
KR102083688B1 (ko) 2020-03-02
JP5989642B2 (ja) 2016-09-07
WO2012001659A3 (en) 2012-03-01
US20120003814A1 (en) 2012-01-05
KR20130129897A (ko) 2013-11-29
CN102959697A (zh) 2013-03-06
KR20190087668A (ko) 2019-07-24
SG186853A1 (en) 2013-02-28
JP2013534731A (ja) 2013-09-05

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