TW201132262A - Printed wiring board and method for manufacturing the same - Google Patents

Printed wiring board and method for manufacturing the same Download PDF

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Publication number
TW201132262A
TW201132262A TW099126679A TW99126679A TW201132262A TW 201132262 A TW201132262 A TW 201132262A TW 099126679 A TW099126679 A TW 099126679A TW 99126679 A TW99126679 A TW 99126679A TW 201132262 A TW201132262 A TW 201132262A
Authority
TW
Taiwan
Prior art keywords
layer
wiring board
printed wiring
via conductor
conductive layer
Prior art date
Application number
TW099126679A
Other languages
English (en)
Inventor
Masahiro Kaneko
Satoru Kose
Hirokazu Higashi
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Publication of TW201132262A publication Critical patent/TW201132262A/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

201132262 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種可較佳地在SSD或其類似物中使用以 安裝多個閃速記憶體的超薄印刷佈線板以及這種印刷佈線 板的製造方法。 本申請案主張2009年8月28曰申請之美國申請案第 61/237,808號之優先權。該美國申請案之全部内容以引用 之方式併入本文中。 【先前技術】 舉例而言，日本專利特許公開案2006·19433描述一種旨 在提供薄型佈線板之製造方法。在該製造方法中，在矽基 板上形成絕緣層，且在該絕緣層中形成通路導體（via conductor)。之後’在通路導體上形成佈線層，且在該佈 線層上安裝半導體元件，並利用樹脂封裝該半導體元件。 接著’藉由移除矽基板來獲得佈線板。本文中以引用之方 式併入包含該公開案之全部内容。 【發明内容】 根據本發明之一態樣，一種印刷佈線板包括：層間樹脂 絕緣層’其具有用於通路導體之貫穿孔；導電電路，其形 成於該層間樹脂絕緣層之一表面上；通路導體，其形成於 該貫穿孔中，且具有自該層間樹脂絕緣層之另一表面突出 的突出部分；及表面處理塗層，其形成於該通路導體之該 突出部分的表面上。該通路導體連接至該導電電路，且具 有形成於該貫穿孔的側壁上之第一導電層及填充該貫穿孔 J50085.doc 201132262 之鍍層。 根據本發明之另態樣，—種用於製造印刷佈線板之方 法包括：在支撲基板上形成可移除層；在該可移除層上形 成層間樹脂絕緣層；在該層間樹脂絕緣層中形成貫穿孔； 在該層間樹脂絕緣層上及該貫穿孔的側壁上形成第一導電 層；在該層間樹脂絕緣層上形成導電電路；在該貫穿孔令 形成通路導體；藉錢用該可移除層自該制樹脂絕緣層 移除該支樓基板；形成該通路導體之自該層間樹脂絕緣層 的表面突出之突出部分；及在該通路導體的該突出部分之 表面上形成表面處理塗層。 【實施方式】 藉由參考以下結合附圖所進行的詳細描述，隨著更佳理 解將容易地獲得對本發明之更完整評價以及本發明之許多 隨之而來的優點。 現將參考附圖描述該等實施例，其中貫穿各圖，相同參 考數字表示相應或相同元件。 第一實施例 參考圖1至圖9來描述根據本發明第一實施例之印刷佈線 板以及用於製造此種印刷佈線板之方法。 圖7為展示印刷佈線板10之部分的橫截面圖。在印刷佈 線板10中，安裝有藉由層壓多片記憶體（10〇Α、ιοοΒ、 100C)所製成的記憶體層壓體（memory laminate)100。記憶 體層壓體100藉由黏接層110固定至印刷佈線板10。舉例而 言’記憶體層壓體100之各記憶體藉由電線106彼此連接。 150085.doc 201132262 該等記憶體亦可經由藉由喷墨所形成的佈線而彼此連接。 印刷佈線板10具有第一層間樹脂絕緣層40與第二層間樹 脂絕緣層60之雙層結構《在第一層間樹脂絕緣層40中所形 成的開口 42中，形成通路導體50。在第一層間樹脂絕緣層 上，形成導電電路52及通路焊盤（via land)5 1。在第二層間 樹脂絕緣層60中形成開口 62，且在開口 62中形成表面處理 塗層70 ^印刷佈線板1〇及記憶體層壓體1〇〇藉由橫跨於印 刷佈線板10的表面處理塗層70及記憶體層壓體1〇〇的焊塾 102之間的電線1〇6相連接。在通路導體50之下表面側（第 一表面侧）上，形成外部連接用的表面處理塗層80以具有 使得能夠進行電線接合（wire bonding)之結構。利用成型樹 脂120來封裝記憶體層壓體1〇〇。 圖9C展示圍繞圖7之通路導體50的區域的放大圖。通路 導體50上之表面處理塗層70形成有填充在第二層間樹脂絕 緣層60的開口 62中之鍍鎳（Ni)層64、鍍鎳層64上的鈀（Pd) 膜66以及le膜66上的金（Au)膜68。金膜68係為了防止導電 電路之腐蝕並使得由金線製成之電線106容易進行接合的 目的而塗佈。 在第一層間樹脂絕緣層40中之開口 42的側壁上.，按次序 形成氮化鈦（TiN)濺鍍膜（44a)(第一導電層）、鈦（Ti)濺鍍膜 (44b)(第一導電層）及銅（Cu)濺鍍膜（44c)(第二導電層）。亦 即’通路導體50形成有氮化欽j賤錢膜（44a)、鈦賤鍵膜 (44b)、銅濺锻膜（44c)以及形成於鋼滅鑛膜（44c)内側上之 電解鍍銅膜48。自通路導體50之下表面側（第一表面側）移 150085.doc 201132262 除SL化鈇濺鍍膜（44a)及鈦濺鍍膜 、 胰（44b) ’且在銅濺鍍膜 (44c)之表面上形成表面處理塗層 表面處理塗層80形成 有在通路導體50之第一表面上开彡忐认μ 衣®上形成的鎳膜82、鎳膜82上之 le«膜84以及纪膜84上的金膜86。 每一層之膜厚展示於圖l〇A中。笛 „ 第—層間樹脂絕緣層及 第二層間樹脂絕緣層形成為約3 歷 X 1J J μπι厚。形成表面處理塗層 7 0之艘鎳層形成為約1 〇 厚。鐘錄恳μ — a 锻螺層上之鈀膜形成為約 〇.〇5叫，且㈣上之金膜形成為約〇3_。同時，通路導 體開口之側壁上形成的銅濺鍍膜形成為約i〇〇 nm，鈦錢鍍 膜形成為約35 nm，且氮化鈦濺鍍膜形成為約i5 nm。形成 表面處理塗層8 0下錦賤鍵層形成*的& 曰〜驭馮約6 μηι，鈀層形成為約 0.0 5 μιη，且金層形成為約〇. 3 。 如上所述，自通路導體λ 之下表面側移除鈦濺鍍膜 (44b)及氮化鈦濺鍍膜（44a)，且銅濺鍍膜（44c)之表面自第 一層間樹脂絕緣層40之第二表面突出了距離d(5〇 參見 圖 10Β)。 在根據第一貫施例之印刷佈線板中，由於通路導體5 〇之 底面自第一層間樹脂絕緣層40之底面突出了 d(5〇 μιη)，因 此可利用在通路導體50上形成之表面處理塗層8〇達成錨固 效果’且改良了通路導體5 〇與表面處理塗層8 〇之間的黏附 性。 本文中’當用於形成表面處理塗層80之基底（通路導體 5〇之第一表面側）為濺鍍膜時，此膜由於其細結晶（fine crystamzation)而展現障壁功能，且抑制形成通路導體的 150085.doc 201132262 銅離子擴散至表面處理塗層80中。因此，確保了表面處理 塗層80之黏合強度。然而，即使藉由電解電鍍所形成之表 面處理塗層8〇與濺鍍膜(鋼減鍍膜(44。))係由相同金屬製 成’其結晶結構亦不同。另夕卜，由於與鑛膜相比較，賤鍍 膜(銅滅鑛膜(44C))具有平坦表面，因此，例如在電線接合 時或田在模組中產生熱時，可能自通路導體％移除表面處 理塗層80 〇因此，為太眘&友丨+ ^ 在本實施例中，使通路導體50之第一表 面侧自第-層間樹脂絕緣層4〇之第二表面突出。因此，即 使用於形成表面處理塗層8〇之基底（通路導體5〇之第一表 面側）為濺鍍膜，亦可確保通路導體5〇與表面處理塗層8〇 之間的黏附性。 以下描述用於製造根據第一實施例的印刷佈線板之方 法。 首先，在圖1A所示之支撐基板3〇上，層壓3 μηι厚之熱 塑性樹月Θ(ΗΤ250’ 由 Nissan Chemical Industries，Ltd.製 造）32(圖IB)。接著，在熱塑性樹脂32上層壓4 厚之層 間樹脂絕緣層（商標名：WPR，由JSR公司製造）4〇(圖1C)。 使用光微影技術，在預定部位形成直徑約為2〇〇 μπι之通 路開口 42(圖2Α)。在層間樹脂絕緣層4〇之包括通路開口 42 的内部之表面上，藉由濺鍍形成三層遮擋層44(圖2Β)。藉 由參考圖8Α中之開口 42的放大圖，進一步詳細描述該遮擋 層之結構。遮擋層44由氮化鈦減鍵膜（44a)、欽錢鍵膜 (44b)及銅濺鍍膜（44c)構成。由於係藉由濺鍍形成氮化鈦 濺鍍膜（44a)、鈦濺鍍膜（44b)及銅濺鍍膜（44c)，因此該等 150085.doc 201132262 膜各自平而薄，且彼此高度黏合。 藉由在塗佈有遮擋層44之層間樹脂絕緣層4〇上塗覆市售 抗钱劑，接著藉由進行曝光及顯影，形成具有預定圖案之 抗鍍層（plating resist)46(圖2C)。接著，藉由執行電解電 鍵，在未形成抗鑛層之區域上形成電解鑛銅膜48(圖3 A)。 此處’由於亦使用銅在銅錢鍍膜（44c)上形成電解鍵銅嫉 48 ’因此遮擋層44與電解鍍銅膜48之間的黏附性高。藉由 移除抗鍍層（圖3B)，且藉由使用快速姓刻移除位於抗鍵層 下方的遮擋層44，在開口 42中形成通路導體5〇，且在層間 樹脂絕緣層40上形成導電電路52及通路焊盤5丨（圖3C)。當 形成兩個或兩個以上的佈線層時，通路導體5〇較佳為經填 充通路。藉由將通路導體50形成為經填充通路，通路導體 50之表面變得實質上平坦。在印刷佈線板具有多層佈線結 構之情況下，有可能將通路導體直接配置在通路導體5〇 上。因而’可達成高度整合之佈線。 在具有導電電路52之第一層間樹脂絕緣層4〇上，層壓4终爪 厚的層間樹脂絕緣層（商標名：WPR，由jsr公司製 造）60(圖3D)。使用光微影技術，在預定通路導體上形成 直徑為200 μιΏ之開口 62(圖4A)。接著，在經由開口 62而暴 露之通路導體50上，藉由無電極電鍍按次序形成鍍鎳層 64、鑛鈀層66及鏡金層68(圖4Β)。 在層間樹脂絕緣層60上，利用黏接層！ 1〇來安裝藉由層 壓記憶體（100Α、10犯及100〇所製成之記憶體層壓體 ，且使用電線106來連接記憶體層壓體1〇〇之焊墊1〇2與 150085.doc 201132262 表面處理塗層70(通路導體50)(圖4C)。 由成型樹脂120封裝層間樹脂絕緣層60及記憶體層壓體 100(圖5A)。之後，加熱且藉由使用熱塑性樹脂32滑動支 撐基板30來移除支撐基板30(圖5B)。圖8B展示移除支撐基 板30之後通路導體50的放大圖。藉由灰化（ashing)移除熱 塑性樹脂32(圖6A以及為圖6A的放大圖之圖8C)。使用含有 KOH之的蝕刻劑進行蝕刻，以移除經由層間樹脂絕緣層4〇 中的開口 42而暴露的鈦濺鍍膜（44b)及氮化鈦濺鍍膜 (44a)。此處，鈦容易被K〇h溶解，但銅難以溶解。圖9A 展示在移除經由開口 42而暴露的鈦濺鍍膜（44b)及氮化鈦濺 鍍膜（44a)之後通路導體50的放大圖。 接著’藉由喷砂對第一層間樹脂絕緣層4〇之表面進行拋 光’以使厚度減小d(50 μπι)(圖6B以及為圖6B的放大圖之 圖9Β)。如以上參考圖1〇Β所述，銅濺鍍膜（44c)之表面自 第一層間樹脂絕緣層40之第二表面突出距離d(5〇 μιη)。 接著，在藉由無電極電鍍於位於通路導體5〇底部上的銅 濺鍍膜44c上形成鎳膜82之後，藉由無電極電鍍按次序形 成鈀膜84及金膜86，且形成表面處理塗層8〇(圖7)。圖冗 展示圖7中的表面處理塗層8〇之放大圖。 利用電線或焊料凸塊將如上製造出的半導體裝置安裝在 主機板上《此處，可層壓多個該種半導體裝置，且接著將 其安裳在主機板上。在進行此操作之過程中，例如，當將 16層s己憶體安裝在主機板上時，僅使用藉由將々層記憶體 安裝在如上之印刷佈線板上所獲得的良好半導體裝置係可 I50085.doc 201132262 行的，且將提高生產率。 第二實施例 參考圖11至圖14來描述根據本發明第二實施例之印刷佈 線板及製造該種印刷佈線板之方法。 圖12為展示印刷佈線板1〇之部分的橫載面圖。第二實施 例之印刷佈線板10構造成與以上藉由參考圖7所述的第一 實施例中之印刷佈線板相同。然而，在第一實施例中，將 二個層（銅濺鍍膜（44c)、鈦濺鍍膜（44b)及氮化鈦濺鍍膜 (44a))形成於層間樹脂絕緣層4〇中的開口 42之側壁上。相 比之下，在第二實施例中’如為圖12中的通路導體5〇之放 大圖的圖14C所示，採用如下的雙層結構：由氮化鈦濺鍍 膜（44a)(第一導電層）及銅濺鍍膜（44c)(第二導電層）構成的 兩層形成於開口 42之側壁上》 在第一貫施例之印刷佈線板中’由於通路導體5 〇之底面 自第一層間樹脂絕緣層40之第二表面突出了 5〇 ， 因此可利用形成於通路導體50上之表面處理塗層8〇來達成 錫固效果’且改良了通路導體5〇與表面處理塗層8〇之間的 黏附性。 ， 以下描述用於製造第二實施例的印刷佈線板之方法。 如以上藉由參考圖i至圖2A所述，在矽基板30上形成熱 塑性樹脂32 ’且在熱塑性樹脂32上層壓層間樹脂絕緣層 40(圖ΠΑ)。在預定部位形成直徑為200 μιη之通路開口 42(圖11Β)。在層間樹脂絕緣層40的包括通路開口 42的内 部之表面上，藉由濺鍍形成雙層遮擋層44(圖11 藉由 150085.doc • 11 - 201132262 參考圖13A所示之開口 42之放大圖，進一步詳細描述該遮 擋層之結構。遮擋層40由氮化鈦濺鍍膜（44a)及銅濺鍍膜 (44c)構成。 接下來’形成與以上藉由參考圖2C至圖5B所述之第一 實施例中的印刷佈線板相同之印刷佈線板，且由成型樹脂 120封裝層間樹脂絕緣層60及記憶體層壓體1〇〇。之後，加 熱’且使用熱塑性樹脂32移除矽基板30(圖13B)，且接著 藉由灰化移除熱塑性樹脂32(圖13C)。使用KOH進行触 刻’以移除經由層間樹脂絕緣層4〇中的開口 42而暴露之氮 化鈦濺鑛膜（44a)(圖ΜΑ)。 藉由喷砂對第一層間樹脂絕緣層4〇之表面進行拋光，以 使厚度減小d2(5 0 μιη)(圖14Β)。如以上參考圖14C所述， 銅濺鍍膜（44c)之表面自第一層間樹脂絕緣層4〇之第二表面 突出了距離d(50 μιη)。 接著，在位於通路導體50底部上之銅濺鍍膜（44c)上，藉 由濺鍍形成鎳膜82。之後，藉由利用無電極電鍍塗佈鈀膜 84及金膜86，形成由鎳膜82、鈀膜84及金膜86構成的表面 處理塗層80(圖12)。圖14C展示圖12中之表面處理塗層8〇 之放大圖。 第三實施例 參考圖15來描述用於製造根據第三實施例之印刷佈線板 之方法。 在第一實施例中，在移除熱塑性樹脂之後，進行蝕刻以 移除經由層間樹脂絕緣層40中的開口42而暴露之鈦濺鍍膜 150085.doc •12- 201132262 (44b)及氮化鈦濺鍍膜（44a)。接著，藉由噴砂對第一層間 樹脂絕緣層4 0之表面進行拋光。相比之下，在第三實施例 中，在如第一實施例中之圖8C所示移除熱塑性樹脂之後， 藉由喷砂對第一層間樹脂絕緣層40之表面進行拋光（圖 1 5 A)。之後，移除經由層間樹脂絕緣層4〇中之開口 42而暴 露的鈦濺鍍膜（44b)及氮化鈦濺鍍膜（44a)(圖15B)。 接著，在位於通路導體5〇底部上的銅濺錄膜（44c)上藉由 無電極電鍍形成鎳膜82之後’藉由無電極電鍍按次序形成 鈀膜84及金膜86’且形成表面處理塗層8〇(圖15(：：)。 在第二貫施例中’如圖1 5B所示’在開口 42與銅濺锻膜 (44c)之間，移除鈦賤鍵膜（44b)及氮化鈦濺鑛膜（44a)直至 内部部分，且如圖15C所示，表面處理塗層8〇之鎳膜82進 入藉由-亥移除所形成之空間。因此，可增強通路導體與 表面處理塗層80之間的黏附性。 第四實施例 在第四實施例中，使用無電極電鍍銅膜作為第一導電 層亦即’通路導體5〇由形成於層間樹脂絕緣層之側壁 上的無電極電鍍銅膜以及填充在開口 42中之電解電鍍膜組 成。此處’例如’在移除通路導體之下側（第一表面側）上 的無電極電鍍鋼骐時，作為選項可考慮喷塗蝕刻劑。然 :二移除方法並無具體限制。在本實施例中，可達成與第 貫知例中的功成及效果相同之功能及效果。 第五實施例 第實把例中，使用非感光性層間樹脂絕緣層。在該 150085.doc 201132262 情況下’藉由雷射形成通路導體開口。在此期間，較佳形 成開口直至位於層間樹脂絕緣層下方的移除層之中間為 止。在進行此操作之過程中，當藉由在開口内部形成通路 導體來形成佈線層之後移除支撐基板時，與第一實施例中 相同’通路導體之第一表面將自層間樹脂絕緣層之第二表 面突出。在第五實施例中，亦可達成與上述第一實施例之 效果相同之效果。 在經由貫穿孔暴露的通路導體之表面上形成有表面處理 塗層的印刷佈線板中，通路導體形成有自層間樹脂絕緣層 之一表面突出之表面’可藉由形成於通路導體之該表面上 的表面處理塗層達成錨固效果，且改良了通路導體與表面 處理塗層之間的黏附性《通路導體可由形成於貫穿孔側壁 上之第一導電層及填充貫穿孔之鍍層組成。 顯而易見，根據以上教示’本發明之許多修改及變化係 可能的。因此，應理解’在所附申請專利範圍之範疇内， 可以不同於本文中所具體描述之方式來實踐本發明。 【圖式簡單說明】 圖1(A)至圖1(C)為用於製造根據本發明第一實施例之印 刷佈線板的步驟之視圖； 圖2(A)至圖2(C)為用於製造根據第一實施例之印刷佈線 板的步驟之視圖； 圖3(A)至圖3(D)為用於製造根據第一實施例之印刷佈線 板的步驟之視圖； 圖4(A)至圖4(C)為用於製造根據第一實施例之印刷佈線 150085.doc -14- 201132262 板的步驟之視圖； 圖5(A)、圖5(B)為用於製造根據第一實施例之印刷佈線 板的步驟之視圖； 圖6(A)、圖6(B)為用於製造根據第一實施例之印刷佈線 板的步驟之視圖： 圖7為展示第一實施例之印刷佈線板的橫截面圖； 圖8(A)至圖8(C)為展示第一實施例之印刷佈線板的橫截 面圖； 圖9(A)至圖9(C)為藉由放大第一實施例之印刷佈線板中 的通路導體及凸塊（bump)所展示的製造步驟之視圖； 圖10(A)、圖l〇(B)為說明第一實施例之印刷佈線板中的 通路導體之視圖； 圖11(A)至圖11(c)為用於製造根據本發明第二實施例之 印刷佈線板的步驟之視圖； 圖12為展示第二實施例之印刷佈線板的橫截面圖； 圖13(A)至圖13(C)為展示第二實施例之印刷佈線板的橫 截面圖； 圖14(A)至圖14(C)為藉由放大第二實施例之印刷佈線板 中的通路導體及凸塊所展示的製造步驟之視圖；及 圖15(A)至圖15(C)為藉由放大第三實施例之印刷佈線板 中的通路導體及凸塊所展示的製造步驟之視圖。 【主要元件符號說明】 10 印刷佈線板 30 支撐基板 150085.doc 201132262 32 熱塑性樹脂 40 第一層間樹脂絕緣層 42 開口 44 遮擋層 44a 氮化鈦（TiN)濺鍍膜 44b 鈦（Ti)濺鍍膜 44c 銅（Cu)濺鍍膜 46 抗鍍層 48 電解鍍銅膜 50 通路導體 51 通路焊盤 52 導電電路 60 第二層間樹脂絕緣層 62 開口 64 鍍鎳（Ni)層 66 鈀（Pd)膜 68 金（Au)膜 70 表面處理塗層 80 表面處理塗層 82 鎳膜 84 鈀膜 86 金膜 100 記憶體層壓體 100A 記憶體 150085.doc -16- 201132262 100B 記憶體 100C 記憶體 102 焊墊 106 電線 110 黏接層 120 成型樹脂 150085.doc • 17

Claims (1)

  1. 201132262 七、申請專利範圍： 1. 一種印刷佈線板，其包含： 一層間樹脂絕緣層，其具有一第一表面及一位於該第 一表面之一相對側之第二表面，該層間樹脂絕緣層具有 用於一通路導體（via conductor)之貫穿孔（penetrating hole)； 一導電電路，其形成於該層間樹脂絕緣層之該第一表 面上； 一通路導體，其形成於該貫穿孔中，且具有一自該層 間樹脂絕緣層之該第二表面突出的突出部分；及 一表面處理塗層’其形成於該通路導體之該突出部分 之一表面上， 其中該通路導體連接至該導電電路，且包含一形成於 该貫穿孔之一側壁上的第一導電層及一填充該貫穿孔之 鑛層。 2·如請求項1之印刷佈線板，其中該通路導體具有一位於 該第一導電層與該鍍層之間的第二導電層。 3.如明求項2之印刷佈線板，其中該第二導電層係形成於 ' 該鍍層與該表面處理塗層之間。 . 4.如凊求項2之印刷佈線板，其中該第二導電層與該鍍層 係由相同金屬製成。 5. 如請求項2之印刷佈線板，其中該第二導電層及該鍍層 係由銅製成。 6. 如凊求項1之印刷佈線板，其中該貫穿孔之該側壁上的 150085.doc 201132262 該第一導電層自該通路導體之該突出部分凹入。 7. 如請求項2之印刷佈線板，其中該第一導電層具有一比 該第二導電層之厚度大之厚度。 8. 如請求項2之印刷佈線板，其中該第一導電層及該第二 導電層係藉由濺鍍形成。 9. 如請求項1之印刷佈線板，其中該表面處理塗層經形成 以塗佈該貫穿孔之一周邊部分。 10·如請求項1之印刷佈線板，其中該第一導電層係由一形 成於該層間樹脂絕緣層上之氮化鈦膜及一位於該氮化鈦 膜上之鈦膜組成。 11· 一種用於製造一印刷佈線板之方法，其包含： 在一支撐基板上形成一可移除層； 在該可移除層上形成一層間樹脂絕緣層； 在該層間樹脂絕緣層中形成一貫穿孔； 在該層間樹脂絕緣層上及該貫穿孔之一側壁上形成一 第一導電層； 在該層間樹脂絕緣層上形成一導電電路； 在該貫穿孔中形成一通路導體； 藉由使用該可移除層而自該層間樹脂絕緣層移除該支 撐基板； 形成該通路導體之自該層間樹脂絕緣層之一表面突出 之一突出部分；及 在該通路導體之該突出部分之一表面上形成一表面處 理塗層。 150085.doc -2- 201132262 12.如請求項11之用於製造一印刷佈線板之方法，其中該通 路導體之該突出部分之該形成包含：減小該層間樹脂絕 緣層之厚度。 13 ·如請求項11之用於製造一印刷佈線板之方法，其中該通 路導體之該形成包含：在該貫穿孔中之該第一導電層上 形成一第二導電層。 14.如請求項11之用於製造一印刷佈線板之方法，其中該通 路導體之該形成包含：在該貫穿孔中之該第一導電層上 形成一第二導電層，並在該第二導電層上形成一金屬鑛 層’且該第二導電層與該鍍層係由相同金屬製成。 15_如請求項11之用於製造一印刷佈線板之方法，其中該通 路導體之該形成包含：在該貫穿孔中之該第一導電層上 形成一第二導電層，並在該第二導電層上形成一金屬鍍 層，且該第二導電層及該鍍層係由銅製成。 16. 如請求項丨丨之用於製造一印刷佈線板之方法，其中該通 路導體之該突出部分之該形成包含：在該表面處理塗層 之該形成之前，移除該第一導電層之自該層間樹脂絕缘 層之該表面突出之一部分。 17. 如請求項11之用於製造一印刷佈線板之方法，其中該可 移除層係由一熱塑性樹脂製成。 18. 如請求項η之用於製造一印刷佈線板之方法，其中該第 一導電層之該形成包含：濺鍍一氮化鈦膜，並在該氮化 鈦膜於該層間樹脂絕緣層上之該濺鍍之後濺鍍一鈦膜。 19 _如响求項11之用於製造一印刷佈線板之方法，其中同時 150085.doc 201132262 形成該導電電路與該通路導體。 20.如請求項19之用於製造一印刷佈線板之方法，其中該導 電電路之該形成及該通路導體之該形成包含藉由一半加 成（semi-additive)法來實行。 150085.doc
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US9320153B2 (en) 2016-04-19
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