CN102005434B - 印刷线路板及其制造方法 - Google Patents

印刷线路板及其制造方法 Download PDF

Info

Publication number
CN102005434B
CN102005434B CN2010102690380A CN201010269038A CN102005434B CN 102005434 B CN102005434 B CN 102005434B CN 2010102690380 A CN2010102690380 A CN 2010102690380A CN 201010269038 A CN201010269038 A CN 201010269038A CN 102005434 B CN102005434 B CN 102005434B
Authority
CN
China
Prior art keywords
conductive layer
via conductor
printed substrate
insulating layers
interlayer resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2010102690380A
Other languages
English (en)
Other versions
CN102005434A (zh
Inventor
金子昌弘
小濑觉
东广和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Publication of CN102005434A publication Critical patent/CN102005434A/zh
Application granted granted Critical
Publication of CN102005434B publication Critical patent/CN102005434B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0344—Electroless sublayer, e.g. Ni, Co, Cd or Ag; Transferred electroless sublayer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H05K2201/09527—Inverse blind vias, i.e. bottoms outwards in multilayer PCB; Blind vias in centre of PCB having opposed bottoms
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/072—Electroless plating, e.g. finish plating or initial plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1377—Protective layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

本发明涉及印刷线路板及其制造方法。该印刷线路板包括：层间树脂绝缘层，其具有通路导体用的贯通孔；导电电路，其形成在所述层间树脂绝缘层的一个表面上；通路导体，其形成于所述贯通孔中，并且具有相对于所述层间树脂绝缘层的另一表面而突出的突出部；以及表面处理涂布物，其形成在所述通路导体的所述突出部的表面上。该通路导体连接至导电电路，并且具有形成在贯通孔的侧壁上的第一导电层以及填充该贯通孔的镀层。

Description

印刷线路板及其制造方法
技术领域
本发明涉及一种可优选在SSD等中使用以安装多个闪速存储器的超薄印刷线路板以及这种印刷线路板的制造方法。
背景技术
例如，日本特开2006-19433号公报说明了一种目的在于提供薄型线路板的制造方法。在该制造方法中，在硅基板上形成绝缘层，并且在该绝缘层中形成通路导体(via conductor)。之后，在通路导体上形成布线层，并且在该布线层上安装半导体元件，并利用树脂封装该半导体元件。然后，通过去除硅基板来获得线路板。这里通过引用包含该公报的全部内容。
发明内容
根据本发明的一个方面，一种印刷线路板包括：层间树脂绝缘层，其具有通路导体用的贯通孔；导电电路，其形成在所述层间树脂绝缘层的一个表面上；通路导体，其形成于所述贯通孔中，并且具有相对于所述层间树脂绝缘层的另一表面而突出的突出部；以及表面处理涂布物，其形成在所述通路导体的所述突出部的表面上。该通路导体连接至所述导电电路，并且具有形成在所述贯通孔的侧壁上的第一导电层以及填充所述贯通孔的镀层。
根据本发明的另一方面，一种印刷线路板的制造方法包括：在支撑基板上形成可去除层；在所述可去除层上形成层间树脂绝缘层；在所述层间树脂绝缘层中形成贯通孔；在所述层间树脂绝缘层上和所述贯通孔的侧壁上形成第一导电层；在所述层间树脂绝缘层上形成导电电路；在所述贯通孔中形成通路导体；通过使用所述可去除层从所述层间树脂绝缘层去除所述支撑基板；形成所述通路导体相对于所述层间树脂绝缘层的表面而突出的突出部；以及在所述通路导体的所述突出部的表面上形成表面处理涂布物。
附图说明
通过参考以下结合附图所进行的详细说明，随着理解的深入能够容易地获得对本发明更完整的评价以及本发明许多随之而来的优点，其中：
图1是用于制造根据本发明第一实施例的印刷线路板的步骤的图；
图2是用于制造根据第一实施例的印刷线路板的步骤的图；
图3是用于制造根据第一实施例的印刷线路板的步骤的图；
图4是用于制造根据第一实施例的印刷线路板的步骤的图；
图5是用于制造根据第一实施例的印刷线路板的步骤的图；
图6是用于制造根据第一实施例的印刷线路板的步骤的图；
图7是示出第一实施例的印刷线路板的断面图；
图8是示出第一实施例的印刷线路板的断面图；
图9是通过放大第一实施例的印刷线路板中的通路导体和凸块(bump)所示出的制造步骤的图；
图10是示出第一实施例的印刷线路板中的通路导体的图；
图11是用于制造根据本发明第二实施例的印刷线路板的步骤的图；
图12是示出第二实施例的印刷线路板的断面图；
图13是示出第二实施例的印刷线路板的断面图；
图14是通过放大第二实施例的印刷线路板中的通路导体和凸块所示出的制造步骤的图；以及
图15是通过放大第三实施例的印刷线路板中的通路导体和凸块所示出的制造步骤的图。
具体实施方式
现在将参考附图说明这些实施例，其中，在各附图中，相同的附图标记表示相应或相同的元件。
第一实施例
参考图1～图9来说明根据本发明第一实施例的印刷线路板以及这种印刷线路板的制造方法。
图7是示出印刷线路板10的一部分的断面图。在印刷线路板10中，安装有通过层压多片存储器(100A、100B、100C)所制成的存储器层压体(memory laminate)100。存储器层压体100利用粘合层110固定至印刷线路板10。例如，存储器层压体100的各存储器通过引线106彼此连接。这些存储器还可以经由通过喷墨所形成的布线彼此连接。
印刷线路板10具有第一层间树脂绝缘层40和第二层间树脂绝缘层60的双层结构。在第一层间树脂绝缘层40中所形成的开口42中，形成通路导体50。在第一层间树脂绝缘层上，形成导电电路52和通路连接层(via land)51。在第二层间树脂绝缘层60中形成开口62，并且在开口62中形成表面处理涂布物70。印刷线路板10和存储器层压体100通过横跨印刷线路板10的表面处理涂布物70和存储器层压体100的焊盘102之间的引线106相连接。在通路导体50的下表面侧(第一表面侧)，形成外部连接用的表面处理涂布物80以具有能够进行引线接合(wire bonding)的结构。利用成型树脂120来封装存储器层压体100。
图9的(C)示出图7的通路导体50周围的区域的放大图。通路导体50上的表面处理涂布物70形成有填充在第二层间树脂绝缘层60的开口62中的镀镍(Ni)层64、镀镍层64上的钯(Pd)膜66以及钯膜66上的金(Au)膜68。为了防止导电电路的腐蚀并使得由金线制成的引线106容易进行接合的目的而涂布金膜68。
在第一层间树脂绝缘层40中的开口42的侧壁上，按顺序依次形成氮化钛(TiN)溅射膜44a(第一导电层)、钛(Ti)溅射膜44b(第一导电层)和铜(Cu)溅射膜44c(第二导电层)。即，通路导体50形成有氮化钛溅射膜44a、钛溅射膜44b、铜溅射膜44c以及形成在铜溅射膜44c的内侧上的电解镀铜膜48。从通路导体50的下表面侧(第一表面侧)去除氮化钛溅射膜44a和钛溅射膜44b，并且在铜溅射膜44c的表面上形成表面处理涂布物80。表面处理涂布物80形成有在通路导体50的第一表面上形成的镍膜82、镍膜82上的钯膜84以及钯膜84上的金膜86。
各层的膜厚如图10的(A)所示。第一层间树脂绝缘层和第二层间树脂绝缘层被形成为约3μm厚。形成表面处理涂布物70的镀镍层被形成为约10μm厚。镀镍层上的钯膜被形成为约0.05μm，并且钯膜上的金膜被形成为约0.3μm。同时，通路导体开口的侧壁上形成的铜溅射膜被形成为约100nm，钛溅射膜被形成为约35nm，并且氮化钛溅射膜被形成为约15nm。形成表面处理涂布物80的镍溅射层被形成为约6μm，钯层被形成为约0.05μm，并且金层被形成为约0.3μm。
如上所述，从通路导体50的下表面侧去除钛溅射膜44b和氮化钛溅射膜44a，并且铜溅射膜44c的表面相对于第一层间树脂绝缘层40的第二表面突出了距离d(50μm)(参见图10的(B))。
在根据第一实施例的印刷线路板中，由于通路导体50的下表面相对于第一层间树脂绝缘层40的下表面突出了d(50μm)，因此利用在通路导体50上形成的表面处理涂布物80来实现锚固效果，并且提高了通路导体50和表面处理涂布物80之间的粘合性。
这里，当用于形成表面处理涂布物80的基体(通路导体50的第一表面侧)是溅射膜时，这种膜由于其细结晶(finecrystallization)而展现出阻挡作用(barrier function)，并且抑制形成通路导体的铜离子扩散到表面处理涂布物80中。因此，确保了表面处理涂布物80的粘合强度。然而，即使通过电解电镀所形成的表面处理涂布物80由与溅射膜(铜溅射膜44c)相同的金属制成，它们的结晶结构也不相同。另外，由于与镀膜相比较，溅射膜(铜溅射膜44c)具有平坦表面，因此，例如在引线接合时或当在模块中生成热时，可以从通路导体50去除表面处理涂布物80。因此，在本实施例中，使通路导体50的第一表面侧相对于第一层间树脂绝缘层40的第二表面突出。因此，即使用于形成表面处理涂布物80的基体(通路导体50的第一表面侧)是溅射膜，也确保了通路导体50和表面处理涂布物80之间的粘合性。
以下说明用于制造根据第一实施例的印刷线路板的方法。
首先，在图1的(A)所示的支撑基板30上，层压3μm厚的热塑性树脂(HT250，由Nissan Chemical Industries，Ltd.制造)32(图1的(B))。然后，在热塑性树脂32上层压4μm厚的层间树脂绝缘层(商品名：WPR，由JSR Corp.制造)40(图1的(C))。
使用光刻技术，在预定部位形成直径约为200μm的通路开口42(图2的(A))。在层间树脂绝缘层40的包括通路开口42的内部的表面上，通过溅射形成三层遮挡层44(图2的(B))。通过参考图8的(A)中的开口42的放大图，进一步详细说明这种遮挡层的结构。遮挡层44由氮化钛溅射膜44a、钛溅射膜44b和铜溅射膜44c构成。由于通过溅射形成氮化钛溅射膜44a、钛溅射膜44b和铜溅射膜44c，因此这些膜均平而薄，并且彼此高度粘合。
通过在涂布有遮挡层44的层间树脂绝缘层40上施加市场上可获得的抗蚀剂，然后通过进行曝光和显影，形成具有预定图案的抗镀层(plating resist)46(图2的(C))。然后，通过进行电解电镀，在没有形成抗镀层的区域上形成电解镀铜膜48(图3的(A))。这里，由于同样使用铜在铜溅射膜44c上形成电解镀铜膜48，因此遮挡层44和电解镀铜膜48之间的粘合性高。通过去除抗镀层(图3的(B))，并且通过使用快速蚀刻去除位于抗镀层下方的遮挡层44，在开口42中形成通路导体50，并且在层间树脂绝缘层40上形成导电电路52和通路连接层51(图3的(C))。当形成两个以上的布线层时，通路导体50优选为填充的通路。通过将通路导体50形成为填充的通路，通路导体50的表面变得大致平坦。在印刷线路板具有多层布线结构的情况下，可以将通路导体直接布置在通路导体50上。因而，可以实现高度集成的布线。
在具有导电电路52的第一层间树脂绝缘层40上，层压4μm厚的层间树脂绝缘层(商品名：WPR，由JSR Corp.制造)60(图3的(D))。使用光刻技术，在预定的通路导体上形成直径为200μm的开口62(图4的(A))。然后，在经由开口62而暴露的通路导体50上，通过无电电镀(electroless plating)，按顺序依次形成镀镍层64、镀钯层66和镀金层68(图4的(B))。
在层间树脂绝缘层60上，利用粘合层110来安装通过层压存储器(100A、100B和100C)所构成的存储器层压体100，并且使用引线106来连接存储器层压体100的焊盘102和表面处理涂布物70(通路导体50)(图4的(C))。
由成型树脂120封装层间树脂绝缘层60和存储器层压体100(图5的(A))。之后，进行加热，并且通过使用热塑性树脂32滑动支撑基板30来去除该支撑基板30(图5的(B))。图8的(B)示出支撑基板30被去除之后通路导体50的放大图。通过抛光(ashing)去除热塑性树脂32(图6的(A)以及作为图6的(A)的放大图的图8的(C))。使用包含氢氧化钾(K0H)的蚀刻剂进行蚀刻，以去除经由层间树脂绝缘层40中的开口42而暴露的钛溅射膜44b和氮化钛溅射膜44a。这里，钛容易被氢氧化钾溶解，但铜难以溶解。图9的(A)示出在去除了经由开口42而暴露的钛溅射膜44b和氮化钛溅射膜44a之后通路导体50的放大图。
然后，通过喷砂(sandblasting)对第一层间树脂绝缘层40的表面进行研磨，以使厚度减小了d(50μm)(图6的(B)以及作为图6的(B)的放大图的图9的(B))。如以上参考图10的(B)所述，铜溅射膜44c的表面相对于第一层间树脂绝缘层40的第二表面突出了距离d(50μm)。
然后，在位于通路导体50的底部的铜溅射膜44c上通过无电电镀形成镍膜82之后，通过无电电镀按顺序依次形成钯膜84和金膜86，并且形成表面处理涂布物80(图7)。图9的(C)示出图7中的表面处理涂布物80的放大图。
利用引线或焊料凸块将如上制造出的半导体设备安装在母板上。这里，可以层压多个这种半导体设备，然后将这些半导体设备安装在母板上。这样，例如，当将16层存储器安装在母板上时，仅使用通过将4层存储器安装在如上的印刷线路板上所获得的好半导体设备是可行的，并且将提高生产率。
第二实施例
参考图11～14来说明根据本发明第二实施例的印刷线路板以及这种印刷线路板的制造方法。
图12是示出印刷线路板10的一部分的断面图。第二实施例的印刷线路板10被构造成与以上通过参考图7所述的第一实施例中的印刷线路板相同。然而，在第一实施例中，将铜溅射膜44c、钛溅射膜44b和氮化钛溅射膜44a这三层形成在层间树脂绝缘层40中的开口42的侧壁上。相比之下，在第二实施例中，如作为图12中的通路导体50的放大图的图14的(C)所示，采用如下的双层结构：在该双层结构中，将由氮化钛溅射膜44a(第一导电层)和铜溅射膜44c(第二导电层)构成的两层形成在开口42的侧壁上。
在第二实施例的印刷线路板中，由于通路导体50的下表面相对于第一层间树脂绝缘层40的第二表面突出了50μm(d2)，因此利用形成在通路导体50上的表面处理涂布物80来实现锚固效果，并且提高了通路导体50和表面处理涂布物80之间的粘合性。
以下说明用于制造第二实施例的印刷线路板的方法。
如以上通过参考图1至图2的(A)所述，在硅基板30上形成热塑性树脂32，并且在热塑性树脂32上层压层间树脂绝缘层40(图11的(A))。在预定部位形成直径为200μm的通路开口42(图11的(B))。在层间树脂绝缘层40的包括通路开口42的内部的表面上，通过溅射形成双层遮挡层44(图11的(C))。通过参考图13的(A)所示的开口42的放大图，进一步详细说明这种遮挡层的结构。遮挡层44由氮化钛溅射膜44a和铜溅射膜44c构成。
下面，形成与以上通过参考图2的(C)～图5的(B)所述的第一实施例中的印刷线路板相同的印刷线路板，并且由成型树脂120封装层间树脂绝缘层60和存储器层压体100。之后，进行加热，并且使用热塑性树脂32去除硅基板30(图13的(B))，然后通过抛光去除热塑性树脂32(图13的(C))。使用氢氧化钾进行蚀刻，以去除经由层间树脂绝缘层40中的开口42而暴露的氮化钛溅射膜44a(图14的(A))。
通过喷砂对第一层间树脂绝缘层40的表面进行研磨，以使厚度减小了d2(50μm)(图14的(B))。如以上参考图14的(C)所述，铜溅射膜44c的表面相对于第一层间树脂绝缘层40的第二表面突出了距离d2(50μm)。
然后，在位于通路导体50的底部的铜溅射膜44c上，通过溅射形成镍膜82。之后，通过利用无电电镀涂布钯膜84和金膜86，来形成由镍膜82、钯膜84和金膜86构成的表面处理涂布物80(图12)。图14的(C)示出图12中的表面处理涂布物80的放大图。
第三实施例
参考图15来说明用于制造根据第三实施例的印刷线路板的方法。
在第一实施例中，在去除热塑性树脂之后，进行蚀刻，以去除经由层间树脂绝缘层40中的开口42而暴露的钛溅射膜44b和氮化钛溅射膜44a。然后，通过喷砂对第一层间树脂绝缘层40的表面进行研磨。相比之下，在第三实施例中，在如第一实施例中的图8的(C)所示去除热塑性树脂之后，通过喷砂对第一层间树脂绝缘层40的表面进行研磨(图15的(A))。之后，去除经由层间树脂绝缘层40中的开口42而暴露的钛溅射膜44b和氮化钛溅射膜44a(图15的(B))。
然后，在位于通路导体50的底部的铜溅射膜44c上通过无电电镀形成镍膜82之后，通过无电电镀按顺序依次形成钯膜84和金膜86，并且形成表面处理涂布物80(图15的(C))。
在第三实施例中，如图15的(B)所示，在开口42和铜溅射膜44c之间，去除钛溅射膜44b和氮化钛溅射膜44a直到深入其内部为止，并且如图15的(C)所示，表面处理涂布物80的镍膜82进入通过这种去除所形成的空间。因此，可以增强通路导体50和表面处理涂布物80之间的粘合性。
第四实施例
在第四实施例中，使用无电电镀铜膜作为第一导电层。即，通路导体50包括形成在层间树脂绝缘层40中的开口42的侧壁上的无电电镀铜膜以及填充在开口42中的电解电镀膜。这里，例如，在去除通路导体的下侧(第一表面侧)的无电电镀铜膜时，作为选择可考虑喷射蚀刻剂。然而，没有特别限制为该去除方法。在本实施例中，可以实现与第一实施例的功能和效果相同的功能和效果。
第五实施例
在第五实施例中，使用非感光性层间树脂绝缘层。在这种情况下，利用激光形成通路导体开口。在此期间，优选形成开口，直至位于层间树脂绝缘层下方的去除层的中间为止。这样，当通过在开口内部形成通路导体来形成布线层之后去除支撑基板时，与第一实施例相同，通路导体的第一表面将相对于层间树脂绝缘层的第二表面而突出。在第五实施例中，也可以实现与上述第一实施例的效果相同的效果。
在经由贯通孔而暴露的通路导体的表面上形成有表面处理涂布物的印刷线路板中，通路导体形成有相对于层间树脂绝缘层的一个表面而突出的表面，利用形成在通路导体的该表面上的表面处理涂布物来实现锚固效果，并且提高了通路导体和表面处理涂布物之间的粘合性。通路导体可以包括形成在贯通孔的侧壁上的第一导电层以及填充贯通孔的镀层。
显然，根据以上教导，可以得出本发明的许多变形和变化。因此，应该理解，除了如这里具体说明的以外，可以在所附权利要求书的范围内实施本发明。
相关申请的交叉引用
本申请要求2009年8月28目提交的美国申请61/237,808的优先权。在此通过引用包含该美国申请的全部内容。

Claims (19)

1.一种印刷线路板，包括：
层间树脂绝缘层，其具有第一表面、位于所述第一表面的相对侧的第二表面以及通路导体用的贯通孔；
导电电路，其形成在所述层间树脂绝缘层的所述第一表面上；
通路导体，其形成于所述贯通孔中，并且具有相对于所述层间树脂绝缘层的所述第二表面而突出的突出部；以及
外部连接用的表面处理涂布物，其形成在所述通路导体的所述突出部的表面上，以具有能够进行引线接合的结构；
其中，所述通路导体连接至所述导电电路，并且包括形成在所述贯通孔的侧壁上的第一导电层以及填充所述贯通孔的镀层。
2.根据权利要求1所述的印刷线路板，其特征在于，所述通路导体具有位于所述第一导电层和所述镀层之间的第二导电层。
3.根据权利要求2所述的印刷线路板，其特征在于，所述第二导电层形成于所述镀层和所述表面处理涂布物之间。
4.根据权利要求2所述的印刷线路板，其特征在于，所述第二导电层和所述镀层由相同的金属制成。
5.根据权利要求2所述的印刷线路板，其特征在于，所述第二导电层和所述镀层由铜制成。
6.根据权利要求1所述的印刷线路板，其特征在于，所述贯通孔的侧壁上的所述第一导电层相对于所述通路导体的所述突出部而凹进。
7.根据权利要求2所述的印刷线路板，其特征在于，所述第一导电层的厚度比所述第二导电层的厚度大。
8.根据权利要求2所述的印刷线路板，其特征在于，通过溅射形成所述第一导电层和所述第二导电层。
9.根据权利要求1所述的印刷线路板，其特征在于，所述表面处理涂布物用于涂布所述贯通孔的外周部分。
10.根据权利要求1所述的印刷线路板，其特征在于，所述第一导电层包括形成在所述层间树脂绝缘层上的氮化钛膜和位于所述氮化钛膜上的钛膜。
11.一种印刷线路板的制造方法，包括：
在支撑基板上形成可去除层；
在所述可去除层上形成层间树脂绝缘层；
在所述层间树脂绝缘层中形成贯通孔；
在所述层间树脂绝缘层上和所述贯通孔的侧壁上形成第一导电层；
在所述层间树脂绝缘层上形成导电电路；
在所述贯通孔中形成通路导体；
通过使用所述可去除层从所述层间树脂绝缘层去除所述支撑基板；
减小所述层间树脂绝缘层的厚度，形成所述通路导体相对于所述层间树脂绝缘层的表面而突出的突出部；以及
在所述通路导体的所述突出部的表面上形成外部连接用的表面处理涂布物以具有能够进行引线接合的结构。
12.根据权利要求11所述的印刷线路板的制造方法，其特征在于，所述通路导体的形成包括：在位于所述贯通孔中的所述第一导电层上形成第二导电层。
13.根据权利要求11所述的印刷线路板的制造方法，其特征在于，所述通路导体的形成包括：在位于所述贯通孔中的所述第一导电层上形成第二导电层并在所述第二导电层上形成镀层，并且所述第二导电层和所述镀层由相同的金属制成。
14.根据权利要求11所述的印刷线路板的制造方法，其特征在于，所述通路导体的形成包括：在位于所述贯通孔中的所述第一导电层上形成第二导电层并在所述第二导电层上形成镀层，并且所述第二导电层和所述镀层由铜制成。
15.根据权利要求11所述的印刷线路板的制造方法，其特征在于，所述通路导体的所述突出部的形成包括：在形成所述表面处理涂布物之前，去除所述第一导电层相对于所述层间树脂绝缘层的表面而突出的部分。
16.根据权利要求11所述的印刷线路板的制造方法，其特征在于，所述可去除层由热塑性树脂制成。
17.根据权利要求11所述的印刷线路板的制造方法，其特征在于，所述第一导电层的形成包括：在所述层间树脂绝缘层上溅射氮化钛膜，并在溅射所述氮化钛膜之后溅射钛膜。
18.根据权利要求11所述的印刷线路板的制造方法，其特征在于，同时形成所述导电电路和所述通路导体。
19.根据权利要求18所述的印刷线路板的制造方法，其特征在于，利用半添加法来执行所述导电电路的形成和所述通路导体的形成。
CN2010102690380A 2009-08-28 2010-08-30 印刷线路板及其制造方法 Active CN102005434B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US23780809P 2009-08-28 2009-08-28
US61/237,808 2009-08-28
US12/840,696 US8410376B2 (en) 2009-08-28 2010-07-21 Printed wiring board and method for manufacturing the same
US12/840,696 2010-07-21

Publications (2)

Publication Number Publication Date
CN102005434A CN102005434A (zh) 2011-04-06
CN102005434B true CN102005434B (zh) 2013-10-16

Family

ID=43623152

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010102690380A Active CN102005434B (zh) 2009-08-28 2010-08-30 印刷线路板及其制造方法

Country Status (3)

Country Link
US (3) US8410376B2 (zh)
CN (1) CN102005434B (zh)
TW (1) TW201132262A (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9275877B2 (en) * 2011-09-20 2016-03-01 Stats Chippac, Ltd. Semiconductor device and method of forming semiconductor package using panel form carrier
US9553059B2 (en) * 2013-12-20 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Backside redistribution layer (RDL) structure
CN106900136B (zh) * 2015-12-21 2021-06-04 青岛海信宽带多媒体技术有限公司 一种光模块的印刷电路板
US9999130B2 (en) 2015-12-21 2018-06-12 Hisense Broadband Multimedia Technologies Co., Ltd. Printed circuit board and optical module comprising solder resist having no contact with an electro-conductive contact sheet group on a same substrate
TWI761852B (zh) * 2016-06-03 2022-04-21 日商大日本印刷股份有限公司 貫通電極基板及其製造方法、以及安裝基板
US11410919B2 (en) * 2017-12-30 2022-08-09 Intel Corporation Stacked silicon die architecture with mixed flipcip and wirebond interconnect
JP7448309B2 (ja) * 2018-11-27 2024-03-12 日東電工株式会社 配線回路基板およびその製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1396797A (zh) * 2001-07-10 2003-02-12 株式会社藤仓 多层接线板组件、多层接线板组件单元及其制造方法
CN101060757A (zh) * 2006-04-18 2007-10-24 国际商业机器公司 用于形成无残余印刷电路板的工艺及其形成的印刷电路板
CN101356642A (zh) * 2006-01-27 2009-01-28 揖斐电株式会社 印刷线路板及其印刷线路板的制造方法
CN101965097A (zh) * 2009-07-23 2011-02-02 揖斐电株式会社 印刷线路板及其制造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1174651A (ja) * 1997-03-13 1999-03-16 Ibiden Co Ltd プリント配線板及びその製造方法
JP2000012627A (ja) * 1998-06-25 2000-01-14 Mitsui Mining & Smelting Co Ltd 両面配線フィルムキャリアの製造方法
RU2134466C1 (ru) * 1998-12-08 1999-08-10 Таран Александр Иванович Носитель кристалла ис
US6709962B2 (en) * 2002-03-19 2004-03-23 N. Edward Berg Process for manufacturing printed circuit boards
US20050081376A1 (en) * 2003-10-21 2005-04-21 Sir Jiun H. Robust interlocking via
TWI246379B (en) * 2004-05-12 2005-12-21 Advanced Semiconductor Eng Method for forming printed circuit board
JP4865197B2 (ja) 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP3914239B2 (ja) * 2005-03-15 2007-05-16 新光電気工業株式会社 配線基板および配線基板の製造方法
US7838779B2 (en) * 2005-06-17 2010-11-23 Nec Corporation Wiring board, method for manufacturing same, and semiconductor package
US7935893B2 (en) * 2008-02-14 2011-05-03 Ibiden Co., Ltd. Method of manufacturing printed wiring board with built-in electronic component
JP2010010644A (ja) * 2008-05-27 2010-01-14 Toshiba Corp 半導体装置の製造方法
US8378230B2 (en) * 2009-07-23 2013-02-19 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US9059187B2 (en) * 2010-09-30 2015-06-16 Ibiden Co., Ltd. Electronic component having encapsulated wiring board and method for manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1396797A (zh) * 2001-07-10 2003-02-12 株式会社藤仓 多层接线板组件、多层接线板组件单元及其制造方法
CN101356642A (zh) * 2006-01-27 2009-01-28 揖斐电株式会社 印刷线路板及其印刷线路板的制造方法
CN101060757A (zh) * 2006-04-18 2007-10-24 国际商业机器公司 用于形成无残余印刷电路板的工艺及其形成的印刷电路板
CN101965097A (zh) * 2009-07-23 2011-02-02 揖斐电株式会社 印刷线路板及其制造方法

Also Published As

Publication number Publication date
US20150075851A1 (en) 2015-03-19
US20110048773A1 (en) 2011-03-03
US8935850B2 (en) 2015-01-20
US8410376B2 (en) 2013-04-02
CN102005434A (zh) 2011-04-06
TW201132262A (en) 2011-09-16
US20130164440A1 (en) 2013-06-27
US9320153B2 (en) 2016-04-19

Similar Documents

Publication Publication Date Title
CN102005434B (zh) 印刷线路板及其制造方法
US7115818B2 (en) Flexible multilayer wiring board and manufacture method thereof
CN110034072B (zh) 半导体封装及其制造方法
US9681546B2 (en) Wiring substrate and semiconductor device
US10306777B2 (en) Wiring board with dual stiffeners and dual routing circuitries integrated together and method of making the same
US9825009B2 (en) Interconnect substrate having cavity for stackable semiconductor assembly, manufacturing method thereof and vertically stacked semiconductor assembly using the same
US20170162556A1 (en) Semiconductor assembly having anti-warping controller and vertical connecting element in stiffener
JP4171499B2 (ja) 電子装置用基板およびその製造方法、並びに電子装置およびその製造方法
US9824963B2 (en) Wiring board, and semiconductor device
CN101315917A (zh) 配线基板及其制造方法
US10062663B2 (en) Semiconductor assembly with built-in stiffener and integrated dual routing circuitries and method of making the same
US20160174365A1 (en) Wiring board with dual wiring structures integrated together and method of making the same
US10217710B2 (en) Wiring board with embedded component and integrated stiffener, method of making the same and face-to-face semiconductor assembly using the same
CN103871998A (zh) 单层无芯基板
US20090008766A1 (en) High-Density Fine Line Structure And Method Of Manufacturing The Same
US8471375B2 (en) High-density fine line structure and method of manufacturing the same
CN101965097B (zh) 印刷线路板及其制造方法
KR20210154450A (ko) 인쇄회로기판 및 이의 제조 방법
US8378230B2 (en) Printed wiring board and method for manufacturing the same
US20030006489A1 (en) Flexible wiring substrate interposed between semiconductor element and circuit substrate
KR101124784B1 (ko) 배선 기판 및 그 제조 방법
KR101034089B1 (ko) 배선 기판 및 그 제조 방법
CN101959374B (zh) 一种多层印制电路板的制造方法
US20090001547A1 (en) High-Density Fine Line Structure And Method Of Manufacturing The Same
US20080303150A1 (en) High-Density Fine Line Structure And Method Of Manufacturing The Same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant