201227890 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種金屬導電結構及其製作方法，尤指—種使用於 玻璃覆晶(chip on glass，COG)技術之金屬導電結構及其製作方法。 【先前技術】 玻璃覆晶(chip on glass , COG)技術係指將晶片直接與破璃基板 •上之連接塾接合的技術，而由於COG技術具有低成本的優勢，因 此目則已廣泛地應用在顯不面板的晶片接合製作上。目前cqg技 術主要使用異方性導電膠(ACF)，將晶片黏貼於玻螭基板上，並以 其中之導電粒子作為晶片上之金屬凸塊與玻璃基板之連接塾的電連 接橋樑。 睛參考第1圖，第1圖為習知將具有金屬凸塊之晶片接合至具 •有連接墊之玻璃基板之示意圖。如第1圖所示，晶片10之鲜塾12 上为別形成有一金屬凸塊I4，且金屬凸塊14係由金所構成。並且， 玻璃基板16上已形成有連接墊18，且連接塾18之位置係對應於銲 墊12之位置。於進行金屬凸塊14與連接墊18的接合製程時，先於 玻璃基板16上塗佈異方性導電膠20，然後將金屬凸塊14係對位於 相對應之連接墊18上，並將金屬凸塊14向下壓合於連接塾丨8上， 使異方性導電膠20中之導電粒子22可電性連接金屬凸塊14與連接 墊18。 201227890 然而，在線路佈局的密度不斷提升的狀況下，晶片上之銲墊間 之距離越來越小’使金屬凸塊之間距亦隨之縮小，並且朗基板上 相對應之連接墊之間距亦會縮小。因此，存在於異方性導電膠中之 導電粒子會因為金屬凸塊之間距縮小啸此更靠近，使得導電粒子 可作為相鄰金屬凸塊之電連接橋樑，進而造成金屬凸塊短路之問 題。並且，金屬凸塊與所欲接合之連触上更存在—定的對位誤差， 因此於晶片與玻璃基板接合後，金屬凸塊與相鄰連接塾之距離更是 小於金屬凸塊之間距，使得導電粒子更容祕為金屬凸塊與相鄰= 接墊之電連接橋樑，而造成短路問題。 有鑑於此，防止因異方性導電膠中之導電粒子產生橫向連 成之短路問題實為業界努力之目標。 【發明内容】 、本心明之主要目的之一在於提供一種金屬導電結構及其製 路問題 包含-载體Γ 種金屬_構。金屬導電結; 導=位於載體上，且第—金屬設於導上，其巾第 一上表面與—側壁’且第—金屬之氧化電位大於或等於銅之^: 201227890 且第二金屬之氧化電位小於 金屬之側壁，且絕緣層包含 位。第二金屬設於第-金屬之上表面， 或等於銀之氧化電位。絕緣層覆蓋第一 有第-金屬之-氧化物。 先 之目的，本發明提供一種金屬導電結構之製作方法首 成一第一金屬於一載體上，第-金屬具有一上表面愈一 且上表面具有1槽，其中第—金 屺、-側壁， 化電位。域，形成—第二金屬於第等於鋼之氧 填滿凹槽，其中第二金屬之 =且第二金屬 著，移除位於•卜m 化電位。接 一金屬之趣形成—絕緣層。 ^驟’以於第 之第於銅之氧化電位 銀之氣L料一金屬未被氧化之前形成氧化電位小於或等於 第二金屬，使第二金屬可藉由第—金屬電性連接至 導電層，村_第—金料有料氧化之祕於第 =面形成絕緣層，以避免於進行晶片與基板接合製程時因異方性 電膠中之導電粒子產生橫向連結而造成短路。、 【實施方式】 本發明主要在於進行-晶片與—基板接合製程之前，先於晶片或 基板上製作金屬導電結構，以用於電性連接晶片與基板，且本發明 之金屬導電結構可聽於餅晶#與基板接合製程巾目異方性導電 201227890 短路問題。 膠中之導電粒子產生橫向連結所造成之 請參考第2圖至第9圖，第 弟圖至第9圖為本發明製作金屬導電 、、。構之方知思®其巾第g圖為本發明較佳實關之金屬導電结 構之剖面示意圖。如第2圖所示，首先提供—載體1()2，且至少_ 導電層106與-保護層1〇8位於載體1〇2上。其中，載體可為基板、 電子元件或晶片，但不限於此。並且，保護層⑽覆蓋於載體ι〇2 與導電層廳上，且保護層108具有一第一穿孔驗，暴露出部分 導電層106。然後，進行，錄製程，形成_緩衝金屬層ιι〇於载 體102上，使緩衝金屬層110覆蓋載體1〇2，並填入第一穿孔職 中’以與導電層106相接觸。值得一提的是，緩衝金屬層⑽係均 勻形成於載體102上’因此當緩衝金屬層m覆蓋於具有第一穿孔 腦之保護層上時，緩衝金屬層m會具有—第—凹槽⑽， 對應第-穿孔108a。其中’本實施例之導電層廳的材料係為導電 金屬材料’例如：！呂’且形成緩衝金屬層11〇之材料可為與導電層 106具有良好接合但未與導電層1〇6產生相互作用之導電材料例 如：鈦鎢合金(TiW)，但不限於此。此外，本發明形成緩衝金屬層 110之方法並不限於使用濺鍍製程，亦可為化學電鍍製程或其他沉 積製程，但不以此為限。 如第3圖所示，接著進行一微影暨蝕刻製程，於緩衝金屬層ιι〇 上形成一圖案化光阻層112，且圖案化光阻層112具有一第二穿孔 112a，使第二穿孔112a對應於導電層1〇6之位置，以暴露出與導電 201227890 層106接觸之緩衝金屬層110。其中，圖案化光阻層112係由光阻 材料所構成，例如：正光阻材料或負光阻材料。此外，第二穿孔 之大小係用於定義出本實施例之金屬導電結構100之寬度，並且後 續所形成之金屬係形成於第二穿孔112a中，因此圖案化光阻層112 之厚度須大於後續所形成之金屬之總厚度，且圖案化光阻層112之 厚度可根據後續所形成之金屬之總厚度來做調整。 如第4圖所接下來於第二穿孔112a中之緩衝金屬層⑽上形 成-第-金屬114’且第-金屬114之厚度係小於圖案化光阻層⑴ 之厚度’使第一金屬114僅位於第二穿孔U2a中，其中第一金屬 114具有-上表面114a與-側壁114b，且第一金屬114係均勻形成 於緩衝金屬層U0上’使第一金屬114之上表面114a隨著第一凹乂槽 110a之輪廓而具有-第二凹槽U4e，且第二凹槽收位與側壁= 相接觸。並且’第-金屬114之氧化電位係大於或等於鋼之氧化電 位’使第-金屬114係屬易氧化金屬，例如：鐵、銅、把、猛、錄 或上述之組合。於本實施财，第—金屬m勒兩金屬層腕'、、 所構成，並且形成第一金屬114之步驟可包含有進行二電鑛製 ，，以分別依序於緩衝金勒則上形成第一金屬層收、隱。 藉此’第-金屬114可為-雙層結構，且雙層結構係為兩種第一金 屬1H之堆疊。然而’本發明之第一金屬114不限於僅由兩個第一 金屬層116a 116b所構成。’於本發明之其他實施例中，第一金屬 1^4可由早-金屬層構成（圖未示），而僅利用單—電錢製程來形成 單-第-金屬114。或者，亦可利用進行複數個電鑛製程，以形成 201227890 由複數個第-金屬層所構成之第一金屬114，且各第一金屬層分別 由不同第-金屬114所構成，使第一金屬114為一多層結構，且多 層結構為複數種第-金屬114之堆疊’但本發明不以此為限。 值得注意的是，本實施例係於形成第一金屬114之前，先於載體 ι〇2上形成緩衝金屬層m，峨絕第一金屬114擴散至載體1〇2上 之導電層106,並且藉自第一金屬m與緩衝金屬層11〇之結合度 高於與導電層106之結合度，以提升第一金屬114結合於載體 上之附著力。然而’本發明並不限於卿成緩衝金屬層ιι〇。 如第5圖所示’然後形成一第二金屬118於第一金屬叫之上表 面脸，且第二金屬118填滿第二凹槽mc。其中，第二金屬⑽ 未覆蓋於_化光_ 112上，而僅位於第二穿孔ma中，使第一 金屬114與第二金屬118之總厚度係小於圖光_ 112之厚 ^ ’第二金屬m之氧化電位小於或等於銀之氧化電位使 第-金屬m係屬不易氧化金屬’例如：金、麵、銀或上述之 於本實施例中，第二金屬118係由單一 、’ 占笛-么思川土 早第一金屬層所構成，並且形 成第-金屬118之步驟可顧―電鍍製程，但不限於此。 :出程，移_案化光阻層112， 如第靡示，接著，以第一金緩衝金屬層110。 除未被第-金屬m與第二金屬UH^18為遮罩’移 足盈之緩衝金屬層110。 201227890 如第8圖所示，然後，進行一研磨製程(p〇lishingpr〇cess)，以移 除位於第二凹槽114c外之第二金屬118，使第一金屬114之裸露出 之上表面114a與第二金屬118之上表面構成一平面，以助於接合於 基板上。此時，第二金屬118僅位於第二凹槽U4c中，因此第二金 屬118未與第-金屬114之側壁114b相接觸。本發明移除位於第二 凹槽114c外之第一金屬118並不限於研磨製程，亦可利用微影暨钱 ^ 刻製程來移除，但不以此為限。 如第9圖所示，最後，實施一氧化步驟，，以於第一金屬丨14之 側i 114b與未受第二金屬118覆蓋之上表面U4a形成一絕緣層 120，使絕緣層120不僅覆蓋於第一金屬114之側壁丨丨牝，更延伸 至位於第二凹槽114c外之第一金屬114之上表面U4a，至此即已完 成本實施例之金屬導電結構1〇〇。於本實施例中，氧化步驟可將已 形成有第-金屬114與第二金屬118之載體1〇2置放於高溫與高濕 Φ的W兄下，例如：坑與相對濕度Μ%，使與環境接觸之第一金屬 u4產生氧化，而於第一金屬114之裸露表面形成絕緣層12〇。並且， 、、、邑緣層120係由氧化第一金屬114而成。然*，本發明形成絕緣層 1之方法並不限於設置於高溫高濕之環境，而僅需使第—金屬！ 14 與氧反應產生氧化，即可形成絕緣層12〇。 值知注意的是’本實施例之設於第一金屬114上之第二金屬118 並不會於冑溫冑濕之環境下與氧反應’因絲可具有導電特性。由 201227890 於=二凹槽mc未與第一金屬114之側壁mb相接觸 金屬118亦不會盘笫一么届, 弟一 120#^ ^ 屬 壁丨丨物相接觸。並且，絕緣層 12〇係由第-金屬114與氧反應而形成，使第一金屬ιΐ4 面:會有絕緣層12。覆蓋，且絕緣層12。姆蓋 二 側壁㈣以及與_⑽她觸之部份上絲ιΐ4 ^ ，片與基板接合製程中，當載魏上形成有複數個第—金屬= 導電好紐絕緣，或者各第—金屬1H可藉由絕緣層12〇斑 相鄰之^層_性絕緣，進而解決因異方性導電膠中之導電粒 子產生檢向連結所造成之短路問題。 ;、 一=所述’本發明係於載體上先形成易氧化之第—金屬，再 金屬未魏化之前形成科氧化之第二金屬，使第二 ' 狀裸絲面形成絕緣層，㈣免於進行晶片盘其此 ^合製程時因異方性導電膠中之導電粒子產生橫向連結而造成I 再者，本發明之第一金屬之上表面更具有未與側壁相 使第二金屬可僅填人第二凹槽中且未與側壁相接觸，因此 效電性絕緣二相鄰之第二金屬或電性絕緣一 所傲以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 之均等變化與修飾，皆應屬本發明之涵蓋範圍。 201227890 【圖式簡單說明】 第1圖為S知將具有金屬凸塊之晶片接合至具有連接蟄之玻璃基板 之示意圖。 第2圖至第9 11為本發明製作金屬導電結構之方法示意圖。 10 14 18 22 1〇2 1〇8 110 112 U4 絕緣層 【主要元件符號說明】 晶片 金屬凸塊 連接墊 導電粒子 載體 保護層 緩衝金屬層 圖案化光阻層 第一金屬 ll4b側壁 ll6a、第一金屬層 116b 120 12 銲墊 16 玻璃基板 20 異方性導電膠 100 金屬導電結構 106 導電層 108a 第一穿孔 110a 第一凹槽 112a 第二穿孔 114a 上表面 114c 第二凹槽 118 第二金屬201227890 VI. Description of the Invention: [Technical Field] The present invention relates to a metal conductive structure and a manufacturing method thereof, and more particularly to a metal conductive structure used in chip on glass (COG) technology and its fabrication method. [Prior Art] The technology of chip on glass (COG) refers to the technology of directly bonding a wafer to a connection on a glass substrate. Since COG technology has the advantage of low cost, it has been widely used. On the wafer bonding fabrication of the panel. At present, the cqg technology mainly uses an anisotropic conductive paste (ACF) to adhere the wafer to the glass substrate, and the conductive particles therein are used as an electrical connection bridge between the metal bumps on the wafer and the glass substrate. Referring to Fig. 1, Fig. 1 is a schematic view showing the bonding of a wafer having metal bumps to a glass substrate having a connection pad. As shown in Fig. 1, a metal bump I4 is formed on the fresh crucible 12 of the wafer 10, and the metal bump 14 is made of gold. Further, a connection pad 18 has been formed on the glass substrate 16, and the position of the connection port 18 corresponds to the position of the pad 12. When the bonding process of the metal bump 14 and the connection pad 18 is performed, the anisotropic conductive paste 20 is applied on the glass substrate 16, and then the metal bumps 14 are paired on the corresponding connection pads 18, and the metal is The bumps 14 are pressed down on the connecting pads 8 to electrically connect the conductive particles 22 in the anisotropic conductive paste 20 to the metal bumps 14 and the connection pads 18. 201227890 However, under the condition that the density of the line layout is increasing, the distance between the pads on the wafer is getting smaller and smaller 'the distance between the metal bumps is also reduced, and the spacing between the corresponding pads on the substrate is also Will shrink. Therefore, the conductive particles existing in the anisotropic conductive paste may be closer to each other due to the narrowing of the distance between the metal bumps, so that the conductive particles can serve as an electrical connection bridge between adjacent metal bumps, thereby causing a short circuit of the metal bumps. Moreover, there is a certain alignment error between the metal bump and the joint to be bonded. Therefore, after the wafer is bonded to the glass substrate, the distance between the metal bump and the adjacent connection is smaller than the distance between the metal bumps. The conductive particles are made more dense as the electrical connection between the metal bumps and the adjacent = pads, causing a short circuit problem. In view of this, it is an industry goal to prevent the short-circuiting of laterally connected conductive particles in the anisotropic conductive paste. SUMMARY OF THE INVENTION One of the main purposes of the present invention is to provide a metal conductive structure and its routing problems including - carrier metal. The metal conductive junction; the conductor is located on the carrier, and the first metal is disposed on the guide, the first upper surface of the towel and the side wall and the oxidation potential of the first metal is greater than or equal to that of the copper: 201227890 and the oxidation of the second metal The potential is less than the sidewall of the metal and the insulating layer contains the bit. The second metal is disposed on the upper surface of the first metal, or equal to the oxidation potential of the silver. The insulating layer covers the first metal-oxide. Firstly, the present invention provides a method for fabricating a metal conductive structure. The first metal is formed on a carrier. The first metal has an upper surface and a groove on the upper surface, wherein the first metal layer and the side wall are formed. Potential. The domain is formed—the second metal fills the groove with oxygen equal to the steel, wherein the second metal = and the second metal is removed, and the removal is at the potential. The formation of a metal is the formation of an insulating layer. The second metal can be electrically connected to the conductive layer by the first metal, before the metal is not oxidized, and the oxidation potential is less than or equal to the second metal, so that the second metal can be electrically connected to the conductive layer by the first metal. The village _ _ gold material has the secret of oxidation on the first surface to form an insulating layer, in order to avoid a short circuit caused by the lateral connection of the conductive particles in the anisotropic electrode during the wafer-substrate bonding process. [Embodiment] The present invention mainly provides a metal conductive structure on a wafer or a substrate for electrically connecting a wafer and a substrate before the wafer-to-substrate bonding process, and the metal conductive structure of the present invention is audible Cake crystal # and substrate bonding process towel anisotropy conductive 201227890 short circuit problem. The conductive particles in the glue are caused by the lateral connection. Please refer to Figures 2 to 9. The figures from the second to the ninth are the conductive materials of the present invention. The structure of the method is the cross-sectional view of the metal conductive structure of the preferred embodiment of the present invention. As shown in Fig. 2, carrier 1 () 2 is first provided, and at least _ conductive layer 106 and - protective layer 1 〇 8 are located on carrier 1 〇 2. The carrier may be a substrate, an electronic component or a wafer, but is not limited thereto. Moreover, the protective layer (10) covers the carrier ι2 and the conductive layer chamber, and the protective layer 108 has a first punch test to expose a portion of the conductive layer 106. Then, the recording process is performed to form a buffer metal layer on the carrier 102 such that the buffer metal layer 110 covers the carrier 1〇2 and fills the first punching member' to be in contact with the conductive layer 106. It is worth mentioning that the buffer metal layer (10) is uniformly formed on the carrier 102. Therefore, when the buffer metal layer m covers the protective layer having the first perforated brain, the buffer metal layer m has a first groove (10). Corresponding to the first through hole 108a. Wherein the material of the conductive layer chamber of the present embodiment is a conductive metal material, for example: The material which forms the buffer metal layer 11 turns may be a conductive material which has a good bonding with the conductive layer 106 but does not interact with the conductive layer 1〇6, such as titanium tungsten alloy (TiW), but is not limited thereto. In addition, the method for forming the buffer metal layer 110 of the present invention is not limited to the use of a sputtering process, but may be an electroless plating process or other deposition process, but is not limited thereto. As shown in FIG. 3, a lithography and etching process is then performed to form a patterned photoresist layer 112 on the buffer metal layer ιι, and the patterned photoresist layer 112 has a second via 112a for the second via. 112a corresponds to the location of the conductive layer 1〇6 to expose the buffer metal layer 110 in contact with the conductive 201227890 layer 106. The patterned photoresist layer 112 is composed of a photoresist material, such as a positive photoresist material or a negative photoresist material. In addition, the size of the second through hole is used to define the width of the metal conductive structure 100 of the embodiment, and the subsequently formed metal is formed in the second through hole 112a, so the thickness of the patterned photoresist layer 112 must be greater than the subsequent The total thickness of the formed metal, and the thickness of the patterned photoresist layer 112, can be adjusted based on the total thickness of the subsequently formed metal. The -metal 114' is formed on the buffer metal layer (10) in the second via 112a as shown in FIG. 4 and the thickness of the first metal 114 is smaller than the thickness of the patterned photoresist layer (1) such that the first metal 114 is only Located in the second through hole U2a, wherein the first metal 114 has an upper surface 114a and a side wall 114b, and the first metal 114 is uniformly formed on the buffer metal layer U0' such that the first surface 114a of the first metal 114 follows the first The contour of the recessed groove 110a has a second groove U4e, and the second groove is in contact with the side wall=. Further, the oxidation potential of the first metal 114 is greater than or equal to the oxidation potential of the steel. The first metal 114 is an easily oxidizable metal such as iron, copper, copper, lanthanum, or a combination thereof. In the present implementation, the first metal metal layer is formed by the second metal layer, and the step of forming the first metal 114 may include performing a second electric current system to form a first step on the buffering gold. A metal layer is closed and hidden. Thereby, the 'first metal 114' may be a two-layer structure, and the two-layer structure is a stack of two first metal 1H. However, the first metal 114 of the present invention is not limited to being composed of only two first metal layers 116a to 116b. In other embodiments of the present invention, the first metal 1^4 may be formed of an early-metal layer (not shown), and the single-metal-only 114 may be formed using only a single-electron process. Alternatively, a plurality of electro-minening processes may be performed to form a first metal 114 composed of a plurality of first-metal layers of 201227890, and each of the first metal layers is composed of a different first-metal 114, so that the first metal 114 is a multilayer structure, and the multilayer structure is a stack of a plurality of first-metals 114', but the invention is not limited thereto. It should be noted that, in this embodiment, before the formation of the first metal 114, the buffer metal layer m is formed on the carrier ι 2 to diffuse the first metal 114 to the conductive layer 106 on the carrier 1 〇 2, and The degree of bonding from the first metal m to the buffer metal layer 11 is higher than the degree of bonding with the conductive layer 106 to enhance the adhesion of the first metal 114 to the carrier. However, the present invention is not limited to the singular metal buffer layer ιι. As shown in Fig. 5, a second metal 118 is then formed on the first metal surface and the second metal 118 is filled in the second recess mc. Wherein, the second metal (10) is not covered on the _ _ _ 112, but only in the second perforation ma, so that the total thickness of the first metal 114 and the second metal 118 is less than the thickness of the light _ 112 ^ second The oxidation potential of the metal m is less than or equal to the oxidation potential of the silver such that the first metal m is a metal that is not easily oxidized, such as gold, surface, silver or the like, in the present embodiment, the second metal 118 is composed of a single, 'according to the flute. - Moss River is formed by the first metal layer, and the step of forming the first metal 118 can be considered as the electroplating process, but is not limited thereto. : Departure, shifting the photoresist layer 112, as shown in the second, followed by the first gold buffer metal layer 110. The buffer metal layer 110 is removed by the first metal m and the second metal UH 18 as a mask. 201227890, as shown in FIG. 8, then, a polishing process is performed to remove the second metal 118 located outside the second recess 114c, exposing the first metal 114 to the upper surface 114a. Forming a plane with the upper surface of the second metal 118 to facilitate bonding to the substrate. At this time, the second metal 118 is only located in the second recess U4c, so that the second metal 118 is not in contact with the side wall 114b of the first metal 114. The removal of the first metal 118 located outside the second recess 114c is not limited to the polishing process, and may be removed by using a lithography and engraving process, but is not limited thereto. As shown in FIG. 9, finally, an oxidation step is performed to form an insulating layer 120 on the side i 114b of the first metal crucible 14 and the upper surface U4a not covered by the second metal 118, so that the insulating layer 120 not only covers The sidewall 丨丨牝 of the first metal 114 extends to the upper surface U4a of the first metal 114 outside the second recess 114c, and thus the metal conductive structure 1〇〇 of the embodiment has been completed. In this embodiment, the oxidation step can place the carrier 1〇2 on which the first metal 114 and the second metal 118 have been formed under the W brother of high temperature and high humidity Φ, for example, pit and relative humidity Μ%, so that The first metal u4 in contact with the environment is oxidized, and the insulating layer 12 is formed on the exposed surface of the first metal 114. Further, the edge layer 120 is formed by oxidizing the first metal 114. However, the method of forming the insulating layer 1 of the present invention is not limited to being placed in an environment of high temperature and high humidity, but only the first metal is required! 14 The reaction with oxygen generates oxidation, and the insulating layer 12 is formed. It is to be noted that the second metal 118 provided on the first metal 114 of the present embodiment does not react with oxygen in an environment of temperature and humidity. The wire may have conductive properties. From 201227890, the second groove mc is not in contact with the side wall mb of the first metal 114. The metal 118 will not be entangled, and the brother 120#^^ belongs to the wall object. Further, the insulating layer 12 is formed by reacting the first metal 114 with oxygen so that the first metal layer 4 has an insulating layer 12. Covered, and insulating layer 12. The two side walls of the Mgai (four) and the part of the _(10) she touches the wire ΐ4 ^ , the film-substrate bonding process, when the carrier is formed with a plurality of first metal = conductive good insulation, or each of the first metal 1H The problem of short circuit caused by the detection connection of the conductive particles in the anisotropic conductive paste is solved by the adjacent layer of the insulating layer 12. ; a = the said 'the invention is formed on the carrier first to form an easily oxidizable first metal, and then the second metal formed by the oxidation of the metal before the metal is not Wei, so that the second 'shaped bare wire surface to form an insulating layer, (four) free In the process of performing the wafer disc, the lateral connection of the conductive particles in the anisotropic conductive paste is caused by the lateral connection. The upper surface of the first metal of the present invention has a second metal which is not adjacent to the sidewall. Filling in the second recess and not in contact with the sidewall, so that the second insulating metal or the electrical insulating is adjacent to the preferred embodiment of the present invention. Equivalent changes and modifications of the scope of the patent application are intended to be within the scope of the invention. 201227890 [Simplified Schematic] FIG. 1 is a schematic view showing the bonding of a wafer having metal bumps to a glass substrate having a connection. 2 to 9 are schematic views showing a method of fabricating a metal conductive structure according to the present invention. 10 14 18 22 1〇2 1〇8 110 112 U4 Insulation layer [Main component symbol description] Wafer metal bump connection pad Conductive particle carrier protective layer Buffer metal layer patterned photoresist layer First metal ll4b sidewall ll6a, first metal Layer 116b 120 12 pad 16 glass substrate 20 anisotropic conductive paste 100 metal conductive structure 106 conductive layer 108a first through hole 110a first groove 112a second through hole 114a upper surface 114c second groove 118 second metal