TW201248814A - Coreless package substrate and method of making same - Google Patents

Abstract

Proposed is a coreless package substrate, including a dielectric layer having openings formed thereon, a circuit layer embedded in the dielectric layer and having electrical contact pads formed thereon, and a metal bump disposed on each of the electrical contact pads while being exposed from the openings. By forming metal bumps on electrical contact pads, solder balls can be connected to electrical contact pads by connecting with the metal bumps in the subsequent ball-implantation process, thereby facilitating ball-implantation and preventing inferior electrical connection. The invention further provides a method for fabricating the coreless package substrate as described above.

Description

201248814 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a packaged expansive substrate, and more particularly to a coreless package substrate and a method of fabricating the same. [Prior Art] [0002] In recent years, with the rapid development of electronic technology, the high-tech electronics industry has come out one after another, making it even more human, and the electronic products with better human functions are constantly being introduced and lighter. The trend of loose, short and small is developing. 〇 At present, the semiconductor hiding structure has developed the same package type, for example: wire-bonding or flip-chip type, which is provided with a semiconductor wafer on a 1-substrate substrate, and the semiconductor wafer is electrically connected to the package by wires or solder bumps. The stomach packaging substrate is composed of a core plate and a line-adding structure provided thereon. However, due to the thickness of the core, the thickness of the plate is not favorable for the demand for thinning, and the development of a The coreless package substrate shown in the figure includes: a circuit layer 1H having a plurality of electrical contacts 11H on a dielectric layer 12 and having a plurality of openings 120 extending through the dielectric layer 12, Exposing the underside of the electrical contact pad 11 and forming a solder resist layer 16 ′ on both surfaces of the dielectric layer 12 and exposing the upper side of the electrical contact pad 110 and the opening 120° The thickness of the dielectric layer 12 is much smaller than the thickness of the core board, so that the overall thickness of the package structure can be greatly reduced to meet the demand for thinning. [0004] 100118151 Further, the electrical contact pad 110 is exposed to the dielectric layer 12. The surface of the opening 120 can be used as a flip chip or a ball pad. The electrical contact pad 110 is exposed on the surface of the solder resist layer 16 and can be used as a flip chip, a wire pad or a ball pad. Therefore, when the package is packaged, the package substrate 1 can provide not only a wire type wafer but also a form number A0101. Page / A total of 23 pages 1002030535-0 201248814 [0005] [0007] [0008] [0009] [0009] [0009] packaging, and can provide flip-chip wafers for packaging, thus meeting the needs of flexibility and multi-function. It is known that the depth of the opening 120 of the dielectric layer 12 of the package substrate 1 is too deep, so that when the ball placement process is performed, the solder ball 14 is not easily connected to the electrical contact pad 110, resulting in poor electrical connection, thus affecting the product. The yield layer 11 is formed on the surface of the dielectric layer 12, so that the overall thickness of the package structure can no longer be reduced, so that it is difficult to increase the degree of thinning. Therefore, how to overcome the above-mentioned prior art Various problems have been solved by the present invention. SUMMARY OF THE INVENTION In view of the above-mentioned various deficiencies of the prior art, the present invention provides a coreless package substrate for burying a circuit layer having a plurality of electrical contact pads. a dielectric layer having opposite surfaces, wherein the metal block is also embedded in the dielectric layer and disposed on the electrical contact pad, and one surface of the dielectric layer has a plurality of openings, and the metal is exposed And the other surface of the dielectric layer exposes the electrical contact pad and the circuit layer. According to the above configuration, the coreless package substrate of the present invention is mainly formed on the electrical contact pad for soldering the solder ball. The metal block, the metal block material such as copper, tin, gold, silver, tin boat alloy, etc., so that the opening of the dielectric layer only needs to expose the metal block to be connected to the solder ball, so when the ball placement process is performed, The solder ball only needs to be connected to the metal block to electrically connect the electrical contact pad, so that the solder ball can not only be stuck in the opening, but also needs to fall into the 100118151 Form No. A0101 Page 4 / Total 23 pages 1002030535-0 201248814 [0011] [0013] [0013]

The depth of the opening is reduced to facilitate the completion of the electrical connection to avoid the problem of poor electrical connection. Furthermore, the circuit layer is embedded in the dielectric layer, and the circuit layer is disposed on the dielectric layer in the prior art. The present invention can reduce the overall thickness of the package structure during subsequent packaging to meet the thinning demand. Moreover, according to the above-described package substrate of the present invention, the present invention provides a method for manufacturing a coreless package substrate, the specific details of which will be described later. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily understand other advantages and functions of the present invention from the disclosure of the present disclosure. It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper side", "lower side", "top", "upper surface" and "lower surface" as used in the specification are merely for convenience of description, and are not intended to limit the present invention. The scope of the invention, the change or adjustment of the relative relationship, is also considered to be within the scope of the invention. First Embodiment 100118151 Form No. Α 0101 Page 5 / Total 23 Page 1002030535-0 [0014] [0015] [0016] [0020] [0020] 100118151 Please refer to Figures 2A to 2E A schematic cross-sectional view of a method for fabricating a core-less package substrate of the present invention. As shown in FIG. 2A, a carrier board 20 is first provided, and a circuit layer 21 having a plurality of electrical contact pads 210 is formed on the upper and lower sides of the carrier board 20. The electrical contact pads 210 are exposed. The first surface (upper surface) 210a and the second surface (lower surface) 210b bonded to the carrier sheet 20. In the present embodiment, the wiring layer 21 is formed by using a copper foil substrate (CCL) to utilize the core plate of the copper germanium substrate as the carrier plate 20, and the copper layers on the upper and lower sides thereof are formed. The circuit layer 21, and the surface of the carrier board 20, has a release film 200 that contacts the circuit layer 21. However, there are many restrictions on the way in which the circuit layer is formed, and there is no particular limitation. Moreover, the processes on the upper and lower sides of the carrier board 20 are the same, so only one side of the process will be described, and the process of the other side will not be repeated. As shown in FIG. 2B, a dielectric layer 22 is formed on the carrier layer 2 and the circuit layer 21, and a plurality of openings 220 are formed on the dielectric layer 22 by laser to make the electrical properties. A portion of the first surface 21A of the contact pad 210 is correspondingly exposed in each of the openings 2 2 . The dielectric layer 22 has an upper side 22a and a lower side 22b. The lower side 22b of the dielectric layer 22 is bonded to the release film 2 of the carrier board 2 and the upper side 22a of the dielectric layer 22. The opening 22 is formed. As shown in FIG. 2C, the metal block ^ is formed by electroplating on the first surface of the electrical contact 塾 (10) in the opening 220. Form number _ * 6 I / * 23 ! ' and each of the 1002030535-0 [0021] 201248814 The top surface of the f-block 23 is lower than the surface of the upper side 22a of the dielectric layer 22, that is, the metal block 23 does not occupy the opening 220. [0023] [0024] θ 2D FIG. 7 ′′ removes the carrier 20 by the release film 2GG, and the coreless package substrate 2 of the two single-layer lines, and The second surface 2 of the circuit layer of the electrical discharge contact 21 is exposed on the surface of the lower side 22b of the dielectric layer 22. ^2D', as shown in the second embodiment of the package substrate 2, the adjacent eight requirements 'by the micro-etching method, removing the exposed surface of the circuit layer 21 and each of the electrical contacts a portion of the second surface 2 serves to the surface of the circuit layer 21' and each of the electrical contacts (4), and the second electrical layer 2 = the lower surface is lower than the surface of the lower side (10) of the dielectric layer 22, such that the dielectric layer The lower side m of 22 can be used as a solder resist layer. As shown in the figure (4) 2E', the surface treatment is formed (4) on the line =, 1 and each of the electrical contacts 21021〇, 21〇b, 2l〇b, above. Ο [0025] The material of the surface treatment layer 25 is selected from the group consisting of electric mineral gold/gold, chemical money nickel/gold, chemical immersion gold (10) (6), and electroless tin plating (immersion). Composition of palladium immersion gold (ENEPIG), Tln) and organic solder resist (0SP) [0026] 100118151 = The substrate used for sealing the substrate of the present invention, as shown in Fig. 2F, is a coating application of the sundial, The ruthenium β in the first surface is formed, so that the solder material 24 is formed on the opening 220 ball to be convex, and the (four) material 24 is a solder bump or a solder-dielectric potential 22 surface, and the solder is formed by the solder Riding material 24 flip chip form number 雠 n page / 23 pages 1002030535-0 201248814 = electrode 塾 6a of the semiconductor wafer 6, and then the primer 5 is formed in the semiconductor, between the sheet 6 and the dielectric layer 22, To cover the solder material (four). Furthermore, the second surface 2丨(10) of the electric 1±contact 塾21〇 is used as a ball-planting ball to bond the circuit board 4 by the ball 40. [0029] [0029] In the other - flip chip application, as shown in the 2F, the second surface 21 () 1) of the contactless 塾 21G is used as a flip chip soldering The solder bump 6 is flip-chip bonded to the semiconductor wafer 6, the electrode electrode 6a, and then the ice is formed on the semiconductor wafer 6, and the solder bump 6G is covered with the dielectric layer μ. Moreover, the first surface of the electrical contact pad 21 is used as a ball pad to bond a circuit board 4 by the solder material 24 on the metal block μ. In the application form of the wire-bonding package, as shown in FIG. 2, the second surface 21Qb of the electrical contact is used as a wire 塾 to be electrically connected to the dielectric layer 22 by wires 6〇. The semiconductor crystal (10), the electric (four) 6a", and the encapsulation colloid 7 is used to cover the semiconductor wafer. Moreover, the first surface 210a of the electrical contact pad 210 acts as a ball bump to bond the circuit board 4 by the tin-like material on the metal block 23. In the manufacturing method of the present invention, a portion of the space formed in the opening 22 of the dielectric layer 22 forms a metal block 23' so that the solder material 24 only needs to fill the remaining opening 220 space to electrically connect the electrical property. The contact pad 21 〇, 21〇, does not need to completely fill the opening 220, so the solder material 24 can not only be firmly received in the opening 220, but also falls into the opening 22 It is less convenient to complete the electrical connection work, so the problem of poor electrical connection can be avoided. 100118151 Form No. A0101 Page 8 of 23 1002030535-0 201248814 [0031] 再 [0032] Further, 'the circuit layer 21 is formed first, and then the circuit layer 21 is covered with the dielectric layer 22' In the prior art, the technique of forming the dielectric layer 12 and then forming the wiring layer η on the dielectric layer 12, the method of the present invention allows the circuit layer 21 to be buried in the dielectric layer 22, thus The overall thickness of the package structure can be reduced during packaging to meet the needs of thinning. In the package substrate 2, 2 of the present invention, the first surface 2i〇a of the electrical contact pad 21〇'21〇 can be used as a flip chip or a ball pad, and the electrical contact pad 21〇, 210, the second surface 210b, 210b, can be used as flip chip soldering, wire bonding or ball bonding. Therefore, the package substrate 2, 2 of the present invention can provide not only a wire-type semiconductor wafer for packaging, but also a flip chip type. The semiconductor wafer is packaged to meet the needs of flexibility and versatility. In addition, the area of the first surface 210a and the second surface 21〇b, 210b' of the electrical contact pads 210, 210' will be different depending on the mode of use (for example, as a flip chip, a ball pad or a wire pad), and When the circuit layers 21, 21' are formed, the electrical contact pads 21, 21, can be adjusted. [0033] Second Embodiment [0034] Please refer to Figures 3A to 3E for the present invention. A schematic cross-sectional view of another manufacturing method of the package substrate 3. The difference between this embodiment and the above embodiment is mainly in the order of formation of the metal block and the dielectric layer. The related processes of the other package substrates are substantially the same, and therefore will not be described again. [0035] As shown in FIG. 3A, the process of FIG. 2A is continued to form a metal block 33 on the first surface 21〇a of each of the electrical contact pads 210. 100118151 Form No. A0101 Page 9 of 23 1002030535-0

201248814 [0036J

[0037J

[0040] [0041] 100118151, as shown in FIG. 1, does not form a dielectric layer 32 on the carrier 20, the line layer 21 and the metal block 33. As shown in FIG. 3C, #1) ^ hunting removes the carrier 20 from the release film 200, and the second surface 21 0 b of each of the electric electrodes 210 is exposed to the dielectric layer. 32 under the side of the coffee surface.

As shown in FIG. 3D, L^ does not form a plurality of openings 320 on the surface 1 of the dielectric layer 32, so that part of the surface of the metal blocks 33 is correspondingly exposed in each of the openings 32, , the coreless package substrate 3 of the present embodiment is described. The steps shown in FIG. 3C and the step shown in FIG. 3D can also be adjusted. After the step 38 is continued, a plurality of openings 320 are formed in the < Exposed on the exposed surface, the portion of the metal block 33 is removed from the opening 32G by the release film, and the second surface a of the circuit layer 21 and each of the electrical contacts t*21G is removed. Exposed to the lower side of the dielectric layer 32, the m table is as shown in the figure (10), and the other type of package base is corrected, and the micro-mode is used to make the circuit layer 2 Sexual contact (4). The second surface is equal to the surface of the lower side 32b. As shown in Fig. 3E or 3E, the surface treatment layer (4) is formed on the second surface 210b, 210b' of the circuit layer 21, 21 and each of the electrical contact pads 21, 21, 。. ~~ In this embodiment, 'before the electrical contact pads 21q, 2ig, the upper force is formed into a metal block 33, and then the dielectric (4) is covered to make the depth of the opening hole ^ Form No. A0101, page 10 / A total of 23 pages 'again.

[0044] [0046] [0046] [0046] The metal block 33 needs to be exposed, so the opening 32 of the present embodiment is deeper than the opening through which the conventional dielectric layer is penetrated. The solder material Μ is only required to be connected to the metal block 33 to electrically connect the electrical contact ports 210, 210 ′, thereby facilitating the electrical connection. According to the method of the two embodiments, a coreless package substrate 2, 3 is obtained, comprising: a dielectric layer 22, 32 having an upper side 22a, 32a and a lower side 22b, 32b, embedded in the The circuit layers 21 of the dielectric layers 22, 32 and having a plurality of electrical contact pads 210, and metal blocks 23, 33 disposed on each of the electrical contact pads 210. The upper layers 22a, 32a of the dielectric layers 22, 32 have a plurality of openings 220, 320 therein. The electrical contact pad 210 has a first surface 21a and a second surface 210b opposite to each other, and the circuit layer 21 and the second surface 210b of each of the electrical contact pads 21 are exposed to the dielectric layer 22, 32 lower side 22b, 32b, and in different embodiments, the first surface 21 of the electrical contact pad 21 can be made into a solder pad or a ball pad, and the electrical contact is made. The second surface 210b of the pad 21 is used as a wire pad or a ball pad. Alternatively, the surface layer 21, the surface (including the second surface 2i〇b' of each of the electrical contact pads 21〇) may be lower than the surface of the lower sides 22b, 32b of the dielectric layers 22, 32. The metal blocks 23, 33 are disposed on a portion of the first surface 210a of each of the electrical contact pads 21, and are exposed to the openings 220, 320 of the dielectric layers 22, 32, and each of the metal blocks 23, 33 The surface is below the surface of the upper side 22a, 32a of the dielectric layer 22, 32. In still other embodiments, the top surface of the metal block 23 can be completely exposed to the opening 22 (as shown in FIG. 2E, 100118151, Form No. A0101, Page 11 / Total 23, 1002030535-0 201248814 [0047] [ [0050] [0050] or expose the top surface portion of the metal block 33 to the opening 320 (as shown in FIG. 3D). The coreless package substrate 2, 3 is formed in the a solder material 24 on the metal blocks 23, 33 in the openings 220, 320, and a surface treatment layer 25 formed on the second surface 21 Ob of the electrical contact pad 210. In summary, the present invention has no core type The package substrate and the manufacturing method thereof are formed on the electrical contact pad to form a metal block, so that the solder ball only needs to be connected with the metal block, so the depth of the solder ball in the dielectric layer is smaller than the conventional technology, thereby facilitating completion. The operation of electrical connection. Furthermore, by embedding the circuit layer in the dielectric layer, the overall thickness of the package structure is reduced by the purpose of thinning. The above embodiments are for illustrative purposes. The principles of the invention and its efficacy, and are not intended to limit the invention. Are persons of skill may be made without departing from the spirit and scope of the present invention, the above-described embodiments can be modified. Thus the scope of the claims of the present invention, as shall be described later after the patent application listed range.

[0053] FIG. 1 is a schematic view of a conventional coreless package substrate; FIGS. 2A to 2E are diagrams of a method for manufacturing a coreless package substrate of the present invention. A cross-sectional view of the first embodiment; wherein, the 2D, 2E' diagram is another embodiment of the 2D to 2E diagram; and the 2F, 2F', and 2F" diagrams are the coreless package to which the present invention is applied. A schematic cross-sectional view of a package structure of different implementations made by a substrate; and a form number A0101 page 12/23 page 1002030535-0

201248814 [0054] FIGS. 3A to 3E are schematic cross-sectional views showing a second embodiment of a method for manufacturing a coreless package substrate of the present invention; wherein, FIGS. 3D' to 3E' are diagrams 3D to 3E An implementation. [Description of main component symbols] [0055] 1, 2, 2, 3, 3, package substrate [0056] 11, 21, 21, circuit layer [0057] 110, 210, 210, electrical contact pad [0058] 12 , 22, 32 Dielectric layer # [0059] 1 20, 220, 320 Opening [0060] 14, 40 solder balls [0061] 16 solder mask [0062] 20 carrier plate [0063] 200 release film [0064] 210a first surface [0065] 210b, 210b' second surface [0066] 22a, 32a upper side [0067] 22b, 32b lower side [0068] 23, 33 metal block [0069] 24 solder material [0070] 25 surface treatment layer 100118151 Form No. A0101 Page 13 of 23 1002030535-0 201248814 [0071] 4 Circuit Board [0072] 5 Primer [0073] 6,6', 6" Semiconductor Wafer [0074] 6a, 6a', 6a" Electrode Pad [0075] 60' solder bump [0076] 60,, wire [0077] 7 package colloid 1002030535-0 100118151 Form No. A0101 Page 14 of 23

Claims (1)

201248814 VII. Patent application scope: 1. A coreless package substrate, comprising: a dielectric layer having opposite first and second sides, and having a plurality of openings on a first side of the dielectric layer a circuit layer embedded in the dielectric layer and having a plurality of electrical contact pads having opposite first and second surfaces, the circuit layer and each of the electrical contact pads The second surface is exposed on the second side of the dielectric layer; and the Λ metal block is disposed on a portion of the first surface of each of the electrical contact pads to expose the metal block to the opening of the dielectric layer And the surface of each of the metal blocks is lower than the first side of the dielectric layer. 2. The coreless package substrate of claim 1, wherein the surface of the circuit layer is lower than the second side of the dielectric layer. 3. The coreless package substrate of claim 1, wherein the first surface of the electrical contact pad acts as a flip chip or a ball pad, and the second surface of the electrical contact pad Used as a flip chip, wire pad or ball pad. 4. The coreless package substrate of claim 1, wherein the top surface of the metal block is completely exposed to the opening or partially exposed to the opening. 5 . The method for manufacturing a coreless package substrate, comprising: providing a carrier board; forming a circuit layer on the carrier board, the circuit layer having a plurality of electrical contact pads, wherein the electrical contact pads have a relative a first surface and a second surface; forming a dielectric layer on the carrier layer and the circuit layer, and forming a plurality of openings on the dielectric layer 100118151 Form No. 1010101, page 15 / 23 pages 1002030535-0 201248814 a portion of the first surface of the electrical contact 对应 is correspondingly exposed in each of the openings; forming a metal block on the first surface of the electrical contact pad in each of the openings to expose the entire surface of the metal block to each of the openings Opening the towel, and the surface of each of the metal blocks is lower than the surface of the dielectric layer; and removing the carrier plate to expose the circuit layer and the second surface of each of the electrical contacts. = The method for manufacturing the non-core handle substrate according to the fifth aspect of the patent, wherein the first surface of the electrical contact is used as a flip chip or a ball implant. The system is used as a rotating crystal material, a wire bonding pad or a β-moon raising (5) 炙熬 core type, which is included in the removal of the residual wire, the removal, and the substrate manufacturing method, so that the surface of the circuit layer is lower than the dielectric Partially exposed form A method of making a coreless package substrate, including a face. Providing a carrier board; forming a circuit layer on the carrier board, the circuit layer having a plurality of electrical contact pads, the electrical contact pads having phase first and second surfaces; forming a metal block on each of the electrical contact pads Rr / . Table ©, open ^ 1 " electric layer on the material balance, circuit layer and the metal block; remove the carrier plate, exposed the line outside the cage ^ 吟 layer and each of the electrical contact pads t And a plurality of openings are formed on the dielectric layer, and a portion of the surface of the metal blocks is correspondingly exposed in each of the openings. The method for manufacturing a coreless package substrate according to claim 8 wherein the first surface of the electrical contact pad is 100118151. Page 16 of 23 Form No. Face No. 16... is a flip chip or a ball-shaped plastic 1002030535-0 201248814, and the second surface of the electrical contact pad acts as a flip chip, wire pad or bulb. 10. The method of manufacturing a coreless package substrate according to claim 8, wherein after removing the carrier board, removing a portion of the exposed surface of the circuit layer, so that the surface of the circuit layer is lower than the medium The surface of the electrical layer. 100118151 Form No. A0101 Page 17 of 23 1002030535-0