201023703 υ»υδυυ/ 29323twf.doc/n 六、發明說明： 【發明所屬之技術領域】 制是有關於 【先前技術】 ❹201023703 υ»υδυυ/ 29323twf.doc/n VI. Description of the invention: [Technical field to which the invention pertains] System is relevant [Prior Art] ❹
“目巧Ϊ半：體封裝技術中，線路基板（cimiit S,rate)是財制的騎元件之—。祕基板主要由 (patterned circuit) Cdielectric layer) =合而成。以製作線路的精細度而言，雷射製程相較於曝 光顯影製程有者較大的優勢，言之，她於透過以微影 形成的圖案化光阻製作出的圖案化線路而言，透過以雷射 製程在介電層形成的圖案化凹槽製作出的圖案化線路，具 有更佳的線路精細度。 然而，在製作圖案化線路中具有較大寬度的部分（例 如接墊）時，雷射製程有著速度慢的缺點。此外’在上述 電鑛製程巾’若透過電朗時形成具有較大寬度部分（例 如接墊）與具有較小寬度部分（例如導線），為了顧及具 有較大寬度部分之完整性’可能會使具有較小寬度部分產 生厚度過大的情形。此情形可能導致後續的蝕刻製程發生 具有較小寬度部分蝕刻不足，或具有較大寬度部分蝕刻過 度等餘刻不均的競爭性缺點現象。 【發明内容】 3 201023703 ⑽⑽υυζ 29323twfdoc/n 路的一T線路基板製程’可提高形成圖案化線 路的產出稼動率，並可大幅提升圖案化線路的平整产。 本發明提出-種線路基板製程。首先，在 二:介2層’並在介電層形成一圖案化凹槽。在圖案化凹/ 3:，成-圖案化線路。在介電層形成一第一開， 露出部分基板。在介電層形成具有、 的中第二開口暴露出第一開口及部分介電 曰且弟二開口暴露出部分圖案化 別在第-開口、第-開丨刀"電層。分 -接墊及一開口形成一導電塊、-第 墊及第一接墊。接著，移除罩幕層。 法為ίί發月之實施例中，上述之形成圖案化凹槽的方 -實補中，上述之在圖案細槽内形成 一=1匕=妓包_過化學鍵在圖案化凹槽内形成 在本發明之一實施例中， -圖案化線路的方法包括透過化内形成 且填滿圖案化凹槽:=。f"電鑛形成覆蓋介電層 形成一圖案化保留填滿圖案化凹槽的部分金屬層，以 在本發明之-實施例中， 口的方法為雷射。 《隹；丨甩層形成第一開 在本發明之-實施例中，上述之在介電層形成具有第 4 201023703 υδυδυυζ 29]2；3twf_doc/n 二開口及第三開口的罩幕層的方法包括在介電層形成一光 阻層以做為一罩幕層。透過曝光顯影在罩幕層形成第二開 口及第三開口。 在本發明之一實施例中，上述之在形成具有第二開口 及第三開口的罩幕層的步驟中，第二開口更暴露出部分圖 案化線路。"In the middle of the body packaging technology, the circuit board (cimiit S, rate) is the financial riding component - the secret substrate is mainly composed of (patterned circuit) Cdielectric layer) = to make the line fineness In general, the laser process has a greater advantage than the exposure and development process. In other words, she uses a laser process to create a patterned line through a patterned photoresist formed by lithography. The patterning groove formed by the electric layer creates a patterned line with better line fineness. However, when manufacturing a portion having a large width (for example, a pad) in the patterned line, the laser process has a slow speed. Disadvantages. In addition, 'in the above-mentioned electric ore processing towel', if it passes through the battery, it forms a part with a larger width (such as a pad) and a part with a smaller width (such as a wire), in order to take into account the integrity of a portion having a larger width. It may cause a case where the portion having a small width is excessively thick. This case may cause a subsequent etching process to occur with a small width portion of the underetch or a larger width partial etch. Excessive and non-existent competitive shortcomings. [Explanation] 3 201023703 (10) (10) υυζ 29323twfdoc / n road of a T circuit substrate process 'can improve the production rate of the patterned circuit, and can greatly enhance the patterned circuit The present invention proposes a circuit substrate process. First, in two layers: a layer of 'and a patterned recess in the dielectric layer. In the patterned recess / 3:, into - patterned lines. In the dielectric Forming a first opening to expose a portion of the substrate. The second opening in the dielectric layer has a first opening and a portion of the dielectric opening, and the second opening exposes a portion of the pattern to be in the first opening, the first The boring tool " electrical layer. The sub-pad and an opening form a conductive block, a pad and a first pad. Then, the mask layer is removed. In the embodiment of the ίί月, the above formation In the square-solid complement of the patterned groove, the above-mentioned forming a =1 匕 = _ _ over chemical bond in the patterned groove is formed in the patterned groove in an embodiment of the invention, - patterned circuit The method includes forming and filling the patterned concave through the inner cavity :=. f" The electric ore forming the covering dielectric layer forms a portion of the metal layer that is patterned to fill the patterned recess, in the embodiment of the invention, the method of the port is a laser. The first layer is formed in the embodiment of the present invention, wherein the method of forming a mask layer having a fourth 201023703 υδυδυυζ 29]2; 3twf_doc/n two openings and a third opening in the dielectric layer includes a dielectric layer Forming a photoresist layer as a mask layer. The second opening and the third opening are formed in the mask layer through exposure and development. In an embodiment of the invention, the forming is formed with the second opening and the third opening. In the step of masking the layer, the second opening exposes a portion of the patterned line.
❹ 在本發明之一實施例中，上述之分別在第一開口、第 二開口及第二開口形成導電塊、第一接塾及第二接墊的方 法為電鍍。 在本發明之一實施例中，上述之線路基板製程更包括 在形成罩幕層之前，在介電層上、圖案化線路層上及第一 開口内形成一第一電鍛種子層。在形成導電塊、第一接塾 及第二接墊之後’移除部分第二電鍍種子層。 在本發明之一實施例中，上述之基板具有一基板接 墊，且第一開口暴露出基板接墊。 在本發明之一實施例中’上述之介電層包括多顆觸媒 顆粒。 在本發明之一實施例中 米金屬顆粒。 在本發明之一實施例中 多個過渡金屬配位化合物。 在本發明之一實施例中 的材質包括過渡金屬氧化物 錯合物或過渡金屬螯合物。 ’上述之觸媒顆粒包括多個奈 ，上述之觸媒顆粒的材質包括 ’上述之過渡金屬配位化合物 、過渡金屬氮化物、過渡金屬 5 201023703 VWVWVV心 29323twf.doc/i 在本發明之一實施例中，上 的材質為選自於由H ^金屬配位化&物 銥、鐵、錳、鉻、錮、i ?金、錄、飽，、銘、姥、 組。 鎢釩、鈕、銦以及鈦所組成的群 在本發明之一實施例巾 凹槽的同時，更包括糾34之在介電層形成圖案化 ㈣圄括化抑的觸媒顆粒，以形成一活化 層於圖案化凹槽的内面。In one embodiment of the invention, the method of forming the conductive block, the first contact and the second pad in the first opening, the second opening and the second opening respectively is electroplating. In an embodiment of the invention, the circuit substrate process further includes forming a first electrically forged seed layer on the dielectric layer, the patterned circuit layer, and the first opening before forming the mask layer. A portion of the second plating seed layer is removed after forming the conductive bumps, the first pads, and the second pads. In an embodiment of the invention, the substrate has a substrate pad, and the first opening exposes the substrate pad. In one embodiment of the invention, the dielectric layer described above comprises a plurality of catalyst particles. In one embodiment of the invention, the rice metal particles. In one embodiment of the invention a plurality of transition metal coordination compounds. Materials in one embodiment of the invention include transition metal oxide complexes or transition metal chelates. The above-mentioned catalyst particles include a plurality of naphthalenes, and the material of the above-mentioned catalyst particles includes 'the above-mentioned transition metal complex compound, transition metal nitride, transition metal 5 201023703 VWVWVV core 29323 twf.doc/i in one embodiment of the present invention In the example, the upper material is selected from the group consisting of H ^ metal coordination & 铱, iron, manganese, chromium, strontium, i gold, recording, full, Ming, 姥, group. The group consisting of tungsten vanadium, button, indium and titanium is in the groove of one embodiment of the present invention, and further comprises a catalyst particle formed by patterning (4) in the dielectric layer to form a film. The active layer is on the inner face of the patterned groove.
圖荦實施例巾，上述之在圖案化凹槽内形成 圖案化線路的方法包括化學沉積法。 土於上述本發明的線路基板製程，分別透過雷射製 製作㈣化線狀具魏小寬度部分及 ;5:分，可提高形成圖案化線路的產出稼動 率，並可大幅提升圖案化線路的平整度。 與眘H本發明之上述特徵和優點能更錄，下文特 舉實施例，並配合所關式作詳細說明如下。 【實施方式】 圖1A至圖1K為本發明一實施例之線路基板製程的 剖視流程圖。首先，請參考圖1A，在—基板UG上形成一 ”電層1=0 ’並透過雷射在介電層12〇形成一圖案化凹槽 Π2。值彳于注意的是，在後續的製程將透過圖案化凹槽122 形成圖案化祕，而由雷射卿成的圖案化凹槽122可使 圖案化線路具有良好的精細度。 明參考圖1B，透過化學鏡在介電層m上及圖案化 6 201023703 υονονν/,ί, 29323twf. doc/π 凹槽122内形成—第一電鍍種子層13〇。第一電鍵種子片 130用以使後續的紐製程能夠糊進行。接著，請參^ 圖1C，透過電錄形成覆蓋介電層m且填滿圖案化凹样 122的-金屬層140。然後，請參考圖1D，透過姓刻移ς 覆蓋介電層120的部分金屬層14〇及覆蓋介電層12〇的部 分第-電鑛種子層130，並保留填滿圖案化凹槽122 分金屬層140，以形成一圖案化線路15〇。 ❹ 特別的是，在另一未繪示的實施例中，介電層可具有 分佈於其内的多個觸媒粒子。在透過雷射形成圖案化^ 的過程中，位於圖案化凹槽表面的觸媒粒子會被^化，二 形成一活化層於圖案化凹槽的内面。因此，在製造過程十 不必在介電層上及圖案化凹槽形成電鍍種子層，就可直接 以化學沉積法的方式在圖案化凹槽形成圖案化線路。 上述之觸媒顆粒包括多個奈米金屬顆粒，其中觸媒顆 粒的材質包括多個過渡金屬配位化合物。這些過渡金屬配 位化合物的材質包括過渡金屬氧化物、過渡金屬氮化物、 ® 過渡金屬錯合物或過渡金屬螯合物。更詳細而言，這些過 渡金屬配位化合物的材質為選自於由鋅、鋼、銀、金、^ 鈀、鉑、鈷、铑、銥、鐵、錳、鉻、鉬、鎢、釩、鈕、銦 以及鈦所組成的群組。舉例而言，這些觸媒顆粒例如是氧 化銅、氮化鋁、鈷鉬雙金屬氮化物（C〇2M〇3Nx)顆粒 金屬顆粒。 一 請參考圖1E’透過雷射在介電層120形成一第一開口 H1，以暴露出部分基板11〇的一基板接墊112。接著=靖 29323twf.doc/n 201023703 參考圖IF，透過化學錄在介電層 150上及第一開口 HI内形成_第二上、圖案化線路層 二電鑛種子層i3G，用以使後續的第 請參考圖ισ及圖ιΗ，在介電芦程此夠順利進行。 做為-罩幕層160 ’並透過曝光顯景;在且:以 第二開口 H2及-第三開口 H3 _卓幕層160形成一 開口 m、部分介電層120及部分扣暴露出第一 參 ❹ 開口 H3暴露出部分圖案化線路15〇及部:三 在本實施例’雖然第—開口 部分圖案化線路150被第二開^電層120及 化線路150及部分介電層12G $卩分圖案 因為第-開口 m、介電芦120及^幵口 Ή3暴露出’但 m-雷^^圖案化線路150上配置有 第-電鑛種子層130,，所以其並非 置有 請參考圖U，透過電齡別在第1暴口露 口 H2及第三開口陶成—導電塊m、-第接= ί後接著’ t參考圖1Jr，移除罩幕層160。 化線路^0的部^笛移除覆蓋部分介電層120及部分圖案 板1〇〇。 ° '刀第二電錄種子層130’，以得到一線路基 除，有鼓寬度區域精雷射移 其在ί實施觸線路基板製程， 、 寬度的第一接墊180及第二接墊190 古圖料⑪3^雷㈣成用以製作接墊的凹槽’因此可以提 同圖案化線路的產出稼動率。 8 201023703 29323twf.doc/n 此外’在本實施例的線路基板製程中，由於具有較小 面積的圖案化線路150並非是與具有較大面積的第一接塾 180及弟二接墊190同時透過電鍵而形成，所以可避免為 了顧及第一接墊180及一第二接墊190之完整性，而使圖 案化線路150產生厚度過大的情形發生。因此，可避免圖 案化線路150钱刻不足或第一接塾18〇及一第二接墊 姓刻過度等蝕刻不均的競爭性缺點現象。 ❿ 圖2為圖1K之線路基板的俯視圖。請參考圖2，透 過本實施例之線路基板製程製作出的線路基板1〇〇，其圖 案化線路150包括一第一導線152、一第二導線154、二第 三導線156及一第四導線158。第三導線156與第二接墊 do導通’且第四導線158與第一接墊18〇導通。 β綜上所述，本發明的線路基板製程，不利用雷射製程 而疋透過微影蝕刻製程形成具有大寬度的接墊，可以提高 =案化線路的產出稼動率。此外，湘雷射製程形成用以 ❹ ^作圖案化線路的凹槽，可使圖案化線路具有良好的精細 X。圖案化線路與接墊分別在不同的步驟中被製 電鑛或餘刻之區域的寬度差異過大而有4或: 均的現象，以提升圖案化線路的表面平整度。 本發已以實施例揭露如上，然、其並非用以限定 任何所屬技術領域中具有通常知識者，在 發明明之精神和範圍内，當可作些許之更動與潤飾，故本 之保護範圍當視後附之申請專利範圍所界定者為準。 9 201023703 υουουυζ. 29323twf. doc/ll 【圖式簡單說明】 圖1A至圖1K為本發明一實施例之線路基板製程的 剖視流程圖。 圖2為圖1K之線路基板的俯視圖。 【主要元件符號說明】 100 :線路基板 154 :第二導線 110 :基板 156 :第三導線 112 :基板接墊 158 :第四導線 120 :介電層 160 :罩幕層 122 :圖案化凹槽 170 :導電塊 130 :第一電鍍種子層 180 :第一接墊 130’ ：第二電鍍種子層 190 :第二接墊 140 :金屬層 H1 :第一開口 150:圖案化線路 H2 :第二開口 152 :第一導線 H3 :第三開口The embodiment of the invention, the method of forming a patterned line in the patterned recess, includes a chemical deposition process. In the above-mentioned circuit substrate manufacturing process of the present invention, respectively, the laser is used to make (4) the linear portion having the Wei small width portion and the 5: minute, which can improve the output rate of the patterned circuit and greatly increase the patterning line. Flatness. The above features and advantages of the present invention can be further exemplified, and the following specific embodiments will be described in detail below with reference to the details. [Embodiment] Figs. 1A to 1K are cross-sectional views showing a process of a circuit substrate according to an embodiment of the present invention. First, referring to FIG. 1A, an "electric layer 1 = 0" is formed on the substrate UG and a patterned recess Π 2 is formed on the dielectric layer 12 by laser. The value is noted in the subsequent process. Patterning is formed through the patterned grooves 122, and the patterned grooves 122 formed by the laser can provide good fineness of the patterned lines. Referring to FIG. 1B, through the chemical mirror on the dielectric layer m and Patterning 6 201023703 υονονν /, ί, 29323 twf. doc / π is formed in the groove 122 - the first plating seed layer 13 〇. The first key seed sheet 130 is used to enable the subsequent New Zealand process to paste. Then, please refer to 1C, a metal layer 140 covering the dielectric layer m and filling the patterned recess 122 is formed by electro-recording. Then, referring to FIG. 1D, a portion of the metal layer 14 covering the dielectric layer 120 is transferred by a surname. Covering a portion of the first-electrode seed layer 130 of the dielectric layer 12, and retaining the patterned trench 122 to form a patterned layer 15A. ❹ In particular, the other is not shown In an embodiment, the dielectric layer can have a plurality of catalyst particles distributed therein. During the formation of the patterning, the catalyst particles on the surface of the patterned groove will be formed, and an active layer will be formed on the inner surface of the patterned groove. Therefore, it is not necessary to be on the dielectric layer during the manufacturing process. The patterned groove forms a plating seed layer, and the patterned groove can be directly formed in the patterned groove by chemical deposition. The above-mentioned catalyst particles include a plurality of nano metal particles, wherein the material of the catalyst particles includes a plurality of Transition metal complexes. Materials of these transition metal complexes include transition metal oxides, transition metal nitrides, ® transition metal complexes or transition metal chelates. More specifically, these transition metal complexes The material is selected from the group consisting of zinc, steel, silver, gold, palladium, platinum, cobalt, rhodium, ruthenium, iron, manganese, chromium, molybdenum, tungsten, vanadium, niobium, indium, and titanium. The catalyst particles are, for example, copper oxide, aluminum nitride, cobalt molybdenum bimetallic nitride (C〇2M〇3Nx) particulate metal particles. Please refer to FIG. 1E' to form a first dielectric layer 120 through the laser. Opening H 1, to expose a substrate pad 112 of a portion of the substrate 11 。. Next = Jing 29323twf.doc / n 201023703 Referring to Figure IF, through the chemical recording on the dielectric layer 150 and the first opening HI formed _ second, The patterned circuit layer of the second electric ore seed layer i3G is used to make the subsequent reference to the figure ισ and the figure ιΗ, which is smooth enough in the dielectric reed. As the mask layer 160' and through the exposure display; And: forming an opening m by the second opening H2 and the third opening H3_the curtain layer 160, the partial dielectric layer 120 and the partial buckle exposing the first reference opening H3 to expose the partial patterned line 15 and the portion: In the present embodiment, the first opening portion patterning line 150 is divided by the second opening layer 120 and the layer 150 and the portion of the dielectric layer 12G $ because the first opening m, the dielectric reed 120 and the 幵The mouthpiece 3 is exposed to 'but the m-ray ^^ patterning line 150 is provided with the first-electro-mine seed layer 130, so it is not placed with reference to Figure U, through the electrical age in the first vent exposed H2 and the first The three openings are made into a conductive layer m, - the first connection = ί, and then the reference layer J1 is removed, and the mask layer 160 is removed. The portion of the circuit ^0 removes the portion of the dielectric layer 120 and the portion of the pattern plate 1''. ° 'Knife second record seed layer 130', in order to get a line base division, there is a drum width region fine laser beam shifting its implementation in the touch circuit substrate process, the width of the first pad 180 and the second pad 190 The picture material 113^Ray (4) is used to make the groove of the pad' so that the output rate of the patterned line can be improved. 8 201023703 29323twf.doc/n Further, in the circuit substrate process of the present embodiment, since the patterned line 150 having a small area is not simultaneously transmitted through the first interface 180 and the second pad 190 having a large area. The key is formed, so that the thickness of the patterned line 150 is excessively large in order to take into account the integrity of the first pad 180 and the second pad 190. Therefore, it is possible to avoid the competitive disadvantage of the etching unevenness such as insufficient patterning of the patterned circuit 150 or the first interface 18〇 and a second pad. Figure 2 is a plan view of the circuit substrate of Figure 1K. Referring to FIG. 2, a circuit substrate 1 manufactured by the circuit substrate process of the embodiment has a patterned wiring 150 including a first conductor 152, a second conductor 154, two third conductors 156, and a fourth conductor. 158. The third wire 156 is electrically connected to the second pad do and the fourth wire 158 is electrically connected to the first pad 18A. In summary, the circuit substrate process of the present invention can form a pad having a large width by using a laser lithography process without using a laser process, and can improve the yield of the case circuit. In addition, the Xiang laser process forms a groove for patterning the line, so that the patterned line has a good fineness X. The patterning line and the pad are respectively different in the steps of making the electric ore or the remaining portion of the gap in the different steps and having a 4 or a uniform phenomenon to improve the surface flatness of the patterned line. The present invention has been disclosed in the above embodiments, but it is not intended to limit any of the ordinary knowledge in the art, and in the spirit and scope of the invention, when some changes and refinements can be made, the scope of protection is considered to be The scope defined in the appended patent application shall prevail. 9 201023703 υουουυζ. 29323 twf. doc/ll BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1K are cross-sectional views showing a process of a circuit substrate according to an embodiment of the present invention. 2 is a top plan view of the circuit substrate of FIG. 1K. [Main component symbol description] 100: circuit substrate 154: second wire 110: substrate 156: third wire 112: substrate pad 158: fourth wire 120: dielectric layer 160: mask layer 122: patterned groove 170 : Conductive block 130 : first plating seed layer 180 : first pad 130 ′: second plating seed layer 190 : second pad 140 : metal layer H1 : first opening 150 : patterned line H2 : second opening 152 : First wire H3: third opening