KR20090065117A - Ultra-thin substrate for semiconductor package, and fabrication method of the same, fabrication method for semiconductor device thereby - Google Patents

Abstract

A ultra-thin semiconductor package substrate, a manufacturing method of a semiconductor package substrate, and a manufacturing method of a semiconductor device by using the same are provided to reduce a thickness of a substrate by eliminating a CCL(Copper-Clad Laminate). A gold plating process and a nickel plating process are sequentially performed to fill a region from which a first photoresist layer is removed. A copper-plated layer is electrically connected with a nickel-plated layer exposed through a second photoresist region. The copper-plated layer is formed to cover a surface including a second photoresist(130). The copper-plated layer includes a flat top surface. A third photoresist layer is formed on the copper-plated layer. The exposed copper-plated layer is removed by performing an etch process using a third photoresist. A part of a fourth photoresist layer is removed by an exposure-development process in order to expose a part of a circuit pattern. A fourth photoresist(160) is removed to connect electrically the nickel-plated layer and the gold-plated layer with the exposed circuit pattern.

Description

Ultra-thin substrate for semiconductor package, and fabrication method of the same, fabrication method for semiconductor device

The present invention relates to a semiconductor package substrate, a method for manufacturing a semiconductor package substrate, and a method for manufacturing a semiconductor device using the same. The present invention relates to a semiconductor package substrate, a method of manufacturing a semiconductor package substrate, and a method of manufacturing a semiconductor device using the same, which can lower and significantly improve planar integration by not forming a plating lead wire separately.

For manufacturing a large-capacity memory semiconductor device, it can be classified into a qualitative integration method of maximizing the number of cells per unit area of a semiconductor chip, and a quantitative integration method of maximizing the number of semiconductor chips stacked per unit height in a packaging step.

Of these, the qualitative integration method has recently been developed to approach the limit of atomic size, which is the limit of 30 nano processes, and the quantitative integration method has a thickness of about 50 μm in the thickness of the semiconductor chip and the thickness of the package substrate. When using CCL (copper clad laminate), it is generally accepted that it is difficult to control the thickness below 80 μm even when using PPG (prepreg), which is the latest method.

On the other hand, in the field of mobile devices using semiconductor memory, thinner and higher capacity semiconductor devices are required. In order to cope with this, it is important to reduce the integration density and thickness of semiconductor chips. There is a need for the development of package substrates with thicknesses thinner than [mu] m.

Examples of manufacturing a semiconductor package substrate using a conventional CCL include Korean Patent Laid-Open Publication No. 2004-110531, Korean Patent Laid-Open Publication No. 2000-23414, and the case of using the PPG method. 2007-0000645, and the like.

In the conventional method of manufacturing a semiconductor package substrate, both the CCL method and the PPG method require a base substrate including an insulating layer, and thus, there is a limit in thickness reduction and electrolytic gold plating to form solder ball pads and wire bonding pads. Since the plating lead wire had to be formed separately to carry out the process, there were various limitations in improving the planar integration degree of the package substrate itself.

However, in the above-mentioned Republic of Korea Patent Application Publication No. 2004-110531 and Republic of Korea Patent Publication No. 2000-23414, the center portion of the substrate while cutting the plate center portion in order to arrange the plating lead wire to the center portion and to form a window portion to which the semiconductor chip is bonded to the center portion Although a method of simultaneously cutting a plating lead wire has been used, this invention, although removed, is still more advanced than other inventions in that it requires a process of forming a separate plating lead wire in a circuit pattern forming process during a substrate manufacturing process. There is room for improvement.

In addition, as the semiconductor package substrate becomes thinner, the rigidity of the substrate is lowered, so that the substrate is easily bent when used in an actual packaging process, and thus, there is a problem that it is very difficult to align and control at an exact position in the packaging process.

To this end, a method in which a stainless carrier is separately mounted and used on a semiconductor package substrate is used, which requires a separate process, which acts as a factor of increasing the manufacturing cost of a semiconductor device.

The problem to be solved by the present invention is not to use a base substrate such as CCL, it is possible to manufacture an ultra-thin semiconductor package substrate of 80㎛ or less, and also do not need to form a separate plating lead wire, and also to use a stainless steel carrier An ultra-thin semiconductor package substrate, and a method for manufacturing the same.

In addition, the present invention further aims to provide a method of manufacturing an actual semiconductor device using such a substrate.

The objects to be achieved by the present invention are not limited to the above-mentioned objects, and other objects not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, a method of manufacturing an ultra-thin semiconductor package substrate according to a first embodiment of the present invention includes: (a) forming a first photoresist layer on a release layer of a carrier plate on which a release layer is formed; Removing a part of the first photoresist layer to expose a part of the release layer through a developing process; (b) sequentially performing a gold plating process and a nickel plating process to fill a region from which the first photoresist layer has been removed; Forming a nickel plating layer and a first gold plating layer; (c) forming a second photoresist layer on the remaining first photoresist layer and the first nickel plating layer, and exposing the second photoresist through an exposure-development process. Removing a portion of the layer to expose the first nickel plated layer; (d) electrically plating the first nickel plated layer exposed through the second photoresist region removed by copper plating. Forming a copper plating layer covering a surface on which the second photoresist is formed so as to be energized and having a flat top surface; (e) forming a third photoresist layer on the copper plating layer and applying a circuit pattern through an exposure-development process. Removing the remaining third photoresist region while leaving a corresponding region; (f) forming a circuit pattern by removing the exposed copper plating layer by performing an etching process on the remaining third photoresist with an etching mask; g) removing the remaining third photoresist, and then forming a fourth photoresist layer covering the circuit pattern to fill a region between the circuit patterns and having a flat top surface; (h) an exposure-development process Removing a portion of the fourth photoresist layer so that a portion of the circuit pattern is exposed through the (i) nickel plating and gold plating processes sequentially So that the said circuit patterns and conducting exposure sihayeo comprises a step of forming a second nickel-plated layer and the second plated layer inside the fourth photo resist is removed area.

According to a second aspect of the present invention, there is provided a method of manufacturing an ultra-thin semiconductor package substrate, which includes: (a) forming a first photoresist layer on a release layer of a carrier plate on which a release layer is formed; Removing a part of the first photoresist layer to expose a part of the release layer through a developing process; (b) sequentially performing a gold plating process and a nickel plating process so that the removed region of the first photoresist layer is filled; Forming a nickel plating layer and a first gold plating layer; (c) forming a second photoresist layer on the remaining first photoresist layer and the first nickel plating layer, and exposing the second photoresist through an exposure-development process. Exposing the first nickel plating layer by removing a portion of the layer; (d) forming an electrolytic copper plating layer in the second photoresist region removed by electrolytic copper plating, and then electrolytic or electroless Performing electrolytic copper plating to form an electrolytic or electroless copper plating layer on the second photoresist and on the electrolytic copper plating layer; (e) forming a third photoresist on the copper plating layer and subjecting the copper through an exposure-development process Removing the remaining third photoresist region while leaving a region where a circuit pattern is to be formed while exposing a plating layer; (f) a circuit is formed in the third photoresist region removed to conduct electricity with the exposed copper plating layer by electrolytic copper plating; Forming a pattern; (g) removing the remaining third photoresist, and performing an etching process to remove the copper plating layer below the third photoresist removed in this step and to expose the second photoresist layer below Thereby electrically separating the circuit patterns from each other; (h) a fourth photoresist layer on the exposed second photoresist layer and the circuit pattern; Process to remove the portions of the fourth photoresist layer such that a portion of the circuit pattern exposed through the development step-forming exposure, and; And (i) forming a second nickel plating layer and a second gold plating layer which are energized with the circuit pattern in the fourth photoresist region removed by sequentially performing a nickel plating and a gold plating process.

The ultra-thin semiconductor package substrate and its manufacturing method according to an embodiment of the present invention does not require CCL or PPG (Prepreg), it is possible to manufacture an ultra-thin semiconductor package substrate of 80㎛ or less, and also to form a separate plating lead wire It is possible to provide a method for producing a breakthrough semiconductor package substrate which does not need to use stainless steel carriers.

Hereinafter, a method of manufacturing the ultra-thin semiconductor package substrate of the present invention will be described with reference to the accompanying drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, only the present embodiments to make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

In addition, in the drawings, the size and thickness of layers and films or regions are exaggerated for clarity of description, and when any film or layer is described as being formed "on" of another film or layer, It may be directly on top of the other film or layer, and a third other film or layer may be interposed therebetween.

1A to 1O are cross-sectional views illustrating a method of manufacturing an ultra-thin semiconductor package substrate according to a first embodiment of the present invention.

In order to manufacture the ultra-thin semiconductor package substrate according to the first embodiment of the present invention, first, a carrier plate 100 is prepared (see FIG. 1A), and a release layer 110 is formed on the carrier plate 100. Form (see FIG. 1B).

At this time, the carrier plate 100 is preferably a conductive metal material, for example, covered with a foil (foil) of copper (Cu), the overall thickness is 100 ㎛ considering the role of the carrier of the substrate to be manufactured It is preferable to have the above thickness.

The carrier plate 100 serves to support a package substrate having a thickness of 80 μm or less, which is finally manufactured in the present invention, from being easily bent when applied in an actual package process.

In addition, the carrier plate 100 serves as an electrode when the electroplating process (copper plating, gold plating) is performed in the present invention.

The release layer 110 serves to easily release the package substrate formed on the release layer 110 later from the carrier plate 100 and the copper of the carrier plate 100 in a gold plating process to be performed later. It serves as a kind of diffusion barrier for preventing the component from diffusing into the gold plating layer.

As a material for forming the release layer 110, the bonding force with the carrier plate 100 must be greater than the bonding force with the first photoresist and the gold plating layer to be formed in the next process (the release layer is also removed when the carrier plate is removed. Should be separated together with the carrier plate), the copper component of the carrier plate 100 should be a material that can prevent the diffusion into the gold plated layer and itself should also be a material that does not diffuse into the gold plated layer, and a material having electrical conductivity.

In the present invention, the chromium (Cr) film is formed as the release layer 110, but any material that can satisfy the above properties may be used, and examples thereof include nickel (Ni) or copper (Cu). have.

The thickness of the release layer 110 should be determined to such an extent that it can perform the above function, preferably 10 μm or less.

Next, the first photoresist layer 120 is formed on the release layer 110 (see FIG. 1C), and an exposure and development process is performed to form the first photoresist layer 120. The partial region is removed (see FIG. 1D).

In the region where the first photoresist layer 120 is removed, the release layer 110 under the exposed portion is exposed. For reference, in FIG. 1D, reference numeral 125 denotes a region in which a portion of the first photoresist layer 120 is removed and the lower release layer 110 is exposed.

A method of forming the first photoresist layer 120 may be performed by applying and drying a liquid photoresist or drying the photoresist in a dry film at a constant pressure on the release layer 110. The lamination method may be selected. The first method is also acceptable, but the latter method may be selected in consideration of the thickness uniformity of the first photoresist layer 120 formed and the resolution during exposure.

Next, gold is applied through electroplating while applying current through the carrier plate 100 on the release layer 110 of the region 125 from which the first photoresist 120 is removed. plating) and nickel plating (Ni-plating) sequentially (see FIG. 1E).

At this time, the thickness of the layer to be plated is preferably 1 to 15㎛ each.

The first gold plating layer 126 and the first nickel plating layer 127 are formed in the region 125 from which the first photoresist has been removed through the electroplating process, and the first gold plating layer 126 is a semiconductor packaging process later. This is the area where solder balls are formed.

As described above, in the conventional package substrate manufacturing process, the solder ball is formed first when the circuit pattern is formed and the gold plating process is performed. In the present invention, the gold plating process is performed first to form one from the bottom to the top of the substrate. It is characterized by.

As shown in FIG. 1E, when the gold plating-nickel plating process is performed, an upper surface of the upper first nickel plating layer 127 is substantially flat with an upper surface of the first photoresist layer 120.

Next, a second photoresist layer 130 is formed on the first photoresist layer 120 and the first nickel plating layer 127 (see FIG. 1F), and the first nickel plating layer 127 is formed through an exposure and development process. ) May be removed to partially or partially expose the second photoresist layer 130 (see FIG. 1G). For reference, reference numeral 135 denotes an area where the second photoresist layer 130 is removed to expose the lower first nickel plating layer 127.

The method of forming the second photoresist layer 130 is the same as the method of forming the first photoresist layer 120 (solution-drying method, dry film pressing method).

In this case, the region 135 removed from the second photoresist layer 130 may be regarded as a region corresponding to a solder ball pad in the related art. However, in the present invention, the signal transmission circuit pattern and the pad region circuit pattern may be considered. Since these are formed in different dimensions (height) there is an unsuitable face to fully respond.

Next, a copper plating process is performed to energize the first plating layer 127 of the region 135 from which the second photoresist has been removed, and to fill all or most of the region 135 from which the second photoresist has been removed. An upper surface of the second photoresist layer 130 may be formed to form a copper plating layer 140 having a flat upper surface (see FIG. 1H).

At this time, the copper plating layer 140 is formed by selectively or in parallel with the electroplating or electroless plating, preferably, the second photoresist is removed by performing electroplating while applying current to the carrier plate 100. After filling the inside of the region 135 with copper, electroless copper plating is performed to perform electroless copper plating so that the upper portion of the second photoresist layer 130 is covered.

3A and 3B show another method for forming the copper plating layer 140 of the first embodiment.

Referring to FIG. 1G, after forming the electroless copper plating layer 136 with a conformal thin thickness on the upper portion of the second photoresist 130 and the exposed first nickel plating layer 127 (step 1G), 3A), an electroplating layer 137 may be formed by electroplating to form a copper plating layer 140 (FIG. 3B).

Next, a third photoresist layer 150 is formed on the copper plating layer 140 (see FIG. 1I), and a portion of the third photoresist 150 corresponding to a circuit pattern to be formed through an exposure and development process is formed. The remaining third photoresist 150 is removed while leaving only the bay (see FIG. 1J). In FIG. 1J, reference numeral 155 denotes an area where the third photoresist 150 is removed to expose the lower copper plating layer 140.

At this time, the method of forming the third photoresist 150 is the same as the method of forming the first photoresist layer 120 described above (liquid type or film type).

Next, the copper plating layer 140 exposed by etching may be formed by using the remaining third photoresist 150 as an etching mask. Etch until exposed (see FIG. 1K). For reference, in FIG. 1K, reference numeral 145 denotes a region in which the copper plating layer 140 is removed by etching.

In this process, the etching process may be selected from wet etching or dry etching, preferably by wet etching.

All of the copper plating layers 140 exposed through the present process are etched, and the remaining copper plating layers 141 become circuit patterns.

Specifically, the upper region of the remaining copper plating layer 140 becomes a signal transmission circuit pattern, fills the inside of the region where the second photoresist layer 130 is removed, and the copper plating layer in contact with the nickel plating layer 127. It serves as a contact layer for electrically conducting the signal transmission circuit pattern and the nickel plating layer 127 below.

Next, the remaining third photoresist layer 150 is removed (see FIG. 1L), and the region 145 from which the copper plating layer is removed and the remaining copper plating layer 141, that is, the upper portion of the circuit pattern are removed. The fourth photoresist layer 160 is formed to cover all of them (see FIG. 1M).

In this case, the method of forming the fourth photoresist layer 160 is the same as the method of forming the first photoresist layer 120.

Next, the partial region of the fourth photoresist layer 160 is removed to expose the partial region (the region corresponding to the wire bonding pad portion) of the copper plating layer 141 remaining through the exposure-development process (FIG. 1N). Reference). For reference, in FIG. 1N, reference numeral 165 denotes a region where the fourth photoresist 160 is removed.

Next, the second nickel plating layer 167 and the second gold plating layer 166 are sequentially formed on the exposed circuit pattern 141 of the region 165 from which the fourth photoresist is removed by performing an electroplating process. (See Figure 1o)

The second gold plating layer 166 formed in the present process is a region that is later wire bonded with the semiconductor chip, and its thickness and formation method are similar to those described with reference to FIG. 1E.

The nickel plating and gold plating processes in this process are performed by electroplating, that is, when a current is applied to the carrier plate 100, the current is transferred from the carrier plate 100 to the chromium release layer 110 to the first gold plating layer ( 126) → the first nickel plating layer 127 → the circuit pattern 141, so that electroplating is possible.

Referring to the plating process described above, that is, the electroplating process of FIG. 1E and the electroplating process of FIG. 1O, the present invention does not require a plating lead wire for electroplating as in the prior art, but through a conductive pattern existing inside the substrate. It can be seen that electroplating can be performed.

So far, the manufacturing method of the ultra-thin semiconductor package substrate according to the first embodiment of the present invention has been described with reference to FIGS. 1A to 1O. Hereinafter, a semiconductor device is manufactured using the ultra-thin semiconductor package substrate using additional drawings. A process to be performed, that is, a packaging process will be described.

1P to 1S are cross-sectional views illustrating an actual package process, that is, a process of manufacturing a semiconductor device using an ultra-thin semiconductor package substrate manufactured by the above method.

In order to manufacture the semiconductor device, the semiconductor chip 170 is adhered to the fourth photoresist layer 160 following the process of FIG. 1O (see FIG. 1P). In this case, the region to which the semiconductor chip 170 is bonded may be a region other than the region where the second gold plating layer 166 is formed.

Thereafter, wire bonding is performed between the pad portion of the semiconductor chip 170 and the second gold plating layer 166 by using a bonding wire 175, and the semiconductor chip 170 and the bonding wire 175 are bonded to each other. It is packaged using a polymer resin such as an epoxy molding compound (EMC) to cover all of them (see FIG. 1Q).

Finally, the carrier plate 100 is removed together with the release layer 110 and the first gold plating layer 126 is exposed (see FIG. 1R), so that the solder balls 190 correspond to the first gold plating layer 126. When placed (see FIG. 1S), the manufacturing process of the semiconductor device in which the packaging process is completed is completed.

Hereinafter, a method of manufacturing an ultra-thin semiconductor package substrate according to a second embodiment of the present invention will be described.

2A to 2N are cross-sectional views illustrating a method of manufacturing an ultra-thin semiconductor package substrate according to a second exemplary embodiment of the present invention.

However, since the process of FIGS. 2A to 2G is the same as the process of FIGS. 1A to 1G of the first embodiment described above, the description thereof will be omitted, and only the subsequent processes will be described below.

In order to manufacture the ultra-thin semiconductor package substrate according to the second embodiment of the present invention, in the next step of the process of Figure 2g, the region 135 from which the second photoresist layer is removed is filled with the electrolytic copper plating 251 (FIG. 2H), A base copper layer 252 is formed through electroless copper plating and / or electrolytic copper plating (FIG. 2I). The base copper plating layer 252 may be covered and a third photoresist layer 250 having a flat upper surface is formed (see FIG. 2J).

At this time, the method of forming the third photoresist 250 is the same as described in the first embodiment.

Thereafter, the third photoresist 250 region of the region 255 in which the circuit pattern is to be formed is removed through an exposure and development process (see FIG. 2K). In FIG. 2K, reference numeral 255 denotes a region where the third photoresist is removed.

Next, an electrolytic copper plating process is performed to form a circuit pattern 260 inside the region 255 from which the third photoresist is removed (FIG. 2L).

 Thereafter, the third photoresist 250 is removed (FIG. 2M; the removed region is indicated by reference numeral 256), and a flash etching process is performed to remove foreign substances on the surface of the circuit pattern and the third photoresist removed by the FIG. 2M process. (25) The base copper layer 252 is removed from the bottom (FIG. 2n). As a result, the lower second photoresist layer 130 is exposed.

Next, the fourth photoresist layer 270 is formed to cover the portion 256 and the upper portion of the circuit pattern 260 (FIG. 2O).

At this time, the method of forming the fourth photoresist layer 270 is the same as described in the first embodiment.

Next, the partial region of the fourth photoresist layer 260 is removed to expose the partial region (the region corresponding to the wire bonding pad portion) of the circuit pattern 260 through the exposure-development process (see FIG. 2P). For reference, in FIG. 2P, reference numeral 275 denotes a region in which the fourth photoresist 270 is removed.

Next, an electroplating process is performed to sequentially form the second nickel plating layer 267 and the second gold plating layer 266 on the exposed circuit pattern 260 of the region 275 from which the fourth photoresist has been removed. (See Figure 1q)

The gold plated layer 266 formed in the present process is a region that is later wire bonded with the semiconductor chip, and its thickness and formation method are similar to those described with reference to FIG. 1E.

Up to now, the method of manufacturing the ultra-thin semiconductor package substrate according to the second embodiment of the present invention has been described with reference to FIGS. 2A to 2N. The process, that is, the package process, is performed in the same process as shown in FIGS. 1P-1S above.

The thickness of the 1st photoresist-the 4th photoresist in this invention demonstrated so far is 1-20 micrometers, the thickness of a copper plating layer is 1-20 micrometers, and the thickness of the nickel plating layer + gold plating layer is 1-15 micrometers, It can be seen that even when the maximum thicknesses are combined, it is only about 80 μm, and thus, it is possible to manufacture a semiconductor package substrate that greatly exceeds the thickness limit of the semiconductor package substrate, which was considered as the limit of the conventional 80 μm.

In addition, the first to fourth photoresists used in the present invention may be used as the terms of solder resist and dry film resist in the manufacturing process of the substrate, and the term is used collectively as a material capable of constant patterning by the exposure-developing process. Should be understood as.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings and tables, the present invention is not limited to the above embodiments, but may be manufactured in various forms, and common knowledge in the art to which the present invention pertains. Those skilled in the art can understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

1A to 1S are cross-sectional views illustrating a method of manufacturing an ultra-thin semiconductor package substrate and a method of manufacturing a semiconductor device using the same, according to the first embodiment of the present invention.

2A to 2Q are cross-sectional views illustrating a method of manufacturing an ultra-thin semiconductor package substrate and a method of manufacturing a semiconductor device using the same, according to the second embodiment of the present invention.

3A and 3B show another method for forming the copper plating layer 140 of the first embodiment.

Claims (16)

(a) forming a first photoresist layer on the release layer of the carrier plate having a release layer formed on one surface, and removing a portion of the first photoresist layer to expose a portion of the release layer through an exposure-development process; Process of doing; (b) forming a nickel plating layer and a gold plating layer by sequentially performing a gold plating process and a nickel plating process so that the region where the first photoresist layer is removed is filled; (c) forming a second photoresist layer on the remaining first photoresist layer and the nickel plating layer, and exposing the nickel plating layer by removing a portion of the second photoresist layer through an exposure-development process; ; (d) forming a copper plating layer having a flat upper surface and covering the surface on which the second photoresist is formed so as to be electrically energized with the nickel plating layer exposed through the second photoresist region removed by copper plating; (e) forming a third photoresist layer on the copper plating layer, leaving a region corresponding to the circuit pattern through an exposure-development process, and removing the remaining third photoresist region; (f) etching the remaining third photoresist with an etching mask to remove the exposed copper plating layer to form a circuit pattern; (g) after removing the remaining third photoresist, forming a fourth photoresist layer covering the circuit pattern to fill a region between the circuit patterns and having a flat top surface; (h) removing a portion of the fourth photoresist layer to expose a portion of the circuit pattern through an exposure-development process; (i) forming a nickel plated layer and a gold plated layer in a region in which the fourth photoresist is removed so as to conduct nickel plating and gold plating processes sequentially so that the exposed circuit pattern is energized; Way. (a) forming a first photoresist layer on the release layer of the carrier plate having a release layer formed on one surface, and removing a portion of the first photoresist layer to expose a portion of the release layer through an exposure-development process; Process of doing; (b) forming a nickel plating layer and a gold plating layer by sequentially performing a gold plating process and a nickel plating process so that the removed region of the first photoresist layer is filled; (c) forming a second photoresist layer on the remaining first photoresist layer and the nickel plating layer, and exposing the nickel plating layer by removing a portion of the second photoresist layer through an exposure-development process; ; (d) forming an electrolytic copper plating layer on the second photoresist region removed by electrolytic copper plating, and then electrolytic or electroless copper plating to form an electrolytic or electroless copper plating layer on the second photoresist and on the electrolytic copper plating layer. Forming step; (e) forming a third photoresist on the copper plating layer and exposing the copper plating layer through an exposure-development process, leaving a region where a circuit pattern is to be formed and removing the remaining third photoresist region; (f) forming a circuit pattern on the third photoresist region removed by conducting electrolytic copper plating so as to conduct electricity with the exposed copper plating layer; (g) removing the remaining third photoresist, and performing an etching process to remove the copper plating layer below the third photoresist removed in this step and to expose the second photoresist layer below the circuit pattern. Electrically separating each other; (h) forming a fourth photoresist layer on the exposed second photoresist layer and the circuit pattern and removing a portion of the fourth photoresist layer to expose a portion of the circuit pattern through an exposure-development process; fair; And and (i) forming a nickel plating layer and a gold plating layer which are energized with the circuit pattern in the fourth photoresist region removed by sequentially performing the nickel plating and gold plating processes. The method according to claim 1 or 2, The release layer is chromium (Cr), nickel (Ni) or copper (Cu) manufacturing method of the ultra-thin semiconductor package substrate, characterized in that. The method according to claim 1 or 2, The carrier plate is a method of manufacturing an ultra-thin semiconductor package substrate, characterized in that having a thickness of 100㎛ or more. The method according to claim 1 or 2, And the carrier plate is covered with a copper (Cu) metal foil. The method according to claim 1 or 2, The first photoresist, the second photoresist, and the fourth photoresist layer may be formed through a solution coating and drying process, or may be formed by laminating a film. . The method according to claim 1 or 2, The nickel plating process and the gold plating process is a method of manufacturing a semiconductor package substrate, characterized in that the electroplating. The method according to claim 1 or 2, The copper plating process is a method of manufacturing a semiconductor package substrate, characterized in that the electroplating, electroless plating is carried out selectively or in parallel. The method according to claim 1 or 2, The third photoresist layer is a method of manufacturing a semiconductor package substrate, characterized in that formed through the solution coating and drying process, respectively, or formed by laminating a film form. The method of claim 1, The etching process is a method of manufacturing an ultra-thin semiconductor package substrate, characterized in that the wet etching or dry etching process. The method of claim 7, wherein The electroplating process is carried out by applying a current to the carrier plate portion manufacturing method of an ultra-thin semiconductor package substrate. The method of claim 8, The electroplating process is carried out by applying a current to the carrier plate portion manufacturing method of an ultra-thin semiconductor package substrate. (A) to (i) process of claim 1; (j) adhering a semiconductor chip onto the fourth photoresist that does not overlap with the wire bonding pad portion; (k) connecting the wire bonding pad portion and the semiconductor chip with a bonding wire; (l) a step of packaging the semiconductor chip and the bonding wire using a polymer resin (m) releasing the carrier plate from the first photoresist with a release layer to expose the solder ball pad region; and (n) forming a solder ball in the exposed solder ball pad region. (A) to (g) the process of claim 2; (h) bonding a semiconductor chip onto the fourth photoresist that does not overlap with the wire bonding pad portion; (i) connecting the wire bonding pad portion and the semiconductor chip with a bonding wire; (j) a process of packaging the semiconductor chip and the bonding wire using a polymer resin (k) releasing the carrier plate from the first photoresist with a release layer to expose the solder ball pad region; (l) forming a solder ball in the exposed solder ball pad region. An ultra-thin semiconductor package substrate produced by the method of claim 1. A semiconductor device manufactured by the method of claim 13 or 14.

Images