CN102762039B - Circuit board and manufacturing method thereof - Google Patents
Circuit board and manufacturing method thereof Download PDFInfo
- Publication number
- CN102762039B CN102762039B CN201110322604.4A CN201110322604A CN102762039B CN 102762039 B CN102762039 B CN 102762039B CN 201110322604 A CN201110322604 A CN 201110322604A CN 102762039 B CN102762039 B CN 102762039B
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- Prior art keywords
- layer
- conductive layer
- blind hole
- line
- wiring board
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 239000003054 catalyst Substances 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000005234 chemical deposition Methods 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 238000004381 surface treatment Methods 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 238000007788 roughening Methods 0.000 claims description 4
- 239000002893 slag Substances 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 238000003825 pressing Methods 0.000 claims description 3
- 238000004073 vulcanization Methods 0.000 abstract description 4
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000001569 carbon dioxide Substances 0.000 description 2
- 229910002092 carbon dioxide Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Landscapes
- Manufacturing Of Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The invention discloses a circuit board and a manufacturing method thereof. The method is to provide a substrate having a circuit layer thereon. A dielectric layer is formed on a substrate. The dielectric layer covers the circuit layer and is provided with a blind hole exposing a part of the circuit layer. Next, a cured layer is conformally formed on the dielectric layer. Then, a patterned mask layer is formed on the cured layer. The patterned mask layer exposes the blind via and a portion of the cured layer. And then, forming a catalyst layer on the vulcanization layer and the circuit layer exposed by the patterned mask layer. Subsequently, the patterned mask layer and the vulcanized layer below the patterned mask layer are removed. Then, a first chemical deposition is performed to form a first conductive layer conformally on the catalyst layer. And performing second chemical deposition to form a second conductive layer on the first conductive layer, wherein the second conductive layer covers the first conductive layer. The second conductive layer fills the blind holes.
Description
Technical field
The present invention relates to a kind of wiring board and preparation method thereof, and particularly relate to a kind of wiring board reduced costs and preparation method thereof.
Background technology
In recent years, along with making rapid progress of electronic technology, coming out one after another of high-tech electronic industry, makes electronic product more humane, with better function constantly weed out the old and bring forth the new, and designs towards light, thin, short, little trend.Usually can configure for installing electronic elements wiring board thereon in these electronic products.
In general circuit board manufacturing process, the normally first substrate with first line layer forms dielectric layer thereon.Then, the blind hole exposing part first line layer is formed in the dielectric layer.Then, the first line layer exposed at dielectric layer and blind hole forms layers of copper.Then, layers of copper forms patterned mask layer.Afterwards, take patterned mask layer as etching mask, etching process is carried out to layers of copper, to form the second line layer.
In above-mentioned circuit board manufacturing process, owing to lithographic fabrication process and etching process need be carried out when forming the second line layer, therefore must spend higher cost, and the etchant used can to environment.In addition, because layers of copper is poor for the adhesive force of dielectric layer, the therefore easy problem causing reliability not good from dielectric layer stripping.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of wiring board, it can reduce production cost effectively.
Another object of the present invention is to provide a kind of wiring board, it has higher reliability.
For reaching above-mentioned purpose, the present invention proposes a kind of manufacture method of wiring board, and it first provides the substrate it with line layer.Then, substrate forms dielectric layer.Dielectric layer covers line layer, and has the blind hole exposing part line layer.Then, sulfuric horizon is conformally formed on the dielectric layer.Then, sulfuric horizon forms patterned mask layer.Patterned mask layer exposes blind hole and partial vulcanization layer.Then, the sulfuric horizon exposed in patterned mask layer and line layer form the first catalyst layer.Subsequently, the sulfuric horizon below patterned mask layer and patterned mask layer is removed.Then, the first chemical deposition is carried out, to be conformally formed the first conductive layer on catalyst layer.Afterwards, carry out the second chemical deposition, to form the second conductive layer on the first conductive layer, the second conduction covering first conductive layer.In addition, the second conductive layer fills up blind hole.
According to the manufacture method of the wiring board described in the embodiment of the present invention, the formation method of above-mentioned dielectric layer is such as first carry out pressing step, and to form dielectric layer and metal level on substrate, its dielectric layer is between substrate and metal level.Then, metal level is removed.Afterwards, carry out laser drill step, to form blind hole in dielectric layer.
According to the manufacture method of the wiring board described in the embodiment of the present invention, above-mentioned after formation blind hole and before formation sulfuric horizon, the line layer that can also expose dielectric layer and blind hole carries out surface treatment.
According to the manufacture method of the wiring board described in the embodiment of the present invention, above-mentioned surface treatment is such as carry out remove photoresist slag (desmear) manufacture craft and/or roughening manufacture craft.
According to the manufacture method of the wiring board described in the embodiment of the present invention, the material of above-mentioned catalyst layer is such as palladium.
According to the manufacture method of the wiring board described in the embodiment of the present invention, the formation method of above-mentioned catalyst layer is such as carry out the 3rd chemical deposition.
According to the manufacture method of the wiring board described in the embodiment of the present invention, the formation method of above-mentioned sulfuric horizon is such as carry out vulcanizing treatment to dielectric layer.
The present invention separately proposes a kind of wiring board, and it comprises substrate, dielectric layer, sulfuric horizon and second line layer it with first line layer.Dielectric layer to be configured on substrate and to cover first line layer, and dielectric layer has blind hole.Blind hole exposes part first line layer.Sulfuric horizon is conformally configured on part of dielectric layer.Second line layer is configured on the first line layer that sulfuric horizon and blind hole expose.Second line layer comprises catalyst layer, the first conductive layer and the second conductive layer.Catalyst layer is conformally configured on the first line layer that sulfuric horizon and blind hole expose.First conductive layer is conformally configured on catalyst.Second conductive layer to be configured on the first conductive layer and to cover the first conductive layer.In addition, the second conductive layer fills up blind hole.The part being arranged in blind hole of the second conductive layer has depression, and the degree of depth of this depression is less than or equal to 5 μm.The distance that the edge of the second conductive layer exceeds the edge of the first conductive layer below it is X, and the thickness being positioned at the second conductor layer on dielectric layer is Y, and the ratio of Y and X is between 6 to 10.
According to the wiring board described in the embodiment of the present invention, the material of above-mentioned catalyst layer is such as palladium.
According to the wiring board described in the embodiment of the present invention, the material of the first above-mentioned conductive layer is such as nickel.
According to the wiring board described in the embodiment of the present invention, the material of the second above-mentioned conductive layer is such as copper.
According to the wiring board described in the embodiment of the present invention, the edge of the second above-mentioned conductive layer exceeds the distance at the edge of the first conductive layer below it such as between 2 μm to 3 μm.
Based on above-mentioned, when the present invention forms line layer on dielectric layer, prior to dielectric layer forms sulfuric horizon, then with the patterned mask layer with line pattern for mask is to carry out chemical deposition, to form catalyst layer on sulfuric horizon.Then, the sulfuric horizon of patterned mask layer and below thereof is removed.Then, carry out chemical deposition and on catalyst layer, form the first conductive layer producing chemical bonded refractory with catalyst layer.Afterwards, carry out chemical deposition and form the second conductive layer on the first conductive layer.Therefore, the line layer (being made up of catalyst layer, the first conductive layer and the second conductive layer) formed can have required line pattern, and do not need to utilize etching process to carry out patterning extraly, thus reduce production cost, and avoid environment.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended accompanying drawing to be described in detail below.
Accompanying drawing explanation
The Making programme profile of the wiring board that Figure 1A to Fig. 1 D illustrates for the embodiment of the present invention;
The generalized section being positioned at the line layer on dielectric layer that Fig. 2 illustrates for the embodiment of the present invention;
The generalized section being arranged in the line layer of blind hole that Fig. 3 illustrates for the embodiment of the present invention.
Main element symbol description
100: substrate
100a: first surface
100b: second surface
102a, 102b, 120a, 120b: line layer
104a, 104b: dielectric layer
106a, 106b: metal level
108a, 108b: blind hole
110: surface treatment
112a, 112b: sulfuric horizon
114a, 114b: patterned mask layer
115a, 115b: catalyst layer
116a, 116b, 118a, 118b: conductive layer
122: depression
X: distance
Y: thickness
Z: the degree of depth
Embodiment
The Making programme profile of wiring board of Figure 1A to Fig. 1 D for illustrating according to the embodiment of the present invention.First, please refer to Figure 1A, the substrate 100 with line layer is provided.Substrate 100 is such as dielectric core (dielectric core).Substrate 100 has each other relative first surface 100a and second surface 100b.In addition, line layer 102a is configured on first surface 100a, and line layer 102b is configured on second surface 100b.The material of line layer 102a, 102b is such as metal.
In the present embodiment, substrate 100 is for having the substrate of two-layer line layer, but the present invention is not as limit.In other embodiments, also multilayer line layer can be had in substrate 100.
Continue referring to Figure 1A, carry out pressing step, metal level 106a and dielectric layer 104a is pressed on the first surface 100a of substrate 100, and metal level 106b and dielectric layer 104b is pressed on the second surface 100b of substrate 100.Dielectric layer 104a covers line layer 102a, and dielectric layer 104b covers line layer 102b.The material of metal level 106a and metal level 106b is such as copper.
Then, please refer to Figure 1B, remove metal level 106a and metal level 106b.The method removing metal level 106a and metal level 106b is such as carry out chemical etching and/or mechanical lapping manufacture craft.Afterwards, carry out laser drill step, to form blind hole 108a in dielectric layer 104a, and form blind hole 108b in dielectric layer 104b.Laser drill step is such as use carbon dioxide (CO2) laser to carry out.Blind hole 108a exposes part line layer 102a, and blind hole 108b exposes part line layer 102b.In addition, after formation blind hole 108a and blind hole 108b, the part line layer 102b that the part line layer 102a that can also expose dielectric layer 104a, 104b and blind hole 108a and blind hole 108b exposes carries out surface treatment 110.Surface treatment 110 is such as carry out slag manufacture craft of removing photoresist, with to remove after laser drill the resin that remains.Surface treatment 110 also can be carry out roughening manufacture craft, carries out microetch to line layer 102a and the 102b that blind hole 108a and 108b exposes, and to increase the surface roughness of line layer 102a and 102b, is conducive to the adhesive force of subsequent metal coating.In addition, above-mentioned roughening manufacture craft also can continue and to carry out after slag manufacture craft of removing photoresist.
Then, please refer to Fig. 1 C, dielectric layer 104a is conformally formed sulfuric horizon 112a, and form sulfuric horizon 112b on dielectric layer 104b.The formation method of sulfuric horizon 112a, 112b is such as carry out vulcanizing treatment to dielectric layer 104a, 104b.Then, sulfuric horizon 112a forms patterned mask layer 114a, and form patterned mask layer 114b on sulfuric horizon 112b.Patterned mask layer 114a has line pattern, and it exposes blind hole 108a and partial vulcanization layer 112a.Patterned mask layer 114b has line pattern, and it exposes blind hole 108b and partial vulcanization layer 112b.The material of patterned mask layer 114a and patterned mask layer 114b is such as photo anti-corrosion agent material.
Continue referring to Fig. 1 C, after formation patterned mask layer 114a, 114b, the sulfuric horizon 112a exposed at patterned mask layer 114a and line layer 102a forms catalyst layer 115a, and the sulfuric horizon 112b exposed at patterned mask layer 114b and line layer 102b forms catalyst layer 115b.The material of catalyst layer 115a, 115b is such as palladium.The formation method of catalyst layer 115a, 115b is such as carrying out chemical deposition.
Afterwards, please refer to Fig. 1 D, remove sulfuric horizon 112a, 112b of patterned mask layer 114a, 114b and below thereof.The method removing sulfuric horizon 112a, 112b of patterned mask layer 114a, 114b and below thereof is such as use alkaline striping liquid, such as NaOH.Then, carry out chemical deposition, to be conformally formed conductive layer 116a on catalyst layer 115a, and be conformally formed conductive layer 116b on catalyst layer 115b.The material of conductive layer 116a, 116b is such as nickel.Special one carries, and conductive layer 116a, 116b can produce chemical bonded refractory with catalyst layer 115a, 115b respectively, therefore can improve the adhesive force between conductive layer 116a and catalyst layer 115a and the adhesive force between conductive layer 116b and catalyst layer 115b.Afterwards, carry out chemical plating process, optionally to form conductive layer 118a on conductive layer 116a, and optionally on conductive layer 116b, form conductive layer 118b.The material of conductive layer 118a, 118b is such as copper.In this step, conductive layer 118a, 118b only can be formed on conductive layer 116a, 116b, and conductive layer 118a, 118b can cover conductive layer 116a, 116b respectively completely.In addition, conductive layer 118a, 118b fills up blind hole 108a, 108b respectively.In the present embodiment, conductive layer 116a, the catalyst layer 115a of conductive layer 118a and below thereof form line layer 120a, and the conductive layer 116b of conductive layer 118b and below thereof, catalyst layer 115b form line layer 120b.
In the present embodiment, because the material of conductive layer 116a and conductive layer 118a is all metal, therefore after formation conductive layer 118a, conductive layer 118a can be attached on conductive layer 116a effectively.Similarly, conductive layer 118b can be attached on conductive layer 116b effectively.In addition, owing to there is preferably adhesive force between conductive layer 116a and catalyst layer 115a and between conductive layer 116b and catalyst layer 115b, therefore line layer 120a is made can be configured at securely on dielectric layer 104a, and line layer 120b can be configured on dielectric layer 104b securely, thus can solve the problem that line layer is peeled off from dielectric layer, and then improve the reliability of element.
In addition, in the present embodiment, when forming catalyst layer 115a, 115b, to have patterned mask layer 114a, the 114b of line pattern as mask, therefore namely follow-up conductive layer 116a, 116b be formed on catalyst layer 115a, 115b have required line pattern.Thus, subsequent selective ground in conductive layer 116a, 116b are upper form conductive layer 118a, 118b respectively with chemical deposition after, line layer 120a, 120b of being formed also have required line pattern, and do not need to carry out etching process again by line layer 120a, 120b patterning, therefore effectively can reduce production cost, and avoid etchant to environment.
Other one carries, and because conductive layer 118a, 118b utilize chemical deposition to be formed, therefore can control formed conductive layer 118a, 118b width and thickness by the manufacture craft parameter adjusted when carrying out chemical deposition.Below will explain for line layer 120a.
The generalized section that be positioned at line layer dielectric layer on of Fig. 2 for illustrating according to the embodiment of the present invention.Please refer to Fig. 2, when forming conductive layer 118a on conductive layer 116a with utilizing the way selection of chemical deposition, the manufacture craft parameter by adjusting chemical deposition controls formed conductive layer 118a and has suitable width and thickness.For example, in the present embodiment, via the manufacture craft parameter of adjustment chemical deposition, the distance making the edge of conductive layer 118a exceed the edge of the conductive layer 116a below it is X, and the thickness being positioned at the conductor layer 118a on dielectric layer 104a is Y, and the ratio of Y and X is between 6 to 10.In one embodiment, X can be controlled as between 2 μm to 3 μm, and Y is controlled as about 20 μm.
The generalized section that be arranged in the line layer of blind hole of Fig. 3 for illustrating according to the embodiment of the present invention.Please refer to Fig. 3, the part being arranged in blind hole 108a of conductive layer 118a has depression 122.Via the manufacture craft parameter of adjustment chemical deposition, the degree of depth Z of depression 122 can be made to be less than or equal to 5 μm, to meet the demand of planarization.
Although disclose the present invention in conjunction with above embodiment; but itself and be not used to limit the present invention; this operator is familiar with in any art; without departing from the spirit and scope of the present invention; a little change and retouching can be done, therefore being as the criterion of should defining with the claim of enclosing of protection scope of the present invention.
Claims (12)
1. a manufacture method for wiring board, comprising:
One substrate is provided, this substrate has line layer;
Form a dielectric layer on the substrate, this dielectric layer covers this line layer, and this dielectric layer has blind hole, and this blind hole exposes this line layer of part;
This dielectric layer is conformally formed a sulfuric horizon;
This sulfuric horizon is formed a patterned mask layer, and this patterned mask layer exposes this blind hole and this sulfuric horizon of part;
This sulfuric horizon exposed in this patterned mask layer and this line layer form a catalyst layer;
Remove this sulfuric horizon below this patterned mask layer and this patterned mask layer;
Carry out one first chemical deposition, to be conformally formed one first conductive layer on this catalyst layer; And
Carry out one second chemical deposition, to form one second conductive layer on this first conductive layer, this second conductive layer covers this first conductive layer, and this second conductive layer fills up this blind hole, and the sidewall of this sulfuric horizon coated, this catalyst layer and this first conductive layer.
2. the manufacture method of wiring board as claimed in claim 1, wherein the formation method of this dielectric layer comprises:
Carry out a pressing step, to form this dielectric layer and a metal level on this substrate, wherein this dielectric layer is between this substrate and this metal level;
Remove this metal level;
Carry out laser drill step, to form this blind hole in this dielectric layer.
3. the manufacture method of wiring board as claimed in claim 2, wherein after this blind hole of formation and before this sulfuric horizon of formation, this line layer also comprised this dielectric layer and this blind hole expose carries out a surface treatment.
4. the manufacture method of wiring board as claimed in claim 3, wherein this surface treatment comprises and carries out remove photoresist slag manufacture craft and/or roughening manufacture craft.
5. the manufacture method of wiring board as claimed in claim 1, wherein the material of this catalyst layer comprises palladium.
6. the manufacture method of wiring board as claimed in claim 1, wherein the formation method of this catalyst layer comprises and carries out one the 3rd chemical deposition.
7. the manufacture method of wiring board as claimed in claim 1, wherein the formation method of this sulfuric horizon comprises and carries out a vulcanizing treatment to this dielectric layer.
8. a wiring board, comprising:
Substrate, this substrate has a first line layer;
Dielectric layer, to be configured on this substrate and to cover this first line layer, and this dielectric layer has a blind hole, and this blind hole exposes this first line layer of part;
Sulfuric horizon, is conformally configured on this dielectric layer of part; And
Second line layer, be configured on this first line layer that this sulfuric horizon and this blind hole expose, this second line layer comprises:
Catalyst layer, is conformally configured on this first line layer that this sulfuric horizon and this blind hole expose;
First conductive layer, is conformally configured on this catalyst; And
Second conductive layer, to be configured on this first conductive layer and to cover this first conductive layer, and this second conductive layer fills up this blind hole, the part being arranged in this blind hole of this second conductive layer has a depression, and the degree of depth of this depression is less than or equal to 5 μm,
Wherein the edge of this second conductive layer exceeds the distance at the edge of this first conductive layer below it is X, and the sidewall of this sulfuric horizon coated, this catalyst layer and this first conductive layer, the thickness being positioned at this second conductive layer on this dielectric layer is Y, and the ratio of Y and X is between 6 to 10.
9. wiring board as claimed in claim 8, wherein the material of this catalyst layer comprises palladium.
10. wiring board as claimed in claim 8, wherein the material of this first conductive layer comprises nickel.
11. wiring boards as claimed in claim 8, wherein the material of this second conductive layer comprises copper.
12. wiring boards as claimed in claim 8, wherein the edge of this second conductive layer exceeds the distance at the edge of this first conductive layer below it between 2 μm to 3 μm.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100114681 | 2011-04-27 | ||
| TW100114681A TWI405516B (en) | 2011-04-27 | 2011-04-27 | Circuit board and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102762039A CN102762039A (en) | 2012-10-31 |
| CN102762039B true CN102762039B (en) | 2015-04-01 |
Family
ID=47056322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110322604.4A Expired - Fee Related CN102762039B (en) | 2011-04-27 | 2011-10-21 | Circuit board and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102762039B (en) |
| TW (1) | TWI405516B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105592639B (en) * | 2014-10-23 | 2019-01-25 | 碁鼎科技秦皇岛有限公司 | Circuit board and preparation method thereof |
| US10096542B2 (en) * | 2017-02-22 | 2018-10-09 | Advanced Semiconductor Engineering, Inc. | Substrate, semiconductor package structure and manufacturing process |
| CN109616746A (en) * | 2018-12-13 | 2019-04-12 | 泉州萃思技术开发有限公司 | A kind of 5G antenna for mobile phone processing technology |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1502123A (en) * | 2000-12-21 | 2004-06-02 | 英特尔公司 | Mechanically reinforced highly porous low dielectric constant films |
| CN101686608A (en) * | 2008-09-23 | 2010-03-31 | 欣兴电子股份有限公司 | Method for producing multilayer fine circuit boards |
| TW201023703A (en) * | 2008-12-11 | 2010-06-16 | Unimicron Technology Corp | Manufacturing process of circuit substrate |
| CN101982024A (en) * | 2008-04-30 | 2011-02-23 | 松下电工株式会社 | Method of producing circuit board by additive method, and circuit board and multilayer circuit board obtained by the method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4582892B2 (en) * | 1999-11-11 | 2010-11-17 | イビデン株式会社 | Multilayer printed wiring board and manufacturing method thereof |
| JP2001342574A (en) * | 2000-06-02 | 2001-12-14 | Hitachi Chem Co Ltd | Method for removing plating catalist residue and manufacturing board |
| TWI482550B (en) * | 2007-11-22 | 2015-04-21 | Ajinomoto Kk | Production method of multilayer printed wiring board and multilayer printed wiring board |
-
2011
- 2011-04-27 TW TW100114681A patent/TWI405516B/en not_active IP Right Cessation
- 2011-10-21 CN CN201110322604.4A patent/CN102762039B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1502123A (en) * | 2000-12-21 | 2004-06-02 | 英特尔公司 | Mechanically reinforced highly porous low dielectric constant films |
| CN101982024A (en) * | 2008-04-30 | 2011-02-23 | 松下电工株式会社 | Method of producing circuit board by additive method, and circuit board and multilayer circuit board obtained by the method |
| CN101686608A (en) * | 2008-09-23 | 2010-03-31 | 欣兴电子股份有限公司 | Method for producing multilayer fine circuit boards |
| TW201023703A (en) * | 2008-12-11 | 2010-06-16 | Unimicron Technology Corp | Manufacturing process of circuit substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201244570A (en) | 2012-11-01 |
| CN102762039A (en) | 2012-10-31 |
| TWI405516B (en) | 2013-08-11 |
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Granted publication date: 20150401 Termination date: 20181021 |