JP2012104521A - Method of manufacturing circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of difficultly in fine and high-precision pattern formation, caused by difficulty of uniform high-precision polishing because of distortion and waviness of a substrate, in a method in which an electrolytic plating copper is embedded in a groove and a hole for removing an affluent plating copper by polishing, such as CMP, related to formation of a wiring pattern and a via of a circuit board by an imprint method.SOLUTION: A palladium film which is a catalyst metal film for electroless plating is formed in a groove which is formed on a resin layer surface by an imprint method and on the resin layer surface. Only the palladium film on the resin layer surface is removed by polishing or the like. The electroless plating copper is embedded to be a wiring by the palladium film in the groove. By removing the palladium film only on the resin layer surface, a resin protection layer is formed on the entire surface of a substrate after the palladium film is formed. The resin protection layer and the palladium film on the resin layer surface are polished and removed at the same time, and then the resin protection layer in the groove is melted and removed.

Description

  The present invention relates to a circuit board manufacturing method.

  The configuration pattern width of wiring and the like in a semiconductor element such as an LSI is becoming increasingly finer, and in recent LSIs, the wiring width has reached the submicron level. On the other hand, in the circuit board for mounting these semiconductor elements, at present, the wiring pattern width is about 10 and several μm, and there is a great difference in terms of pattern miniaturization. In order to increase the speed of various electronic devices and to further reduce the size of portable devices, it is necessary to mount electronic components such as semiconductor elements on the circuit board with high density. A reduction in width is required.

  As a method for forming circuit board wiring, for example, a subtractive method, a semi-additive method, an imprint method, and the like are known. In the subtractive method, wiring is formed by wet-etching the conductive film using a resist pattern formed on the conductive film for wiring as a mask. In this method, etching proceeds isotropically. Therefore, the realized minimum line width is about 35 μm, which is not an effective method for forming finer wiring.

  In the semi-additive method, after forming a seed layer on an insulating layer, a plating resist pattern is formed thereon, and a conductive film is formed by electrolytic plating in the opening of the plating resist pattern while supplying power to the seed layer. . Then, after removing the plating resist pattern, the seed layer is wet-etched, whereby a wiring is formed by the conductive film remaining without being etched.

  Such a semi-additive method can reduce the realizable wiring width more than the subtractive method described above, but it is easy to form a wiring in a stable shape when the wiring width is about 5 μm, for example. In addition, the adhesion between the wiring and the base also deteriorates. Therefore, the semi-additive method is often used for wiring having a wiring width of about 10 μm or more.

  On the other hand, in the imprint method, by forming irregularities on the surface of the mold (stamper) on the resin layer, wiring grooves and via holes are formed in the resin layer, and plating and the like are formed in the grooves and holes. In this method, a conductive film is embedded to form wirings and vias.

  FIG. 9 is a schematic cross-sectional view for explaining a manufacturing process of a circuit board in which wirings and the like are formed by an imprint method. FIG. 9A is an example of a mold 101 used for the imprint method. In this case, a wiring protrusion 102 for printing the wiring shape and a via for printing the via shape. It has a projection 103 for use. The mold 101 is made of nickel, for example, and its manufacturing method is basically the same as the method described later with reference to FIG. As shown in FIG. 9 (2), an insulating resin plate 105 having electrode pads 104 on the other main surface side is prepared, the resin layer thereof is once softened, and the mold 101 is press-fitted onto the surface.

  As shown in FIG. 9 (3), the insulating resin plate 105 is solidified as it is, and the mold 101 is peeled off from the insulating resin plate 105. As a result, the insulating resin plate 105 has a wiring groove portion 106 and a via hole portion 107 which are in a mirror image relationship with the respective protrusion portions (convex pattern) of the wiring protrusion portion 102 and the via protrusion portion 103 of the mold 101. Each marking part (concave pattern) is formed. Then, as shown in FIG. 9 (4), for example, electroless copper plating is performed so that copper is embedded in these stamped portions (concave patterns), and then electricity is applied as one of the electrodes. To form a thick copper plating layer 108 that fills the groove and hole. Next, as shown in FIG. 9 (5), the excess copper plating layer 108 on the insulating resin plate 105 is removed by a polishing process such as CMP (Chemical Mechanical Polishing), for example. The via 110 connected to is completed.

  In the description of this manufacturing process, the example of the insulating resin plate 105 having the electrode pads 104 has been described. However, the electrode pads 104 are part of a core layer or a build-up layer formed in multiple layers by an interlayer insulating resin layer. The insulating resin plate 105 can be regarded as an insulating resin layer laminated on the multilayer circuit board. . Accordingly, since the manufacturing process diagram as shown in FIG. 9 is considered to be one step of the manufacturing process of the multilayer circuit board, a process diagram showing a similar simple layer configuration schematic diagram will be disclosed in the future process explanatory diagram. However, the portion of the insulating resin plate is considered as a resin layer and will be described as a resin layer.

  The realizable wiring width of the circuit board by such an imprint method is relatively easy to realize, for example, 5 μm or less, and can be 1 μm to submicron level.

JP 2007-36217 A JP 2006-1000046 A JP 2005-5721 A JP 2006-303438 A

  However, in such an imprint method, polishing of a thick copper plating layer is an essential process, and it is possible to use a fine wiring having a width of several μm to a submicron (in this case, the wiring film thickness is also appropriate). However, it is necessary to polish the copper plating thickness of the wiring portion with high accuracy, for example, at a submicron level. In an actual circuit board, the warp and the undulation of the substrate occur as the multilayer level increases, and it is technically very difficult to realize such a high polishing accuracy.

  Accordingly, an object of the present invention is to provide a method of manufacturing a circuit board in which a fine and high-definition wiring pattern is formed without the need for the above-described polishing in the wiring formation of the circuit board by the imprint method. is there.

The method for manufacturing the circuit board of the present invention includes:
Forming a plurality of concave patterns on the insulating resin layer laminated on the top surface of the substrate;
Forming a catalyst metal film for electroless plating on the inside of the concave pattern and on the surface of the insulating resin layer;
Removing the electroless plating catalyst metal film on the insulating resin layer surface;
Performing electroless plating on the inside of the concave pattern;
It is characterized by having.

  In circuit board wiring formation by imprinting, a catalytic metal film for electroless plating is formed only inside the concave pattern stamped on the insulating resin layer, and electroless plating is applied to the circuit board in this state. To fill the concave pattern and finish the plating when the copper grows to the surface level of the insulating resin layer. For this reason, it is not necessary to polish the plating layer, and a highly accurate wiring pattern can be formed.

The figure explaining the manufacturing process of the metal mold | die applied to this invention The figure explaining the manufacturing process (Example 1) of the circuit board of this invention (the 1) The figure explaining the manufacturing process (Example 1) of the circuit board of this invention (the 2) FIG. 3 illustrates a circuit board manufacturing process (Example 1) according to the present invention. The figure explaining the manufacturing process (Example 2) of the circuit board of this invention The figure (the 1) explaining the manufacturing process (Example 3) of the circuit board of this invention The figure explaining the manufacturing process (Example 3) of the circuit board of this invention (the 2) The figure explaining the circuit board (Example 4) by the manufacturing method of the circuit board of this invention The figure explaining the manufacturing process of the circuit board by the conventional imprint method

Embodiments of the present invention will be described below with reference to the accompanying drawings.
(Example)
(1) Manufacture of mold in this embodiment First, a mold for manufacturing the circuit board of the present invention is formed. FIG. 1 is a schematic cross-sectional view showing a process of manufacturing a mold. As shown in FIG. 1A, a photoresist 2 is applied to the entire upper surface of the silicon substrate 1 and baked. Next, as shown in FIG. 1 (2), pattern exposure is performed using a photomask 3, and this is developed to obtain a resist pattern 4 as shown in FIG. 1 (3). Then, as shown in FIG. 1 (4), the silicon substrate 1 is etched through the resist openings 5 of the resist pattern 4 to form grooves 6, and the resist pattern 4 is peeled off as shown in FIG. 1 (5). Thus, a mother die 7 made of the silicon substrate 1 in which the grooves 6 are formed is obtained.

The shape of the groove 6 is important, and dry etching by, for example, RIE (Reactive Ion Etching) is applied to the etching for forming the groove 6. At this time, a mixed gas of a reactive gas and an inert gas is used as an etching gas. As the reactive gas, a fluorine-based gas such as F ₂ , SF ₂ , CF ₄ , or C ₄ F ₈ is applicable. Cl ₂ or H ₂ may be used. For example, Ar gas can be used as the inert gas. Instead of dry etching, wet etching using an etchant such as hydrofluoric acid or KOH may be used. In the groove 6 of this example, a unit groove having a width of 1.0 μm and a depth of 0.5 μm arranged in parallel with a groove interval of 1.0 μm was formed.

  Next, as shown in FIG. 1 (6), a nickel plating film 8 was formed on the mother die 7 by known nickel electroforming. The film thickness at this time was about 0.3 mm in thickness on the substrate.

Then, as shown in FIG. 1 (7), the nickel plating film 8 was mechanically peeled from the mother die 7 to obtain a nickel die 9.
(2) Production of circuit board in this embodiment (Example 1)
2 to 4 are schematic cross-sectional views for explaining a manufacturing process of Example 1 of the circuit board according to the present invention.

  FIG. 2 (1) uses a prepared mold 9 having a fine convex pattern (for example, the above-mentioned nickel mold), and as shown in FIG. For example, the resin layer 11 is formed on the formed substrate (not shown), and the resin layer 11 is cured and solidified with the mold 9 being pressed into the resin layer 11. As the resin layer 11, for example, epoxy resin, silicone resin, cyanate resin, polyolefin resin, acrylic resin, benzocyclobutene, and the like can be applied. When a thermosetting resin such as an epoxy resin is used, a film in a semi-cured (B stage) state is laminated in advance as a resin layer, and after press-fitting into a mold, the resin layer is cured by heating.

  Then, as shown in FIG. 2 (3), the mold 9 is peeled off, and a concave pattern forming resin layer having a concave portion (groove 12 in the resin layer in the figure) in a mirror image relation with the convex portion of the mold 9. A circuit board having 13 is formed.

  Next, a process of embedding metal (copper) in the groove 12 is performed. First, the surface of the concave pattern forming resin layer 13 of the substrate is degreased, microetched, etc. in a pretreatment process, and then a catalyst is applied ( 2 (4) and a partially enlarged view in the figure, a palladium film 14 is deposited on the surface of the concave pattern forming resin layer 13 including the inside of the groove 12.

  Then, as shown in FIG. 2 (5), the palladium film 14 attached to portions other than the inside of the groove 12 is removed by polishing the surface of the concave pattern forming resin layer 13. The polishing at this time may be either a CMP process or a buff polishing. If the surface of the concave pattern forming resin layer 13 is polished and removed by about 100 nm, the palladium film 14 on the surface can be removed.

  Further, as shown in FIG. 3 (6), the substrate is scrubbed and activated to activate palladium, and then immersed in an electroless copper plating solution to be electrolessly plated with copper 15 in the groove 12. The groove 12 is filled up to the surface of the concave pattern forming resin layer 13. In this way, it is possible to form the fine copper wiring 16 made of the electroless plated copper 15 and embedded in the surface of the resin layer 11 which is not subjected to the polishing treatment.

  Next, as shown in FIG. 3 (7), a photosensitive resin film (film thickness of about 10 μm) is laminated on the surface, and after curing, a photolithographic technique is applied to match the position of the lower electrode pad 10. A photosensitive resin layer pattern 17 having an opening is formed.

  Then, as shown in FIG. 3 (8), via holes 18 that reach the concave pattern forming resin layer 13 to the electrode pads 10 are formed by laser processing in the openings of the photosensitive resin layer pattern 17. Thereafter, as shown in FIG. 3 (9), the photosensitive resin layer pattern 17 is removed, and the processing residue is removed by a desmear process.

Thereafter, plated copper is buried in the via hole 18 by a semi-additive process to form a via and a land. That is, as shown in FIG. 3 (10), an electroless copper plating film 19 is formed as a seed layer, and a photosensitive resin layer pattern 17 is formed thereon again as shown in FIG. 4 (11). Then, as shown in FIG. 4 (12), electrolytic plated copper 20 is formed so as to fill the via hole 18. And as shown in FIG.4 (13), on the electroplating copper 20 of the via hole 18, electroless nickel plating and electroless gold plating are performed, and the Ni-Au plating layer 21 which is a surface electrode is formed, As shown in FIG. 4 (14), after removing the photosensitive resin layer pattern 17, as shown in FIG. 4 (15), the electroless copper plating film (seed layer) 19 on the surface is etched to form the surface. A circuit having a fine copper wiring 16 made of electroless plated copper 15, a via 22 connected to the lower electrode pad 10 embedded with electrolytic plated copper 20, and a surface electrode 23 made of a Ni—Au plated layer 21 thereon. A substrate is manufactured.
(Example 2)
In the above embodiment, with respect to the removal of the palladium film 14 on the surface of the concave pattern forming resin layer 13 in FIG. 2 (4) and thereafter, a method of removing the palladium film 14 by direct polishing and obtaining the situation after the removal of FIG. 2 (5). Applied. In this case, since the adhesion strength of the formed palladium film 14 to the resin is not necessarily high, there is a risk that the palladium film inside the recess is also peeled off depending on the polishing conditions.

  FIG. 5 is a schematic cross-sectional view for explaining the second step of the second embodiment that copes with this. FIG. 5 (1) is a diagram for explaining the situation where the palladium film 14 is attached, as in FIG. 2 (4). Next, as shown in FIG. 5 (2), an insulating resin solution dissolved in a solvent is applied to the adhesion surface of palladium 14 to form a coating film including the inside of the groove 12, and then dried. A resin protective layer 24 is formed. Thereby, the palladium film 14 is fixed to the inner surface of the groove 12 and the surface of the concave pattern forming resin layer 13. At this time, for example, acrylic resin, styrene resin, or the like can be applied as the resin. As the solvent to be dissolved, acetone, toluene or the like can be applied as the organic solvent, and polyvinyl alcohol (PVA) or the like can be applied as the water-soluble resin.

  Then, as shown in FIG. 5 (3), the resin protective layer 24 is removed together with the palladium film 14 on the surface of the concave pattern forming resin layer 13 by a polishing process such as CMP. The thickness of the resin protective layer 24 can be very thin, for example, at a submicron level. Since the resin protective layer 24 is a material that is easier to polish than a metal layer or the like, It is possible to avoid a change in the shape of the concave pattern.

As shown in FIG. 5 (4), for example, the resin protective layer 24 in the groove 12 is dissolved and removed by an organic solvent such as acetone (or water if water-soluble resin). Thus, the palladium film 14 adhered to the inside of the groove 12 is secured. Thereafter, the circuit board of the present invention can be manufactured by the steps after the step of forming the electroless plated copper in FIG.
(Example 3)
In Example 1, the electroless copper plating film 19 in FIG. 3 (10) is formed on the surface of the electroless plating copper 15 of the fine copper wiring 16 completed in FIG. 3 (6). A step was taken in which the film 19 was removed in FIG. For this reason, the surface of the fine copper wiring 16 may be easily damaged.

  FIG. 6 to FIG. 7 are schematic cross-sectional views for explaining the process of Example 3 for avoiding this. FIG. 6 (1) is the same as FIG. 3 (6), and is a situation in which fine copper wirings 16 made of electroless plated copper 15 are embedded in the surface of the concave pattern forming resin layer 13 without being subjected to polishing treatment. It is. In Example 3 of this example, next, as shown in FIG. 6B, a resin film 25 is laminated on this surface so as to have a thickness of about 10 μm and cured.

  As shown in FIG. 6 (3), via holes 18 are formed by laser from above the resin film 25 in accordance with the positions of the electrode pads 10 of the concave pattern forming resin layer 13. Thereafter, the processing residue is removed by desmear treatment.

  Next, as shown in FIG. 6 (4), the electroless copper plating film 19 is formed on the resin film 25 including the inside of the via hole 18 on the surface by the method described above. The electroless copper plating film 19 is not in contact with the fine copper wiring 16 made of the electroless plating copper 15.

  Thereafter, a copper via is formed in the via hole 18 by a semi-additive process by electrolytic plating. As the process, as shown in FIG. 7 (5), a photosensitive resin layer pattern 17 is formed on the electroless copper plating film 19 so as to open the via hole 18, and the electrolytic plated copper 20 is formed in the via hole 18. Embed. Next, as shown in FIG. 7 (6), a Ni—Au plated film 21 is formed on the electrolytic plated copper 20.

  As shown in FIG. 6 (7), the two resin layers (the photosensitive resin layer pattern 17 and the patterned resin film 25) and the electroless copper plating film 19 between them are removed by an etching process or the like to obtain fine copper. The wiring 16 and the top of the via are exposed.

  Then, as shown in FIG. 6 (8), a circuit board having fine copper wirings 16 and surface electrodes 23 and vias 22 connected to the electrode pads 10 is formed in the concave pattern forming resin layer 13.

  As described above, in the method for manufacturing a circuit board according to the present invention, when a metal wiring such as a fine copper wiring is formed on the surface of the insulating resin, the presence of the catalytic metal is determined by the imprinting method. It is limited to the inside of the recess (groove) of the concave pattern so that the electroless plating metal is formed only inside the recess (groove) of the resin concave pattern. Therefore, it is possible to form a metal wiring without polishing the plated metal that is plated thick on the surface. As a result, a fine pattern can be formed with high accuracy, and problems that affect the pattern formation accuracy, which is generally caused when the embedded plating metal surface layer is polished, can be avoided.

Since the method of the present invention uses an electroless plating metal for the embedded metal layer such as wiring, the present method is suitable for forming a fine metal pattern having a relatively thin film thickness. Therefore, a suitable example is a thickness of about 1 μm or less, preferably about 0.5 μm or less. Therefore, the concave pattern depth, that is, the height of the convex portion of the mold is also commensurate with them. It can be said that a particularly suitable application example is that the formation pattern thickness (groove depth) is all the same or close to each other with a fine and thin film thickness.
Example 4
FIG. 8 shows a schematic cross-sectional view of an example of the entire configuration of the circuit board 26 manufactured by the manufacturing method of the present invention. In FIG. 8, the core layer 27 has a plurality of through holes 28 connecting the upper and lower surfaces of the substrate, and the core layer electrode pads 30 are formed at both ends thereof. Several layers (two layers in this example) of build-up resin layers 29 are laminated on both surfaces of the core layer 27, and build-up layer vias 32 connected to the build-up layer wirings 31 and the core layer electrode pads 30. An electrode pad 10 is formed at each end. Furthermore, several layers (two layers in this example) of resin layers 11 are formed thereon, in which resin layer wiring 33, resin layer vias 34, and electrode pads 10 are formed, and the uppermost resin layer 11, the fine copper wiring 16, the via 22 connected to the electrode pad 10, and the surface electrode 23 are formed on the via 22. It can be said that the circuit board cross-sectional schematic diagrams described in Examples 1 to 3 show the portions within the dotted line in the figure.

  Thus, the fine conductor (copper) wiring using the imprint method of the manufacturing method of the present invention is formed on the uppermost surface of the circuit board laminated in multiple layers in FIG. It is possible to provide an optimal wiring or electrode pad for mounting a semiconductor element (chip) having high-density connection terminals.

  The various materials including the metals used in the above-described embodiments and the forming means employed are only examples, and the manufacturing method of the present invention can be applied to other materials and other forming means. Needless to say.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Photoresist 3 Photomask 4 Resist pattern 5 Resist opening 6, 12 Groove 7 Master mold 8 Nickel plating film 9 Mold 10 Electrode pad 11 Resin layer 13 Recessed pattern formation resin layer 14 Palladium film 15 Electroless plating copper 16 Fine copper wiring 17 Photosensitive resin layer pattern 18 Via hole 19 Electroless copper plating film 20 Electroplated copper 21 Ni-Au plating layer 22 Via 23 Surface electrode 24 Resin protective layer 25 Resin film 26 Circuit board 27 Core layer 28 Through hole 29 Build-up Resin Layer 30 Core Layer Electrode Pad 31 Build-up Layer Wiring 32 Build-up Layer Via 33 Resin Layer Wiring 34 Resin Layer Via 101 Mold 102 Wiring Protrusion 103 Via Protrusion 104 Electrode Pad 105 Insulation Resin plate 106 Wiring groove 1 7 hole 108 copper plating layer 109 wiring 110 via a via

Claims (5)

Forming a pattern having at least a concave portion on the insulating resin layer laminated on the uppermost surface of the substrate;
Forming a catalyst metal film for electroless plating on the inside of the concave portion and on the surface of the insulating resin layer;
Removing the electroless plating catalyst metal film on the insulating resin layer surface;
Performing electroless plating on the inside of the concave portion;
A method of manufacturing a circuit board, comprising: The method of manufacturing a circuit board according to claim 1, wherein the concave portions have the same depth.   2. The circuit board according to claim 1, wherein the step of forming the pattern having the concave portion includes a step of press-fitting a mold having a convex portion having a mirror image relationship with the concave portion into the insulating resin layer. Manufacturing method. The removing step includes
2. The method for manufacturing a circuit board according to claim 1, further comprising a step of polishing the electroless plating catalyst metal film on the surface of the insulating resin layer. The removing step includes
Forming a resin protective layer on the inside of the concave portion and the catalyst metal film for electroless plating formed on the surface of the insulating resin layer;
Polishing the electroless plating catalyst metal film on the insulating resin layer surface together with the resin protective layer on the insulating resin layer surface;
Removing the resin protective layer on the electroless plating catalyst metal film inside the concave portion;
The method of manufacturing a circuit board according to claim 1, wherein: