KR101987359B1 - The printed circuit board and the method for manufacturing the same - Google Patents

Abstract

The present invention relates to a semiconductor device comprising a plurality of circuit patterns formed in an active region, a dummy pattern formed in a dummy region other than the active region, and a plating contact portion connected to the dummy pattern and receiving a current for plating, And a plurality of plating contact patterns are formed on the plating contact portions. Therefore, when the circuit pattern is formed, the plating deviation can be reduced by forming the dummy pattern and the plating contact portion together. In addition, by forming a pattern in the plating contact portion while reducing the thickness of the dummy pattern, it is possible to reduce the dishing of the large-area plating contact portion.

Description

[0001] The present invention relates to a printed circuit board and a method of manufacturing the same,

The present invention relates to a printed circuit board and a method of manufacturing the same.

A printed circuit board (PCB) is an electrically insulating substrate such as copper

Refers to a board formed by printing a circuit pattern with a conductive material and immediately before mounting electronic components. In other words, a circuit board on which a mounting position of each component is determined, and a circuit pattern connecting the components are printed on the surface of the flat plate and fixed is fixed in order to densely mount various kinds of electronic devices on a flat plate.

Such a printed circuit board generally has a build-up board, i.e., a multi-layer PCB, in which a single-layer PCB and a PCB are formed in multiple layers.

In recent years, a buried pattern substrate which can reduce the thickness of a printed circuit board and planarize the surface of the substrate has been used in order to cope with high performance and miniaturization of electronic parts.

The printed circuit board on which the buried pattern is formed has a very high bonding force with the insulating member due to the base circuit pattern and the formation structure of the contact portion and the pitches of the base circuit pattern and the contact portion can be uniformly and finely formed.

However, in the case of forming the buried pattern, a plating thickness difference occurs in the buried pattern and other portions in the plating process for forming the buried pattern.

When the plating thickness difference is generated, the etching process is not performed uniformly, so that in the region where no etching occurs, the buried pattern may be short-circuited with the neighboring pattern or the buried pattern may not be formed in the region where etching has occurred.

An embodiment provides a printed circuit board having a new structure and a method of manufacturing the same.

Embodiments provide a printed circuit board without a plating thickness difference and a method of manufacturing the same.

The embodiment includes a plurality of circuit patterns formed in an active region, a dummy pattern formed in a dummy region other than the active region, and a plating contact portion connected to the dummy pattern and receiving a current for plating, And a plurality of plating contact patterns are formed on the plating contact portions.

The embodiment includes a step of preparing an insulating substrate which defines an active region where circuit patterns and elements are formed, a dummy region other than the active region and a plating contact portion connected to the dummy region, and a plurality of circuit patterns And forming a dummy pattern in the dummy area and a plurality of plating contact patterns in the plating contact part.

According to the present invention, when the circuit pattern is formed, the plating deviation can be reduced by forming the dummy pattern and the plating contact portion together.

In addition, by forming a pattern in the plating contact portion while reducing the thickness of the dummy pattern, it is possible to reduce the dishing of the large-area plating contact portion.

As the plating variation decreases, the etching is made uniform so that the circuit pattern can be formed without causing etching or being excessively etched.

1 is a top view of a printed circuit board according to the present invention.
2 is a cross-sectional view of the printed circuit board of Fig.
FIG. 3 is an embodiment showing a pattern shape of the plating contact portion of FIG. 2. FIG.
4 to 10 are sectional views showing a first method for manufacturing a printed circuit board of the present invention.
11 to 17 are sectional views showing a second method for manufacturing a printed circuit board of the present invention.
18 is a cross-sectional view of a printed circuit board according to the control group of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

In order to clearly illustrate the present invention in the drawings, thicknesses are enlarged in order to clearly illustrate various layers and regions, and parts not related to the description are omitted, and like parts are denoted by similar reference numerals throughout the specification .

Whenever a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case where it is "directly on" another portion, but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

Hereinafter, a printed circuit board according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 10. FIG.

FIG. 1 is a top view of a printed circuit board according to the present invention, FIG. 2 is a cross-sectional view of the printed circuit board of FIG. 1, and FIG. 3 is an embodiment showing a pattern shape of the plating contact portion of FIG.

The printed circuit board panel 500 of FIG. 1 includes an active area AA in which a plurality of printed circuit board 100 units are formed and a dummy area DA surrounding the active area AA.

2 to 3, each printed circuit board 100 includes an insulating plate 110, a first circuit pattern 120 formed on the insulating plate 110, an insulating layer 130, 2 circuit pattern 153. [

The printed circuit board panel 500 includes an active area AA formed with the second circuit pattern 153 and a pad on which a plurality of elements are mounted, a dummy area DA including a dummy pattern 157, And includes a contact point PA.

The dummy area DA is defined in the printed circuit board panel 500 as an area other than the active area AA.

The dummy area DA may be located between the active area AA and the active area AA and may be formed to surround the active area AA as shown in FIG.

The dummy area DA is electrically insulated from the active area AA except for the plating line.

The plating contact PA is a pad for electrolytic plating and is connected to a part of the pattern of the dummy area DA to supply a current to a pattern of the dummy area DA and the active area AA.

The plating contact PA may be connected to one of the edges of the edge of the dummy area DA.

The insulating plate 110 may be a thermosetting or thermoplastic polymer substrate, a ceramic substrate, an organic-inorganic composite substrate, or a glass fiber impregnated substrate. When the insulating plate 110 includes a polymer resin, the insulating plate 110 may include an epoxy insulating resin. Based resin and a polyimide-based resin.

A plurality of first circuit patterns 120 are formed as a base circuit pattern on the insulating plate 110.

The first circuit pattern 120 is formed of a material having a high electrical conductivity and a low resistance. The first circuit pattern 120 may be formed by patterning a copper foil, which is a thin copper layer, with a conductive layer. When the plate 110 includes a resin, the first circuit pattern 120 and the insulating plate 110 may be a conventional CCL (copper clad laminate).

Meanwhile, the insulating layer 130 is formed by embedding the first circuit pattern 120 on the insulating plate 110.

The insulating layer 130 may be formed of a plurality of insulating layers 130, and each insulating layer 130 may be a polymer resin or the like.

The insulating layer 130 of the active area AA of the insulating layer 130 may include a via hole 131 for exposing the first circuit pattern 120 and a circuit for forming a plurality of second circuit patterns 153. [ Pattern groove 135 and the insulating layer 130 of the dummy area DA includes a dummy pattern groove 137 for forming the dummy pattern 151. [

In addition, a plating contact groove 139 for forming the plating contact portion PA in the same plane as the circuit pattern groove 135 is formed.

The dummy pattern grooves 137 may be uniformly formed with respect to the dummy area DA, and may include a plurality of small patterns.

The width of the dummy pattern groove 137 is formed so as to satisfy 50 μm or less, which is excellent in superfinishing characteristics.

The plating contact groove 139 may have a plurality of patterns as shown in FIG.

That is, as shown in FIG. 3A, the plating contact grooves 139 may be formed concentrically, and a part of the concentric circles may be short-circuited.

In addition, the plating contact groove 139 may be formed to have a stripe shape, and the stripe may be connected to the stripe of the next row as shown in FIG. 3B, and the stripe may be connected to the stripe And may be associated with the next row of stripes.

On the other hand, the plating contact groove 139 may be formed of a plurality of dispersed dots, and the upper surface of the dot may have a circular shape as shown in FIG. 3D or may be rectangular as shown in FIG. 3E.

A metal layer 140 is formed in the insulating layer 130 in the plurality of via holes 131, the circuit pattern groove 135, the plating contact groove 139, and the dummy pattern groove 137.

The metal layer 140 may be formed of copper, nickel, or an alloy thereof as a seed layer.

A second circuit pattern 153, a dummy pattern 151, a plating contact pattern 155, and a via 150 for embedding the respective pattern grooves 135, 137, 139 and the via hole 131 are formed on the metal layer 140 Respectively.

The second circuit pattern 153, the dummy pattern 151 and the via contact pattern 155 and the via 150 are formed simultaneously and are formed of an alloy containing at least one of aluminum, copper, silver, platinum, nickel or palladium And may be formed by performing plating with the metal layer 140 as a seed layer.

The printed circuit board 100 as shown in FIG. 2 has the same layer as that of the second circuit pattern 153 in the plating contact portion in addition to the active area AA in which the second circuit pattern 153 and the vias 150 are formed, Pattern 155 is formed.

Since the plating contact pattern 155 is formed at the same time as the second circuit pattern 153 and simultaneously with the second circuit pattern 153, the plating proceeds uniformly without increasing the process, Two circuit patterns 153 can be accurately formed.

At this time, the width of the dummy pattern 151 is formed so as to satisfy 50 μm or less, which is excellent in superfinishing characteristics.

Hereinafter, a method of manufacturing the printed circuit board 100 of FIG. 1 will be described with reference to FIGS. 4 to 10. FIG.

First, a first circuit pattern 120 is formed on an insulating plate 110 as shown in FIG.

The insulating plate 110 and the first circuit pattern 120 may be formed by etching the copper foil layer of the CCL according to the design of the first circuit pattern 120. Alternatively, 110, and then etching the copper foil layer.

At this time, the first circuit pattern 120 may include a pattern connected to the second circuit pattern 153 through the via hole 131 as shown in FIG.

Next, the first circuit pattern 120 is embedded on the insulating plate 110 to form the insulating layer 130 of FIG.

The insulating layer 130 includes a thermosetting resin. The insulating layer 130 may be formed by applying a semi-cured resin that is not completely cured to a predetermined thickness on the insulating plate 110, and then curing by applying heat and pressure. .

Next, as shown in FIG. 6, a via hole 131 is formed in the insulating layer 130 to expose the first circuit pattern 120. The via hole 131 may be formed to have a side surface inclined at a predetermined angle with respect to the plane of the substrate as shown in FIG. 6, or alternatively may be formed to have a side surface perpendicular to the plane of the substrate.

The via hole 131 may be formed using a laser 200 as shown in FIG. 6, and the laser 200 may be formed using a UV laser, a CO ₂ laser, or the like.

The via hole 131 may be formed by a physical method, such as drilling, or may be formed by selective etching by a chemical method.

Next, as shown in FIG. 7, pattern grooves 135, 137, 139 for forming circuit patterns 153, plating contact patterns 155, 155, and dummy patterns 151 are formed in the insulating layer 130 do. 7, the pattern grooves 135, 137, and 139 may be formed using an excimer laser that emits a laser beam having a wavelength in the ultraviolet region. As the excimer laser, a KrF excimer laser (krypton fluorine, central wavelength: 248 nm) or an ArF excimer laser (argon fluorine, central wavelength: 193 nm) can be applied.

A pattern mask 300 for forming the circuit pattern grooves 135, the plating contact grooves 139 and the dummy pattern grooves 137 at the same time is formed when the circuit pattern grooves 135 are formed through the excimer laser, And then selectively irradiating the excimer laser through the pattern mask 300.

7, a dummy pattern groove 137 for forming a dummy pattern 151 is formed in the dummy area DA by irradiating the laser 200, and the plating contact part PA is provided with a plating A contact groove 139 is formed, and a second circuit pattern 153 is formed in the active area AA.

At this time, the region where the via hole 131 is formed may have a groove having a larger area than the exposed upper surface of the via hole 131, so that a layered structure may be formed in the via hole 131.

When the via hole 131 is formed in a layered structure, the extended upper surface of the via hole 131 can be used as a pad for mounting the device, thereby ensuring an area for mounting the device.

Next, a metal layer 140 is formed on the insulating layer 130 as shown in FIG.

The metal layer 140 is formed on the entire surface of the printed circuit board 100, that is, across the active area AA, the plating contact PA, and the dummy area DA.

The metal layer 140 is first subjected to a desmear process to remove the smear of the insulating layer 130 and to enhance the adhesion to the metal layer 140. The metal layer 140, which is a conductive seed layer, .

The metal layer 140 may be formed by an electroless plating method.

The electroless plating process can be performed by treating the process in the order of degreasing process, soft corrosion process, preliminary catalyst process, catalytic process, activation process, electroless plating process and oxidation prevention process. The metal layer 140 may be formed by sputtering metal particles using plasma.

The metal layer 140 is formed of an alloy containing copper, nickel, palladium or chromium.

Next, the metal layer 140 is electroplated with a seed layer to form a plating layer 155.

The plating layer 155 is formed by filling the dummy pattern groove 137 of the dummy area DA and the circuit pattern groove 135 of the active area AA, the dummy pattern groove 137, and the via hole 131 The height of the uppermost layer of the plating layer 155 can be uniformly formed.

At this time, the plating layer 155 may be formed of copper having high conductivity.

10, the unnecessary plating layer 155 and the metal layer 140 are etched to form the insulating layer 130 so that the plating layer 155 remains only in the pattern grooves 135, 137, 139 and the via hole 131. [ Etch until the surface is exposed.

At this time, the method of exposing the surface of the insulating layer 130 can be selectively performed by a flash etching method or a surface polishing method. When the thickness of the plating layer 155 is thick, have.

As described above, the plating layer 155 is formed only in the pattern grooves 135, 137, 139 and the via holes 131 until the insulating layer 130 is exposed, so that the second circuit patterns 153, The second circuit pattern 153 can be formed while maintaining the insulation state by forming the dummy pattern 151, the plating contact pattern 155, and the via 150.

A dummy pattern groove 137 is formed in the dummy region DA and a plating contact pattern 155 is formed on the plating contact portion PA and a plating contact pattern 155 and a dummy pattern 151 are formed on the second circuit By forming the pattern 153 at the same time as the pattern 153, no plating deviation occurs when the plating layer 155 is formed, the etching can proceed uniformly, and the second circuit pattern 153 can be accurately formed.

In addition, by forming a pattern in the plating region of the large-area plating contact portion PA, it is possible to prevent the dishing phenomenon of the central region at the time of large-area plating by dispersing a large area.

At this time, the width of the dummy pattern 151 is formed so as to satisfy 50 μm or less, which is excellent in superfinishing characteristics.

The above characteristics are shown in the following table.

Dummy pattern width 5 μm 7 μm 10μm 15μm 30μm 50μm 70μm 90μm 130 m 200μm 300μm Really 0.26 0.24 0.41 0.77 1.08 1.17 1.99 2.30 2.70 4.30 5.02

Hereinafter, a second method of manufacturing the printed circuit board of the present invention will be described with reference to Figs. 11 to 17. Fig.

First, a first circuit pattern 220 is formed on an insulating plate 210 as shown in FIG.

The insulating plate 210 and the first circuit pattern 220 may be formed by etching the copper foil layer of the CCL according to the first circuit pattern 220. Alternatively, Or may be formed by laminating and then etching.

At this time, the first circuit pattern 220 may include a pattern connected to the second circuit pattern 263 through a via hole to be described later. The first circuit pattern 220 is embedded on the insulating plate 210 to form the insulating layer 230 of FIG.

The insulating layer 230 includes a thermosetting resin. The semi-cured resin that is not completely cured may be coated on the insulating plate 210 to a predetermined thickness, and the insulating layer 230 may be formed of a plurality of layers.

12, a dummy pattern 261 is formed in the circuit pattern groove 235, the plating contact groove 239, and the dummy area DA for forming the second circuit pattern 263 in the active area AA The dies 240 corresponding to the dummy pattern grooves 235 are prepared.

The mold 240 may be made of a transparent mold 240 such as ceramic, quartz, glass, or polymer, or may be an opaque material such as a semiconductor material, ceramic, metal, or polymer.

The method of manufacturing the mold 240 can be performed by forming a concavo-convex pattern by processing a flat surface of a material in the form of a plate 210. The processing can be variously performed by electron beam lithography, photolithography, dicing, laser, .

For example, the metal mold 240 corresponding to the dummy area DA and the metal mold 240 corresponding to the active area AA can be formed separately. And the mold 240 corresponding to the active area AA may be formed by separating into a plurality of mold units.

At this time, the mold 240 may be formed by closely adhering a release film so as to facilitate separation from the insulating layer 130.

Next, as shown in FIG. 13, the mold 240 is brought into close contact with the insulating layer 230 to form a plurality of grooves corresponding to the concavities and convexities of the mold 240 in the insulating layer 230, And the insulating layer 230 is cured using heat.

The insulating layer 230 is cured in a state where a plurality of the plating contact grooves 239, the dummy pattern grooves 237 and the circuit pattern grooves 235 are formed and then the mold 240 is removed from the insulating layer 230 And a via hole 231 is formed in the insulating layer 230 to expose the first circuit pattern 220 as shown in FIG.

The via hole 231 may be formed to have a side surface inclined at a predetermined angle with respect to the plane of the insulating plate 210 as shown in FIG. 14, or may be formed to have a side surface perpendicular to the plane of the insulating plate 210 .

The via hole 231 may be formed using a laser 200 as shown in FIG. 14. At this time, the laser 200 may be formed using a UV laser, a CO ₂ laser, or the like.

The via hole 231 may be formed by a physical method, that is, by drilling or the like, or may be formed by selective etching by a chemical method.

The via hole 231 may be formed to have a layered structure because a region where the via hole 231 is to be formed by the mold 240 is formed in the groove after forming a groove wider than the upper surface of the via hole 231 .

When the via hole 231 is formed in a layered structure, the extended upper surface of the via hole 231 can be used as a pad for mounting the device, thereby securing an area for mounting the device.

Next, a metal layer 250 is formed on the insulating layer 230 as shown in FIG.

The metal layer 250 is formed on the entire surface of the printed circuit board, that is, over the active area AA and the dummy area DA.

The metal layer 250 is first subjected to a desmear process to remove the smear of the insulating layer 230 and to enhance the adhesion with the metal layer 250 and then the metal layer 250 as the conductive seed layer .

The metal layer 250 may be formed by an electroless plating method. The electroless plating process can be performed in the order of degreasing process, soft corrosion process, preliminary catalyst process, catalytic process, activation process, electroless plating process, and oxidation prevention process. The metal layer 250 may be formed by sputtering metal particles using plasma.

The metal layer 250 is formed of an alloy containing copper, nickel, palladium or chromium.

Next, as shown in FIG. 16, a conductive material is electrolytically plated with the seed layer of the metal layer 250 to form a plating layer 265.

The plating layer 265 is formed on the dummy pattern groove 237 of the dummy area DA, the circuit pattern groove 235 of the active area AA and the plating contact groove 239 of the via hole 231 and the plating contact part PA And the height of the uppermost layer of the plating layer 265 can be uniformly formed.

At this time, the plating layer 265 may be formed of copper having high conductivity.

Finally, the unnecessary plating layer 265 and the metal layer 250 are etched as shown in FIG. 17, and the surface of the insulating layer 230 is removed so that the plating layer 265 remains only in the grooves 235, 237, and 239 and the via hole 231. [ Etch until exposed.

At this time, the method of exposing the surface of the insulating layer 230 can be selectively performed by a method of flash etching or a surface polishing method. If the thickness of the plating layer 265 is thick, half etching and flash etching can be performed.

The plating layer 265 is formed only in the grooves 235, 237 and 239 and the via hole 231 until the insulating layer 230 is exposed to form a dummy pattern 261, a plating contact pattern 265, the second circuit pattern 263, and the via 260, the second circuit pattern 263 can be formed while maintaining the insulation state.

As described above, the dummy pattern groove 237 is formed in the dummy area DA and the dummy pattern 261 is formed simultaneously with the second circuit pattern 263, so that no plating deviation is formed when the plating layer 265 is formed The etching can be uniformly formed, and the second circuit pattern 263 can be uniformly formed without being short-circuited or over-etched.

At this time, the panel 500 of FIG. 1 includes a plurality of printed circuit board units that are not separated, and are separately used for each of the printed circuit board units in a subsequent process.

18 is a cross-sectional view of a printed circuit board according to the control group of the present invention.

Referring to FIG. 18, a printed circuit board 10 according to a control group of the present invention includes a first circuit pattern 2, an insulating layer 3 having a plurality of pattern grooves formed on an insulating plate 1, And a metal layer 4 formed on the pattern groove and a plating layer 5 formed on the metal layer.

1, a dummy pattern is not formed in the dummy area DA other than the active area AA, and a plurality of patterns are not formed in the plating contact part.

When the dummy pattern and the plating contact pattern are not formed as described above, the plating layer 4 formed by plating is formed thick on the metal layer 4 on the insulating layer 3 of the dummy area DA, The plating layer 5 is not completely etched in the region A other than the pattern groove of the active region AA during etching to expose the region B where the plating layer 5 in the via hole is excessively etched, And uniformity is not ensured.

Therefore, as in the present invention, since a plating pattern can be reduced by forming a plurality of patterns in a large-area plating contact portion while forming a dummy pattern in the dummy region DA simultaneously with the second circuit pattern of the active region, So that a short circuit between the second circuit patterns can be prevented.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

The printed circuit board 100
Insulation plates 110, 210
The first circuit patterns 120 and 220
The insulating layers 130 and 230
Plating contact part PA
Dummy patterns 151 and 161
Plating contact patterns 155 and 165

Claims (21)

An insulating substrate including an active region and a dummy region surrounding and surrounding the active region;
A plurality of circuit patterns formed on the active region of the insulating substrate,
A dummy pattern formed on the dummy region of the insulating substrate, and
And a plating contact portion formed on the dummy region of the insulating substrate and connected to the dummy pattern and adapted to receive a current for plating,
The dummy area
Wherein the conductive line is connected to the active region through a plating line, and electrically isolated from the active region except for the plating line,
Wherein the plating contact portion comprises:
And a plurality of plating contact patterns connected to the dummy patterns disposed at the edges of the dummy region. The method according to claim 1,
Wherein:
Wherein a plurality of circuit pattern grooves are formed on a surface of the active region, a dummy pattern groove is formed on a surface of the dummy region, and a plurality of plating contact grooves are formed in the plating contact portion,
Wherein each of the plurality of circuit patterns, the dummy pattern and the plating contact portion includes a first metal layer formed along the inner wall of the circuit pattern groove, the dummy pattern groove, and the plating contact groove,
And a second metal layer formed by embedding the circuit pattern groove, the dummy pattern groove, and the plating contact groove on the first metal layer, respectively. 3. The method of claim 2,
Wherein the second metal layer is a plating layer formed by plating the first metal layer with a seed layer. 3. The method of claim 2,
Wherein:
Insulation plate,
A base circuit pattern patterned on the insulating plate, and
And an insulating layer covering the base circuit pattern and formed on the insulating plate,
Wherein the circuit pattern groove, the dummy pattern groove, and the plating contact groove are formed on a surface of the insulating layer. 5. The method of claim 4,
Wherein the insulating layer further comprises a via hole exposing the underlying circuit pattern. The method according to claim 1,
Wherein the width of the dummy pattern is 50 mu m or less. The method according to claim 1,
Wherein the plating contact pattern is formed concentrically. The method according to claim 1,
Wherein the plating contact pattern has a dot shape. The method according to claim 1,
Wherein the plating contact patterns have a plurality of stripe patterns connected to each other. The method according to claim 1,
Wherein the dummy area includes a plurality of corner areas,
Wherein the plating contact portion comprises:
And is selectively formed on only one of the corner portions of the plurality of corner portions. delete delete delete delete delete delete delete delete delete delete delete

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