TW201334646A - The printed circuit board and the method for manufacturing the same - Google Patents

Abstract

Disclosed are a printed circuit board and a method of fabricating the same. The method includes preparing an insulating substrate, forming a circuit pattern groove on a surface of the insulating substrate, plating a first metal layer on the substrate of the insulating substrate, forming a plating layer burying the circuit pattern groove by performing a plating process using the first metal layer of the circuit pattern groove as a seed layer, forming a buried pattern by removing the plating layer through chemical mechanical polishing until an insulating layer is exposed, and forming a concave pattern on a top surface of the buried pattern through a flash etching. Both of the half-etching process and the flash etching process in order to improve the efficiency of the chemical mechanical polishing are performed, thereby preventing the short between the patterns.

Description

Printed circuit board and method of manufacturing same

The present invention relates to a printed circuit board and a method of fabricating the same.

A printed circuit board (PCB) is formed by printing a circuit line pattern on an electrical edge substrate using a conductive material such as copper (Cu), and refers to a plate on which the electronic component has not adhered. In other words, the PCB refers to a circuit board in which the mounting position of the electronic components has not yet been determined, and a circuit pattern connecting the electronic components is fixedly printed on a flat board body to densely mount the electronic components. On the flat plate.

Meanwhile, in recent years, a buried pattern substrate having a reduced thickness and a planarized surface has been used for the purpose of high function and miniaturization of electronic components.

FIG. 1 illustrates a typical buried pattern PCB 10 .

As shown in FIG. 1, the buried pattern PCB 10 includes a buried pattern trench 2 formed in the surface of an insulating substrate 1 and a circuit pattern 3 filled with a buried pattern trench 2 through an electroplating process.

The PCB 10 having the buried circuit pattern 3 can exhibit a very strong adhesive strength to an insulating member due to a base circuit pattern and a contact portion forming structure, and the base circuit patterns and the pitch of the contact portions (pitches) ) can be formed uniformly and accurately.

However, when the buried circuit pattern 3 is formed by electroplating, the plating variation occurs between a region having the pattern groove 2 and a region having no pattern groove 2, so that the etching process may not be performed uniformly after the plating process. Therefore, a region of the circuit pattern 3 may not be etched away as shown in FIG. 1, and thus the circuit pattern 3 may be short-circuited with an adjacent circuit pattern. In addition, another area of the circuit pattern 3 may be over-etched, so errors may occur in signal transmission.

The embodiment provides a printed circuit board having a novel structure and a method of fabricating the same.

Embodiments provide a novel method of fabricating buried circuit patterns.

According to an embodiment, a method of fabricating a printed circuit board is provided. The method includes: preparing an insulating substrate, forming a circuit pattern groove on a surface of the insulating substrate, plating a first metal layer on the substrate of the insulating substrate, and using the circuit pattern groove A metal layer is used as a sub-layer to perform an electroplating process to form a plating layer to bury the circuit pattern recess, and the electroplated layer is removed by chemical mechanical polishing until an insulating layer is exposed to form a buried pattern. And forming a concave pattern on an upper surface of the buried pattern by flash etching.

According to an embodiment, there is provided a printed circuit board having an insulating substrate including a plurality of circuit pattern grooves on a surface of the printed circuit board, and the plurality of circuit patterns are filled by filling the circuit pattern grooves form. The upper surface of each circuit pattern has a concave shape.

As described above, the circuit pattern is formed by a plating method by filling a groove of the substrate. The plating layer formed on the insulating layer is removed by chemical mechanical polishing to simply form the micro-buried pattern.

In addition, a half etching process and a flash etching process for improving the efficiency of chemical mechanical polishing are performed to prevent a short circuit between the patterns.

In addition, the circuit pattern is formed into a curved shape without edges, thereby reducing noise and heat generated from the edges, and thereby achieving high speed and highly integrated packaging.

1‧‧‧Insert substrate

2‧‧‧ buried pattern groove

3‧‧‧ circuit pattern

10‧‧‧PCB

100,400‧‧‧PCB

110‧‧‧Insulation board

120‧‧‧First circuit pattern

130‧‧‧Insulation

131‧‧‧Circuit pattern groove

135‧‧‧through holes

140‧‧‧metal layer

150‧‧‧second circuit pattern

151‧‧‧layer window

155‧‧‧Electroplating

200‧‧‧ pattern cover layer

H1‧‧‧ thickness

1 is a cross-sectional view of a printed circuit board in accordance with conventional techniques.

2 is a cross-sectional view showing a printed circuit board according to an embodiment.

3 to 10 are cross-sectional views showing a method of manufacturing the printed circuit board according to an embodiment.

11 and 12 show photographs of a printed circuit board in accordance with an embodiment.

13 is a cross-sectional view showing a printed circuit board according to another embodiment.

In the following, the embodiments will be described in detail with reference to the drawings, and thus those skilled in the art can be easily accomplished by the embodiments. However, embodiments may have various modifications that are not limited.

In the following description, when a predetermined portion includes a predetermined element, unless the context indicates otherwise, the predetermined portion does not exclude another element and further includes any element.

The thickness and size of each layer appearing in the drawings may be exaggerated, omitted or schematically illustrated for convenience or clarity. Furthermore, the dimensions of the components do not fully reflect a true size. In the following description, the same elements will be denoted by the same element symbols.

In the description of the embodiments, it will be understood that when a layer, a film, or a piece is indicated to be "on" or "under" of any layer, any film, any region, or any of the sheets, a Or multiple intermediaries. The location of this layer will be described with reference to the drawings.

The present disclosure provides a method of forming a circuit pattern by forming a circuit pattern by chemical mechanical polishing on a printed circuit board (PCB) having a buried pattern circuit pattern.

Hereinafter, a PCB according to an embodiment will be described with reference to FIGS. 2 to 12.

2 is a cross-sectional view of the printed circuit board in accordance with an embodiment.

Referring to FIG. 2, a PCB 100 according to an embodiment includes an insulating plate 110, a first circuit pattern 120 formed on the insulating plate 110, an insulating layer 130, and a plurality of second circuit patterns 150.

The insulating plate 110 may include a thermosetting substrate, a thermoplastic polymer substrate, a ceramic substrate, an organic-inorganic composite material substrate, or a glass-woven dip substrate. If the insulating plate 110 comprises a polymer resin, the insulating plate 110 may comprise an epoxy-based insulating resin or may comprise a poly-liminium-based resin.

A plurality of first circuit patterns 120 are formed on the insulating plate 110 as a base circuit pattern.

Further, the first circuit pattern 120 may include a material exhibiting high electrical conductivity and low electrical resistivity. In particular, the first circuit pattern 120 can be formed by patterning a thin copper film as a conductive layer. If the first circuit pattern 120 is a copper film and the insulating plate 110 contains a resin, the first circuit pattern 120 and the insulating plate 110 may have a typical copper foil laminate (CCL) structure.

At the same time, the insulating layer 130 is buried by the first circuit pattern 120. The insulating plate 110 is formed.

The insulating layer 130 may include a plurality of insulating layers 130, and each of the insulating layers 130 may include a polymer resin.

The insulating layer 130 includes a via hole 135 to expose the first circuit pattern 120 and the circuit pattern recesses 131 to form the second circuit patterns 150.

In this example, the circuit pattern groove 131 has a diagonal cross section. Preferably, the cross section of the circuit pattern groove 131 has a width which gradually narrows downward.

Each of the circuit pattern grooves 131 has a width in the range of 3 μm to 25 μm and a depth in the range of 3 μm to 25 μm. Further, the via 135 has a diameter of less than or about 80 μm and a depth of less than or about 100 μm.

A metal layer 140 is formed in the via holes 135 of the insulating layer 130 and the circuit pattern recesses 131 along the shape of the circuit pattern recesses 131.

The metal layer 140 may serve as a sub-layer and may include copper (Cu), nickel (Ni), or an alloy thereof.

A second circuit pattern 150 and a via 151 are formed on the metal layer 140 to fill the circuit pattern recess 131 and the via hole 135.

The second circuit pattern 150 and the via 151 are simultaneously formed, and may include aluminum (Al), copper (Cu), silver (Ag), platinum (Pt), nickel (Ni), and palladium (Pd). An alloy of at least one. The second circuit pattern 150 and the via 151 may be formed by performing an electroplating process using the metal layer 140 as a sublayer.

The second circuit pattern 150 and the via 151 have a concave shape and a depth gradually decreasing from the edge region toward the central portion thereof.

Hereinafter, a method of manufacturing the PCB 100 of FIG. 2 will be described with reference to FIGS. 3 to 10.

As shown in FIG. 3, the first circuit pattern 120 is formed on the insulating plate 110.

The structure of the insulating plate 110 and the first circuit pattern 120 may be formed by etching a thin copper layer of the CCL according to the design of the first circuit pattern 120. Alternatively, the structure of the insulating plate 110 and the first circuit pattern 120 may be formed by stacking a copper film on a ceramic substrate and etching the resultant structure.

In this example, the first circuit pattern 120 may include a pattern through the via 135 to be connected to the second circuit pattern 150 as shown in FIG. 2 .

Next, the insulating substrate is prepared by forming the insulating layer 130 to cover the first circuit pattern 120 on the insulating plate 110.

The insulating layer 130 may include a thermosetting resin. The insulating layer 130 can be formed by coating a B-stage resin on the insulating sheet 110 at a predetermined thickness and applying heat and pressure to the B-stage resin. It is also possible to provide a plurality of insulating layers 130.

Then, as shown in FIG. 4, via holes 135 are formed in the insulating layer 130 to expose the first circuit pattern 120. As shown in FIG. 4, the via 135 may have a sidewall that is inclined at a predetermined angle with respect to a plane of the substrate. Alternatively, vias 135 may have sidewalls that are perpendicular to the plane of the substrate.

The via hole 135 can be formed by using a laser such as a UV laser or a CO2 laser.

In addition, the via hole 135 can be formed by a physical method. For example, the via hole 135 can be formed through a drilling process. Furthermore, the via 135 can be permeable to a selective chemistry Formed by an etching process.

Next, as shown in FIG. 5, a circuit pattern groove 131 is formed in the insulating layer 130 to form a second circuit pattern 150. As shown in FIG. 5, the circuit pattern groove 131 can irradiate a laser light having a wavelength of ultraviolet light by using a pseudo-molecular laser. The excimer laser may comprise a KrFexcimer laser (krypton fluoride, central wavelength of 248 nm) or an ArFexcimer laser (argon fluoride), 193 The central wavelength of nm).

When the circuit pattern grooves 131 are formed by using a pseudo-molecular laser, the circuit pattern grooves 131 can be formed by forming a pattern mask layer (pattern) for simultaneously forming the circuit pattern grooves 131. The mask 200 is formed by selectively illuminating the excimer laser through the pattern mask layer 200.

As shown in FIG. 5, when the circuit pattern grooves 131 are formed by using a pseudo-molecular laser through the pattern mask layer 200, each circuit pattern groove 131 has a trapezoidal edge or a rectangular edge as shown in the figure. 5 is shown.

At this time, a recess having a region larger than the upper portion exposed by the via hole 135 may be formed in a region having the via holes 135, and the via holes 135 may have a layered structure in this manner.

If the via holes 135 have a layered structure, the expanded upper portions of the via holes 135 can be used as pads of the mounting device, thereby ensuring the mounting area of the device.

Then, the slag on the surface of the insulating layer 130 is removed by performing a desmear process.

In detail, after the surface of the insulating layer 130 is bumped, the protruding insulating layer 130 is removed by using permanganate, and a wet etching process is performed to neutralize the insulating layer 130. Thereby removing the insulating layer.

The surface of the insulating layer 130 may be roughened by a desmear process.

Then, as shown in FIG. 6, the metal layer 140 is formed on the insulating layer 130.

The metal layer 140 can be formed by an electroless plating method.

The electroless plating method can be a degreasing process, a soft etching process, a pre-catalyst process, a catalytic treatment process, an accelerator process, and no electricity. The electroplating process and the sequence of an anti-oxidation treatment process are carried out. Further, the metal layer 140 can be formed by sputtering metal particles using a plasma.

The metal layer 140 contains an alloy containing copper (Cu), nickel (Ni), palladium (Pd), or chromium (Cr).

Then, as shown in FIG. 7, a metal layer 140 is used as a sub-layer, and an electroplating process is performed on a conductive material to form a plating layer 155.

The plating layer 155 can be formed by performing an electroplating process using the metal layer 140 as a sub-layer, and according to a plating region, the electroplating process can simultaneously control current while being performed.

The plating layer 155 may include copper (Cu) exhibiting high conductivity.

In this example, the plating layer 155 is formed with a first thickness h2 from the upper surface of the insulating layer 130.

Next, as shown in FIG. 8, the plating layer 155 is etched through a half etching process. The plating layer 155 has a second thickness h3.

The second thickness h3 obtained by the half etching process satisfies the thickness h2 of 1/3 or less than 1/3.

Next, as shown in FIG. 9, a chemical mechanical etching is performed to remove the plating layer 155 on the insulating layer 130.

In other words, referring to FIG. 9, after the PCB 100 is placed on a plate 310, the over-plated plating layer 155 is ground under a basic atmosphere of pH 9 or above. Preferably, the overplating plating layer 155 is ground by adding ammonia as a main component and a slurry to which a small amount of peroxide is added.

A grinder 320 is rotated on the bottom plate 310 to induce physical etching of the overplating plating layer 155 and the polishing liquid.

Therefore, as shown in FIG. 9, the plating layer 155 is etched by chemical mechanical etching until the insulating layer 130 is exposed, so that the plating layer remaining on the insulating layer 130 is removed.

The bottom plate 310 may have a diameter of 1300 mm or less. Further, the bottom plate 310 may be provided with a heat wire so that heat is transferred to the PCB 100. Therefore, the PCB 100 having a size of 510 mm × 410 mm or more can be simultaneously etched, so that a plating layer having a large area can be removed.

If chemical mechanical etching is performed, the upper surface of the second circuit pattern 150 coincides with the upper surface of the insulating layer 130.

Next, as shown in FIG. 10, the central regions of the second circuit pattern 150 and the via 151 are etched by performing a flash etching process, so the second circuit pattern 150 and the via layer The central area of the window 151 is a concave recess.

The metal particles remaining on the surface of the insulating layer 130 are removed through the flash etching process to prevent an electrical short between the patterns.

In other words, referring to Figures 11 and 12, after the chemical mechanical etching is performed, if a component of the surface of the insulating layer 130 is detected, copper (Cu) is detected in addition to carbon (C) and oxygen (O). ). In this example, after the chemical mechanical etching and flash etching processes are performed, if the composition of the surface of the insulating layer 130 is detected, copper (Cu) will not be detected at all.

Hereinafter, a PCB according to another embodiment will be explained with reference to FIG.

Referring to FIG. 13, a PCB includes an insulating plate 110, a first circuit pattern 120 formed on the insulating plate 110, the insulating layer 130, and the second circuit patterns 150.

The insulating plate 110 may include a thermosetting substrate, a thermoplastic polymer substrate, a ceramic substrate, an inorganic composite material substrate, or a glass woven impregnation substrate. If the insulating sheet 110 contains a polymer resin, the insulating sheet 110 may include an epoxy-based insulating resin, or may include a polyamid-based resin.

The first circuit pattern 120 is formed on the insulating plate 110 as a base circuit pattern.

Further, the first circuit pattern 120 may include a material exhibiting high electrical conductivity and low electrical resistivity. In particular, the first circuit pattern 120 can be formed by patterning a thin copper film as a conductive layer. If the first circuit pattern 120 is a copper film and the insulating plate 110 contains a resin, the first circuit pattern 120 and the insulating plate 110 may have a typical copper foil laminate (CCL) structure.

At the same time, the insulating layer 130 is formed by burying the first circuit pattern 120 on the insulating plate 110.

The insulating layer 130 may include a plurality of insulating layers 130, and each of the insulating layers 130 may include a polymer resin.

The insulating layer 130 includes the via holes 135 to expose the first circuit patterns 120 and the circuit pattern grooves 131 for forming the second circuit patterns 150.

In this case. Each of the circuit pattern grooves 131 has a curved cross section and, preferably, has a U-shaped cross section.

Each of the circuit pattern grooves 131 has a width in the range of 3 μm to 25 μm and a depth in the range of 3 μm to 25 μm. Further, the via hole 135 has a diameter of about 80 μm or less and a depth of about 100 μm or less.

A metal layer 140 is formed in the via holes 135 of the insulating layer 130 and in the circuit pattern recess 131 along the U shape of the circuit pattern recess 131.

The metal layer 140 may serve as a sub-layer and may include copper (Cu), nickel (Ni), or an alloy thereof.

A second circuit pattern 150 and a via 151 are formed on the metal layer 140 to fill the circuit pattern recess 131 and the via 135.

The second circuit pattern 150 and the via 151 are simultaneously formed, and may include aluminum (Al), copper (Cu), silver (Ag), platinum (Pt), nickel (Ni), and palladium (Pd). An alloy of at least one of them. The second circuit pattern 150 and the via 151 may be formed by performing an electroplating process using the metal layer 140 as a sublayer.

As for the PCB 400 of FIG. 13, the circuit pattern groove 131 of the insulating layer 130 has a curved shape, and a metal is filled in the curved circuit pattern groove 131, thereby forming the second circuit pattern 150.

Further, even in the PCB 400 of FIG. 13, since the flash etching is performed after the chemical mechanical polishing, the upper surface of the second circuit pattern and the via has a concave shape similar to that of the PCB 100 of FIG.

As described above, the second circuit pattern 150 is formed in a curved shape without an edge, thereby preventing the resistance from being concentrated on the edge, so that no signal noise is generated, and thus heat is prevented from increasing at the edge.

While the present invention has been described above in terms of the preferred embodiments thereof, it is not intended to limit the invention, and the equivalent of the modification and retouching of the present invention is still within the spirit and scope of the present invention. Within the scope of patent protection of the present invention.

100‧‧‧PCB

110‧‧‧Insulation board

120‧‧‧First circuit pattern

130‧‧‧Insulation

131‧‧‧Circuit pattern groove

135‧‧‧through holes

140‧‧‧metal layer

150‧‧‧second circuit pattern

H1‧‧‧ thickness

Claims (18)

A method of manufacturing a printed circuit board, the method comprising: preparing an insulating substrate; forming a circuit pattern groove on a surface of the insulating substrate; plating a first metal layer on the substrate of the insulating substrate; The first metal layer of the circuit pattern recess is used as a sub-layer to perform an electroplating process to form a plating layer to embed the circuit pattern recess; the electroplating is removed by chemical mechanical polishing until an insulating layer is exposed The layer is formed to form a buried pattern; and a concave pattern is formed on an upper surface of the buried pattern by a flash etching. The method of claim 1, wherein the circuit pattern recess is formed on the surface of the insulating substrate, the circuit pattern recess being formed by using a laser. The method of claim 1, wherein the plating layer is removed by passing the chemical mechanical polishing until the insulating layer is exposed to form the buried pattern by using a polishing liquid. It is removed under a basic atmosphere of pH 9 or above. The method of claim 3, wherein the basic atmosphere is formed by mixing ammonia and a peroxide with a slurry. The method of claim 4, wherein the chemical mechanical polishing etches the printed circuit board on a substrate while applying heat to the printed circuit board under the substantially atmospheric atmosphere. The method of claim 1, wherein the insulating substrate comprises: preparing an insulating plate: forming a base circuit pattern on the insulating plate by patterning a thin copper film; and the insulating plate Forming an insulating layer thereon while covering the base circuit pattern, and Wherein the circuit pattern recess is formed on a surface of the insulating layer. The method of claim 1, further comprising forming a via hole exposing the base circuit pattern in the insulating layer after the insulating layer is formed. The method of claim 1, further comprising reducing the thickness of the plating layer by performing a half etching process before the chemical mechanical polishing is performed. The method of claim 8, wherein the half etching is performed to reduce the thickness of the plating layer to 1/3. The method of claim 1, wherein the first metal layer comprises a group selected from the group consisting of copper (Cu), nickel (Ni), palladium (Pd), chromium (Cr), and alloys thereof. A printed circuit board comprising: an insulating substrate, a plurality of circuit pattern grooves formed on a surface of the insulating substrate; and a plurality of circuit patterns formed by filling the circuit pattern grooves, wherein each circuit pattern An upper surface is formed with a concave pattern. The printed circuit board of claim 11, wherein each of the circuit pattern grooves and each buried circuit pattern has a curved cross section. The printed circuit board of claim 11, wherein the circuit pattern recess and the buried circuit pattern have a U-shaped cross section. The printed circuit board of claim 11, wherein the insulating substrate comprises: an insulating plate; a base circuit pattern patterned on the insulating plate; and an insulating layer formed on the insulating plate to cover the same a base circuit pattern, wherein the circuit pattern recess is formed on a surface of the insulating layer. The printed circuit board of claim 14, wherein the insulating layer comprises a via hole to expose the base circuit pattern. The printed circuit board of claim 15 further comprising a via to fill the via, wherein an upper surface of the via is formed with a concave pattern. The printed circuit board of claim 11, further comprising a metal layer formed along the circuit pattern recess. The printed circuit board of claim 17, wherein the metal layer comprises a group selected from the group consisting of copper (Cu), nickel (Ni), palladium (Pd), chromium (Cr), and alloys thereof.