KR101231362B1 - The printed circuit board and the method for manufacturing the same - Google Patents

Abstract

The present invention relates to a printed circuit board, wherein the substrate covers an insulating substrate, a first circuit pattern on the insulating substrate, a first insulating layer covering the first circuit pattern and including a via hole, and the via hole on the first insulating layer. A second insulating layer including a via pad hole aligned with the via hole, and a via filling the via hole and the via pad hole, wherein the via includes a via body filling the via hole, a metal layer formed on the via body, and And an upper via pad filling the via pad hole on the metal layer. Therefore, by forming the buried circuit pattern through a separate process from the via, variation in plating thickness may be minimized, thereby forming a uniform buried circuit pattern.

Description

[0001] The present invention relates to a printed circuit board and a method of manufacturing the same,

The present invention relates to a printed circuit board and a method of manufacturing the same.

Printed Circuit Boards (PCBs) are like copper on electrically insulating substrates.

Is formed by printing a circuit line pattern with a conductive material, and refers to a board immediately before mounting an electronic component. That is, it means the circuit board which fixed the mounting position of each component, and printed and fixed the circuit pattern which connects components to the flat surface surface, in order to mount many electronic elements of various types densely on a flat plate.

1A and 1B illustrate a typical printed circuit board.

Referring to FIGS. 1A and 1B, a general printed circuit board 10 forms circuit patterns 2 and 3 on a conductive substrate 1 using a conductive material such as copper.

The circuit patterns 2 and 3 may be formed by inclining the side surface of the circuit pattern 2 at a predetermined angle with respect to the plane of the substrate 1 as shown in FIG. 1A according to the forming method, and as shown in FIG. 1B. (3) can be formed perpendicular to the plane of the substrate (1).

However, as shown in FIGS. 1A and 1B, when the circuit patterns 2 and 3 are formed on the substrate 1, there is a limit in forming the fine circuit patterns 2 and 3 because the surface of the upper surface of the substrate 1 is uneven. .

Accordingly, in order to cope with high performance and miniaturization of electronic components, a buried pattern substrate that can reduce the thickness of the printed circuit board 10 and planarize the surface of the substrate 1 has been used.

The printed circuit board on which the buried pattern is formed may have a very high bonding force with the insulating member due to the structure of the base circuit pattern and the contact portion, and the pitch of the base circuit pattern and the contact portion may be uniformly and finely formed.

The embodiment provides a printed circuit board and a manufacturing method thereof, in which a circuit pattern advantageous for signal transmission is formed.

The present invention includes an insulating substrate, a first circuit pattern on the insulating substrate, a first insulating layer covering the first circuit pattern and including a via hole, and a via pad hole aligned with the via hole on the first insulating layer. A second insulating layer, and a via filling the via hole and the via pad hole, wherein the via includes a via body filling the via hole, a metal layer formed on the via body, and filling the via pad hole on the metal layer. And an upper via pad.

On the other hand, the present invention comprises the steps of preparing an insulating substrate, forming a via hole by etching the insulating substrate, forming a via body filling the via hole, forming an upper insulating layer covering the insulating substrate, Forming a via pad hole in the upper insulating layer to open the via body; forming a seed layer on the upper insulating layer surface and the upper surface of the via body; electroplating the seed layer with a seed to form the via pad hole. Forming a buried plating layer, and etching the plating layer and the seed layer to expose the upper insulating layer to form an upper via pad.

According to the present invention, the thickness of the plating may be minimized by forming the buried circuit pattern through a separate process from the via. In addition, by varying the desmear conditions for the via and the buried circuit pattern, plating may be performed in an optimized state, and variations in the plating thickness may be minimized, thereby forming a uniform buried circuit pattern.

1A and 1B are cross-sectional views of a printed circuit board according to the prior art.
2 is a cross-sectional view of a printed circuit board according to the present invention.
3 to 12 are cross-sectional views illustrating a method for manufacturing the printed circuit board of FIG. 2.
13 to 15 are cross-sectional views illustrating another method for manufacturing the printed circuit board of FIG. 2.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

Throughout the specification, when a part is said to "include" a certain component, it means that it can further include other components, without excluding other components unless specifically stated otherwise.

In order to clearly illustrate the present invention in the drawings, thicknesses are enlarged in order to clearly illustrate various layers and regions, and parts not related to the description are omitted, and like parts are denoted by similar reference numerals throughout the specification .

Whenever a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case where it is "directly on" another portion, but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

The present invention provides a printed circuit board in which a via and a circuit pattern are processed in a separate process so that the circuit pattern is uniformly formed in the printed circuit board having the circuit pattern embedded.

Hereinafter, a printed circuit board according to the present invention will be described with reference to FIGS. 2 to 12.

2 is a cross-sectional view of a printed circuit board according to the present invention.

Referring to FIG. 2, the printed circuit board 100 according to the present invention includes an insulating plate 110, a first circuit pattern 110, a first insulating layer 130, and a second formed on the insulating plate 110. The insulating layer 140 and the plurality of second circuit patterns 145 are included.

The insulating plate 110 may be a supporting substrate of a printed circuit board having a single circuit pattern formed therein, but may also mean an insulating layer region in which one circuit pattern is formed among printed circuit boards having a plurality of stacked structures.

When the insulating plate 110 means one insulating layer among a plurality of stacked structures, a plurality of circuit patterns may be continuously formed on the upper or lower portion of the insulating plate 110.

The insulation plate 110 may be a thermosetting or thermoplastic polymer substrate, a ceramic substrate, an organic-inorganic composite material substrate, or a glass fiber impregnated substrate. When the insulation plate 110 includes a polymer resin, the insulation plate 110 may include an epoxy-based insulation resin. It may alternatively include polyimide resin.

A plurality of first circuit patterns 120 are formed on the insulating plate 110 as base circuit patterns.

The first circuit pattern 120 is formed of a material having high electrical conductivity and low resistance. The first circuit pattern 120 may be formed by patterning a copper foil, which is a thin copper layer, as a conductive layer, and the first circuit pattern 120 is a copper foil layer and the insulation. When the plate 110 includes a resin, the first circuit pattern 120 and the insulating plate 110 may be a conventional copper clad laminate (CCL).

The first circuit pattern 120 includes a lower via pad 121 that is electrically connected to the second circuit pattern 145 and the via.

The lower via pad 121 may have a larger width than the other first circuit pattern 120 and may have a width wider than a lower surface of the via body 132.

Meanwhile, a first insulating layer 130 is formed by filling the first circuit pattern 110 on the insulating plate 110.

The first insulating layer 130 may be formed of a plurality of insulating layers, each of the first insulating layer 130 may be a polymer resin.

The first insulating layer 130 includes a via hole 135 exposing the first circuit pattern 120.

A lower diameter of the via hole 135 may satisfy about 80 μm or less, and a depth may satisfy about 100 μm or less, and the width of the via hole 135 may increase toward an upper portion thereof.

A via body 132 may be formed in the first insulating layer 130 to bury the inside of the via hole 135.

The via body 132 may increase in width toward the top along the shape of the via hole 135.

The via body 132 may be formed of an alloy including at least one of a group containing copper, silver, tin, gold, nickel, or palladium, and preferably, may be an alloy including copper.

The via body 132 may further include a first seed layer 131 between the side surface of the via hole 135, and the first seed layer 131 may be copper, gold, nickel, palladium, or indium. , Titanium or tin may be formed of an alloy including at least one of the group or a conductive polymer material having conductivity including the alloy.

Meanwhile, a second insulating layer 140 is formed on the first insulating layer 130.

The second insulating layer 140 may be made of the same polymer resin as the first insulating layer 130, and the thickness t2 of the second insulating layer 140 may be equal to the thickness of the second circuit pattern 145. Can be.

In this case, the thickness t2 of the second insulating layer 140 may be smaller than the thickness t1 of the first insulating layer 130.

The second insulating layer 140 includes a circuit pattern hole 147 for forming the second circuit pattern 145 and a via pad hole 148 exposing an upper surface of the via body 132.

The circuit pattern hole 147 and the via pad hole 148 have the same depth, the circuit pattern for the width of the holes 147 is from 3 to 15 μ m, the depth of the pattern is to meet a 3 to 15 μ m have.

The via pad hole 148 may be formed to have a wider width than an upper surface of the via body 132, and may have a shape in which a cross section thereof becomes wider toward an upper portion thereof.

The second circuit pattern 145 and the upper via pad 142 are formed in the circuit pattern hole 147 and the via pad hole 148 of the second insulating layer 140, respectively.

The second seed layer 141 is formed on side surfaces and bottom surfaces of the circuit pattern hole 147 and the via pad hole 148 along the shapes of the circuit pattern hole 147 and the via pad hole 148.

The second circuit pattern 145 and the upper via pad 142 may be formed of the same material as the via body 132, and the second seed layer 141 may be the same as the first seed layer 131. It can be formed of a material.

As such, the printed circuit board 100 may include a first insulating layer 130 on which the via body 132 is formed and an upper circuit pattern 145 and an upper via pad 142 on the first insulating layer 130. The second insulating layer 140 is formed separately to form the via body 132 and the upper circuit pattern 145, respectively.

Accordingly, each of the vias may include a lower via pad 121 that is part of the first circuit pattern 120, a via body 132 on the via pad 121, and an upper via pad 142 on the via body 132. It is formed by forming a metal layer. In addition, the first and second seed layers 131 and 141 are formed between the metal layers to form a boundary.

In addition, only the second insulating layer 140 includes a circuit pattern hole 147 for the second circuit pattern 145, and the first insulating layer 130 has a structure including only the via hole 135.

Hereinafter, a method of manufacturing the printed circuit board 100 of FIG. 2 will be described with reference to FIGS. 3 to 12.

3 to 12 are cross-sectional views illustrating a first method for manufacturing the printed circuit board of FIG. 2.

First, as shown in FIG. 3, the first circuit pattern 120 is formed on the insulating plate 110, the first circuit pattern 120 is embedded, and the first insulating layer 130 is formed.

The insulating plate 110 and the first circuit pattern 120 may be formed by etching the copper foil layer of the CCL according to the design of the first circuit pattern 120. Alternatively, the copper foil layer may be stacked on the ceramic substrate. It may also be formed by etching.

In this case, the first circuit pattern 120 may also include a lower via pad 121 connected to the first circuit pattern 150 through the via hole 135 as shown in FIG. 3.

The first insulating layer 130 includes a thermosetting resin, and may be formed by applying a semi-cured resin, which is not completely cured, to a predetermined thickness on the insulating plate 110, and curing by applying heat and pressure. It is also possible to form a layer of.

Next, as shown in FIG. 4, a via hole 135 exposing the lower via pad 121 is formed in the first insulating layer 130. The via hole 135 may be formed to have a side surface inclined at a predetermined angle with respect to the plane of the substrate. Alternatively, the via hole 135 may be formed to have a side surface perpendicular to the plane of the substrate.

The via hole 135 may be formed using the laser 300 of FIG. 4. In this case, the laser 300 may be formed using a UV laser or a CO ₂ laser.

In addition, the via hole 135 may be formed by a physical method, that is, by drilling, or may be formed by selective etching by a chemical method.

Next, as shown in FIG. 5, the metal layer 136 forming the first seed layer 131 is formed on the first insulating layer 130.

The metal layer 136 may be formed by an electroless plating method.

The electroless plating method may be performed by treating the degreasing process, the soft corrosion process, the precatalyst process, the catalyst process, the activation process, the electroless plating process, and the anti-oxidation process.

In this case, plating may be promoted by desmearing the surface of the first insulating layer 130 before the electroless plating.

That is, after the surface of the first insulating layer 130 is inflated, roughness is imparted through a wet process of removing the inflated second insulating layer using permanganate and neutralizing the surface of the first insulating layer 130.

Alternatively, roughness may be applied to the surface of the first insulating layer 130 through a dry plasma process using plasma at low vacuum.

The metal layer 136 may be formed of an alloy including at least one of a group containing copper, gold, nickel, palladium, indium, titanium, or tin, or a conductive high molecular material including the alloy.

In addition, when the metal layer 136 is formed of an alloy, it may be formed by sputtering metal particles using plasma.

Next, as shown in FIG. 6, a plating layer 137 is formed to fill the via hole 135 by applying power to the metal layer 136 and plating metal.

The plating layer 137 may be formed of an alloy including at least one of a group containing copper, silver, tin, gold, nickel, or palladium, and preferably, may be an alloy including copper.

Next, as shown in FIG. 7, the via body 132 filling the via hole 135 by etching the plating layer 137 and the metal layer 136 until the top surface of the first insulating layer 130 is exposed. A first seed layer 131 is formed below the via body 132.

Accordingly, the first seed layer 131 formed along the inner surface of the via hole 135 and the via body 132 filling the via hole 135 are formed in the via hole 135.

Next, as shown in FIG. 8, the second insulating layer 140 is formed on the first insulating layer 130.

The second insulating layer 140 may have a thickness smaller than that of the first insulating layer 130 and may have the same thickness as that of the second circuit pattern 145.

A circuit pattern hole 147 for forming the second circuit pattern 145 is formed in the second insulating layer 140.

In FIG. 9, the circuit pattern hole 147 may be formed using an excimer laser that emits a laser beam having a wavelength in the ultraviolet region. As the excimer laser, KrF excimer laser (krypton fluorine, center wavelength 148 nm), or ArF excimer laser (argon fluoride, center wavelength 193 nm) may be applied.

When the circuit pattern hole 147 is formed through an excimer laser, a pattern mask for simultaneously forming the circuit pattern hole 147 is formed, and is formed by selectively irradiating the excimer laser through the pattern mask 400. can do.

As such, when the circuit pattern hole 147 is formed using the excimer laser, the cross section of the pattern hole 147 is formed to have an edge of a trapezoidal or rectangular shape as shown in FIG. 9.

 In this case, the via pad hole 148 is formed to open the via body 132 and have a wider width than the upper surface of the via body 132.

Therefore, the via hole 135 and the via pad hole 148 of the first insulating layer 130 forming the via are formed in a layered structure so that a via region formed in the via pad hole 148 may be mounted. It can be used as a pad for securing the area for mounting the device.

Next, as shown in FIG. 10, the metal layer 146 for forming the second seed layer 141 is formed along the upper surface of the second insulating layer 130.

In this case, roughness may be provided by performing a desmear process on the second insulating layer 140.

That is, after the surface of the second insulating layer 140 is inflated, the roughness is removed through a wet process of removing the expanded second insulating layer 140 using permanganate and neutralizing the surface of the second insulating layer 140. Grant.

Alternatively, roughness may be applied to the surface of the second insulating layer 140 through a dry plasma process using plasma at low vacuum.

 The metal layer 146 may be formed of an electroless plating, and the electroless plating method may include a degreasing process, a soft corrosion process, a precatalyst process, a catalyst process, an activation process, an electroless plating process, and an anti-oxidation process. Can proceed by processing.

The metal layer 146 may be formed of an alloy including at least one of a group containing copper, gold, nickel, palladium, indium, titanium, or tin, or a conductive high molecular material including the alloy.

In addition, when the metal layer 146 is formed of an alloy, it may be formed by sputtering metal particles using plasma.

Next, as shown in FIG. 15, a plating layer 149 is formed to fill the via pad hole 148 and the circuit pattern hole 147 by applying power to the metal layer 146 and plating metal.

The plating layer 149 may be formed of an alloy including at least one of a group containing copper, silver, tin, gold, nickel, or palladium, and preferably may be an alloy including copper.

Next, as shown in FIG. 12, the plating layer 149 and the metal layer 146 are etched until the second insulating layer 140 is exposed to form the second circuit pattern 145 and the upper via pad 142. do.

In this case, a second seed layer 141 is formed between the second insulating layer 140, the second circuit pattern 145, and the upper via pad 142.

As such, by performing a plating process for forming the via body 132 and the second circuit pattern 145 in a separate process, a partial region may be overetched or not etched when the plating layer is etched according to the plating thickness difference. You can prevent it.

Therefore, device reliability can be ensured by preventing short circuits or errors in signal transmission between neighboring circuit patterns.

Hereinafter, another method of manufacturing the printed circuit board 100 of FIG. 2 will be described with reference to FIGS. 13 to 15.

In the method of FIGS. 13 to 15, the first insulating layer 130 is formed as shown in FIGS. 3 and 4, and the process of forming the via holes 135 in the first insulating layer 130 proceeds in the same manner.

Next, as shown in FIG. 13, the via body 132 may be formed by filling the conductive paste in the via hole 135.

The conductive paste may be formed of an alloy including at least one of a group containing copper, silver, tin, gold, nickel, or palladium, and preferably may be an alloy including copper.

The via body 132 may be formed by applying a conductive paste and pressing the roller 350 or the like, and may be formed by pressing the conductive coin.

Next, as shown in FIG. 14, the second insulating layer 140 is formed on the first insulating layer 130.

The second insulating layer 140 may have a thickness smaller than that of the first insulating layer 130 and may have the same thickness as that of the second circuit pattern 145.

A circuit pattern hole 147 for forming the second circuit pattern 145 is formed in the second insulating layer 140.

In FIG. 14, the circuit pattern hole 147 may be formed using an excimer laser that emits a laser beam having a wavelength in the ultraviolet region. As the excimer laser, KrF excimer laser (krypton fluorine, center wavelength 148 nm), or ArF excimer laser (argon fluoride, center wavelength 193 nm) may be applied.

In this case, the via pad hole 148 is formed to open the via body 132 and have a wider width than the upper surface of the via body 132.

Therefore, the via hole 135 and the via pad hole 148 of the first insulating layer 130 forming the via are formed in a layered structure so that a via region formed in the via pad hole 148 may be mounted. It can be used as a pad for securing the area for mounting the device.

Next, as shown in FIG. 15, the metal layer 146 for forming the second seed layer 141 is formed along the upper surface of the second insulating layer 130.

In this case, roughness may be provided by performing a desmear process on the second insulating layer 140.

That is, after the surface of the second insulating layer 140 is inflated, the roughness is removed through a wet process of removing the inflated second insulating layer 140 using permanganate and neutralizing the surface of the second insulating layer 140. Grant.

Alternatively, roughness may be applied to the surface of the second insulating layer 140 through a dry plasma process using plasma at low vacuum.

 The metal layer 146 may be formed by electroless plating.

The metal layer 146 may be formed of an alloy including at least one of a group containing copper, gold, nickel, palladium, indium, titanium, or tin, or a conductive high molecular material including the alloy.

In addition, when the metal layer 146 is formed of an alloy, it may be formed by sputtering metal particles using plasma.

Next, as shown in FIG. 15, a plating layer 149 is formed to fill the via pad hole 148 and the circuit pattern hole 147 by applying power to the metal layer 146 and plating metal.

The plating layer 149 may be formed of an alloy including at least one of a group containing copper, silver, tin, gold, nickel, or palladium, and preferably may be an alloy including copper.

Finally, the plating layer 149 and the metal layer 146 are etched until the second insulating layer 140 is exposed to form the second circuit pattern 145 and the upper via pad 142 of FIG. 2.

In the above method, the via body 132 may be formed using a conductive paste instead of plating, thereby forming a via without a seed layer.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

The printed circuit board 100
Insulation Plate 110
First Circuit Pattern 120
First Insulation Layer 130
Second Insulation Layer 140
Second Circuit Pattern 145
Via Body 132

Claims (16)

Insulating substrate,
A first circuit pattern on the insulating substrate,
A first insulating layer covering the first circuit pattern and including a via hole,
A second insulating layer including a via pad hole and a plurality of circuit pattern holes aligned with the via hole on the first insulating layer;
A second circuit pattern formed by filling the plurality of circuit pattern holes, and
Vias filling the via holes and the via pad holes
Including;
The vias
Via body filling the via hole,
A metal layer formed on the via body, and
An upper via pad filling the via pad hole on the metal layer
Including,
The via pad hole and the circuit pattern hole are formed through the second insulating layer. The method of claim 1,
The via pad hole has a width greater than the width of the via hole. The method of claim 1,
The second insulating layer has a thickness smaller than the first insulating layer. delete The method of claim 1,
The first circuit pattern includes a lower via pad aligned with the via body. The method of claim 5,
The printed circuit board further comprises a metal layer between the lower via pad and the via body. The method according to claim 6,
The metal layer between the lower via pad and the via body and between the via body and the upper via pad is formed of the same material. The method according to claim 6,
The metal layer between the lower via pad and the via body and between the via body and the upper via pad is formed of an alloy comprising at least one of a group comprising copper, gold, nickel, palladium, indium, titanium or tin. Printed circuit board. The method of claim 1,
The via body is formed of an alloy comprising at least one of a group containing copper, silver, tin, gold, nickel or palladium. Preparing an insulating substrate,
Etching the insulating substrate to form via holes;
Forming a via body filling the via hole;
Forming an upper insulating layer covering the insulating substrate,
Simultaneously forming a via pad hole and a plurality of circuit pattern holes through the upper insulating layer to open the via body;
Forming a seed layer on a surface of the upper insulating layer and on an upper surface of the via body;
Electroplating the seed layer with a seed to form a plating layer filling the via pad hole and the circuit pattern hole; and
Etching the plating layer and the seed layer to expose the upper insulating layer to form an upper via pad and an upper circuit pattern
And a step of forming the printed circuit board. The method of claim 10,
Forming the via body,
Forming a seed layer on the front surface of the via hole, and
Electroplating the seed layer with a seed to form a plating layer filling the via hole; and
Etching the plating layer and the seed layer until the insulating substrate is exposed to form the via body
And a step of forming the printed circuit board. The method of claim 11,
The metal layer of the upper and lower portions of the via body is formed by electroless plating of the same material. The method of claim 11,
Forming the via body,
A method of manufacturing a printed circuit board to apply a conductive paste so as to fill the via hole. delete The method of claim 10,
Preparing the insulating substrate,
Preparing the insulation plate,
Patterning a copper foil layer on the insulating plate to form a base circuit pattern, and
Covering the base circuit pattern, and forming an insulating layer on the insulating plate,
The via hole may be formed by etching the insulating layer to expose the base circuit pattern. 16. The method of claim 15,
The insulating layer is a manufacturing method of a printed circuit board thicker than the upper insulating layer.

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