TW201110206A - Method for cleaning a semiconductor device - Google Patents
Method for cleaning a semiconductor device Download PDFInfo
- Publication number
- TW201110206A TW201110206A TW099116885A TW99116885A TW201110206A TW 201110206 A TW201110206 A TW 201110206A TW 099116885 A TW099116885 A TW 099116885A TW 99116885 A TW99116885 A TW 99116885A TW 201110206 A TW201110206 A TW 201110206A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- main surface
- cleaning
- insulating layer
- gate
- Prior art date
Links
Classifications
-
- H10P70/234—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H10D64/0112—
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009151288A JP5326113B2 (ja) | 2009-06-25 | 2009-06-25 | 半導体装置の洗浄方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201110206A true TW201110206A (en) | 2011-03-16 |
Family
ID=43381215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW099116885A TW201110206A (en) | 2009-06-25 | 2010-05-26 | Method for cleaning a semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US20100330794A1 (enExample) |
| JP (1) | JP5326113B2 (enExample) |
| TW (1) | TW201110206A (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104658966A (zh) * | 2013-11-21 | 2015-05-27 | 中芯国际集成电路制造(上海)有限公司 | 制作高k金属栅晶体管的接触孔的方法 |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5729571B2 (ja) | 2011-07-11 | 2015-06-03 | 栗田工業株式会社 | メタルゲート半導体の洗浄方法 |
| TWI517235B (zh) * | 2013-03-01 | 2016-01-11 | 栗田工業股份有限公司 | 半導體基板洗淨系統以及半導體基板的洗淨方法 |
| FR3013502A1 (fr) | 2013-11-20 | 2015-05-22 | Commissariat Energie Atomique | Procede de protection d’une couche de siliciure |
| US9536877B2 (en) * | 2014-03-03 | 2017-01-03 | Globalfoundries Inc. | Methods of forming different spacer structures on integrated circuit products having differing gate pitch dimensions and the resulting products |
| JP6737436B2 (ja) | 2015-11-10 | 2020-08-12 | 株式会社Screenホールディングス | 膜処理ユニットおよび基板処理装置 |
| JP2017157863A (ja) * | 2017-06-06 | 2017-09-07 | セントラル硝子株式会社 | ウェハの洗浄方法 |
| US11152213B2 (en) * | 2019-03-01 | 2021-10-19 | International Business Machines Corporation | Transistor device with ultra low-k self aligned contact cap and ultra low-k spacer |
| CN115802743B (zh) * | 2022-11-11 | 2025-07-15 | 上海积塔半导体有限公司 | 半导体测试结构及其制备方法 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6664196B1 (en) * | 1999-03-15 | 2003-12-16 | Matsushita Electric Industrial Co., Ltd. | Method of cleaning electronic device and method of fabricating the same |
| JP3434750B2 (ja) * | 1999-09-30 | 2003-08-11 | Necエレクトロニクス株式会社 | 洗浄装置のライン構成及びその設計方法 |
| US7008872B2 (en) * | 2002-05-03 | 2006-03-07 | Intel Corporation | Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures |
| JP2006100378A (ja) * | 2004-09-28 | 2006-04-13 | Renesas Technology Corp | 半導体装置及びその製造方法 |
| KR100655647B1 (ko) * | 2005-07-04 | 2006-12-08 | 삼성전자주식회사 | 반도체 기판용 세정액 조성물, 이의 제조 방법, 이를이용한 반도체 기판의 세정 방법 및 반도체 장치의 제조방법 |
| JP4362785B2 (ja) * | 2006-09-28 | 2009-11-11 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
| JP2010205782A (ja) * | 2009-02-27 | 2010-09-16 | Renesas Electronics Corp | 半導体装置の製造方法 |
-
2009
- 2009-06-25 JP JP2009151288A patent/JP5326113B2/ja not_active Expired - Fee Related
-
2010
- 2010-05-26 TW TW099116885A patent/TW201110206A/zh unknown
- 2010-06-21 US US12/819,675 patent/US20100330794A1/en not_active Abandoned
-
2012
- 2012-12-05 US US13/706,056 patent/US20130189835A1/en not_active Abandoned
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104658966A (zh) * | 2013-11-21 | 2015-05-27 | 中芯国际集成电路制造(上海)有限公司 | 制作高k金属栅晶体管的接触孔的方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5326113B2 (ja) | 2013-10-30 |
| JP2011009452A (ja) | 2011-01-13 |
| US20100330794A1 (en) | 2010-12-30 |
| US20130189835A1 (en) | 2013-07-25 |
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