TW200847307A - Semiconductor device and fabricating method thereof - Google Patents

Semiconductor device and fabricating method thereof Download PDF

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Publication number
TW200847307A
TW200847307A TW096130832A TW96130832A TW200847307A TW 200847307 A TW200847307 A TW 200847307A TW 096130832 A TW096130832 A TW 096130832A TW 96130832 A TW96130832 A TW 96130832A TW 200847307 A TW200847307 A TW 200847307A
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Taiwan
Prior art keywords
layer
semiconductor device
conductive
wafer
polymer
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TW096130832A
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English (en)
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TWI377630B (en
Inventor
Kuo-Chin Chang
Han-Ping Pu
Pei-Haw Tsao
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Taiwan Semiconductor Mfg
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Publication of TW200847307A publication Critical patent/TW200847307A/zh
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Publication of TWI377630B publication Critical patent/TWI377630B/zh

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

200847307 九、發明說明： 【發明所屬之技術領域】 本發明係有關於晶圓級晶片尺寸封裝（wafer ievei chip scale packaging ; WLCSP)的技術，特別係關於用於 晶圓級晶片尺寸封裝之強化的銅導電柱。 【先前技術】 在過去數十年中在電子產品與半導體封裝技術的演 變，已衝擊到整體半導體工業。表面黏著技術 (surface-mount technology; SMT)與球閘陣列（bali grid army ; BGA)封裝技術的引進，對各式各樣的積體電路裝 置的南產出的封裝技術而言，是很重要的一步，而同時 亦可降低印刷電路板上的連接墊間距（pad pitch)。傳統 上’已封I的積體電路的基本結構是由極細的金線在晶 片上的金屬連接墊與封裝體的電極之間形成内連線，而 上述電極則延伸至封裝體的封裝膠體以外的區域。雙列 式封裝（dual inline package; DIP)或四面扁平封裝（叫以 flat package ; QFP)係現行積體電路封裝的基本結構，然 而設計於封裝體周邊並圍繞封裝體的引腳數量的增加， 通常造成引腳間距太小，而會對已封裝的晶片連接到主 機板時的良率造成影響。 晶片尺寸封裝（chip scale packaging ; CSP)與球閘陣 列封裝的技術對上述問題提供了相當的解決方案，可在 不大幅增加封裝尺寸的前提下，增加電極的分佈密度。 0503-A33148TWF/dwang 5 200847307 晶片尺寸封裝係使晶圓的封裝尺寸維持在晶片的尺度’ 其封裝後的尺寸通常是晶片的1.2倍，而藉由晶片尺寸封 裝技術的使用，而大幅減少可能的裝置大小。雖然上述 的優點可使電子裝置的尺寸得以最小化，但目前需求的 趨勢在於更小、更輕、更薄的消費性電子產品，則更需 要繼續使封裝尺寸最小化。 為了滿足市場上日與倶增之對尺寸最小化及功能上 的需求，近年來電子封裝業界係引入了晶圓級晶片尺寸 封裝（wafer level chip scale packaging ; WLCSP)的技術， 以增加裝置的密度、效能、與成本效益，同時又能減少 裝置的重量與尺寸。在晶圓級晶片尺寸封裝技術中，通 常是直接在晶片上完成與球閘陣列封裝體及凸塊電極的 接觸。近來所發展的電子裝置例如行動電話、可攜式電 腦、攝錄影機（camcorder)、個人數位助理（personal digital assistant ; PDA)、與其他類似裝置係使用小巧、輕量、薄 型、且非常高密度封裝的積體電路封裝體。對尺寸較小、 且具有較小的接點數量的晶片進行封裝時，對應於一片 晶圓上具有大量晶片，故使用晶圓級晶片尺寸封裝技術 通常較有利且可節省成本。 現行晶圓級晶片尺寸封裝技術的一項缺點是會在軟 銲料球狀物與導電柱之間產生裂缝，軟銲料球狀物或凸 塊通常係直接置於凸塊電極或導電柱上，形成銲點（solder joint)並固定而維持結構上的整體性。晶圓級晶片尺寸封 裝體是由數層不同的材料所構成，這些不同的材料通常 0503-A33148TWF/dwwang 6 200847307 具有不同的熱膨脹係數，因此，此一熱膨脹係數的差異 會使上述導電柱與凸塊電極之間的銲點，受到相對較大 的應力作用，而常常在上述凸塊電極/導電枉與上述軟銲 料球狀物或凸塊之間的連接處產生裂缝。 第1圖為一剖面圖，係顯示常見於一晶圓級晶片尺 寸封裝體10的一單一的軟銲料球狀物101，晶圓級晶片 尺寸封裝體10係直接形成於晶片1〇〇上，銅墊102則形 成於晶片100上，銅墊102係作為軟銲料球狀物101的 接點與連接墊。在銲接的過程中，在軟銲料球狀物101 與銅墊102之間的銲點會自然形成一層介金屬化合物 (intermetallic compound ; IMC)例如為介金屬化合物形成 層103。雖然介金屬化合物形成層1〇3的存在通常是意味 著軟銲料與基底之間的銲接良好，但是其通常是銲點中 最脆的部分。由於晶圓級晶片尺寸封裝體1〇中的銲點# 常小，在應力作用於銲點時，裂痕例如裂痕1〇4會較容 易產生，而因為封裝體整體尺寸的因素，裂痕1〇4就可 能較容易發生破壞。發生於軟銲料球狀物1〇1的一侧的 小裂痕例如裂痕104，會容易擴展到整個銲點的長度。 在標題為「MOUNTING STRUCTURE HAVING COLUMNAR ELECTRODES AND A SEALING FILM」、 由Kuwabara等人所提出的美國專利US 6,600,234中，已 揭露可減少因應力所造成的裂痕的方法，據記載此方法 係使用多層材料來形成一密封層，而凸塊接點的一部分 凸出於上述密封層。上述密封層係有助於吸收因熱膨脹 0503-A33148TWF/dwwang 7 200847307 係數的差異所產生的應力， 材料，使其具有漸變的熱 ：擇上处猞封層的各層 基底者的熱膨脹係數心厂而使？層膜中接近 板者的熱膨脹係數與電路板相近。此—漸^ ft 數係有助於緩和由劇列的 文、心％脹係 力。然而，上述密封; 強度，而無法減低任；=構仍具有較低的剪應力 進展，因此仍會降低整體銲點的可靠度。層的衣痕的 【發明内容】 有鑑於此，為了解、、表十 成所期望的技術效果，題的發生，而達 多個接腳狀物，其俤凸出 乂土声轭例係形成一或 電柱的上表面。級晶片尺寸封裳體的導 柱上時，軟銲料材料會將球狀物銲接於上述導電 接腳狀物不但能增加上述軟二。上述 間的銲點剪應力強度，亦可 '、述¥電桎之 狀物與上述軟銲料球狀物之間的=上述導電柱/接腳 連接的可靠度。還有，:、、面積’而增加了電性 於上诚f赴沾人Ρ /成一不規則的銲點可延缓來杰 於上迷I點的金屬間化合物中的 L㈣成 本發明的較佳實施例係 二*、、。 方法，包含形成至少一導、/、一 +導體裝置的製造 體晶圓上，其令上料電=(:nductive P⑽)於—半導 圓的一線路層。—或多個生連接至上述半導體晶 飞夕個導電接腳則形成於上述至少_ wang 0503-A33l48TWF/dw^ 8 200847307 導電柱的一表面上，其中上述一或多個導電接腳係自上 述表面處凸起。將一軟銲料球狀物銲至上述至少一導電 柱的上述表面上，其中上述軟銲料球狀物係將凸出於上 述表面的上述一或多個導電接腳封入其中。 本發明的較佳實施例係又揭露一種半導體裝置，包 含：一基底、一電路層於上述基底中、與一線路層於上 述基底的一第一表面上。上述線路層係電性連接於上述 電路層；一或多個電極凸出於上述第一表面，上述一或 多個電極係電性連接至上述線路層，並具有凸出於上述 一或多個電極的一上表面的一或多個接腳狀物；一軟銲 料球狀物連接於上述上表面，並將上述一或多個接腳狀 物封入其中。 本發明的較佳實施例係又揭露一種半導體裝置的製 造方法，包含形成一線路層於一半導體晶片中。一聚合 物絕緣層係沈積於上述半導體晶片的一第一表面上。一 或多個電極的形成係使其穿透上述聚合物絕緣層，其中 上述一或多個電極係電性連接至上述線路層。至少一接 腳狀物的形成係使其凸出於上述一或多個電極的一上表 面。將一軟銲料球狀物銲至每一個上述一或多個電極之 上，上述軟銲料球狀物係將上述至少一接腳狀物封入其 中。 本發明的較佳實施例係又揭露一種半導體裝置，包 含：一基底、一或多個線路層於上述基底的一第一表面 中、與一聚合物絕緣層於上述第一表面上。上述聚合物 0503- A3 3148T WF/d wwang 9 200847307 取多個導電柱 絕緣層具有 透上述聚合物絕緣層而位於上心電柱係穿 絕緣層的-上表面之間，其中多面以聚合物 性f接至與其對應的上述-或多個線路層的；；；係電 -軟鋅科球狀物係連接於每_個上述—或。 一上表面，並將凸出於上述-或多個導電柱的上 面的一或多個導電接腳封入其中。 处上表 本發明的較佳實施例的一 形成’其最後是封入軟焊料球狀物中，的 晶片尺寸封裝體整體的剪應力強度。 .曰圓級 本卷明的較佳實施例的另一項優點泰 善。所增加的接腳狀物會增加電極性的改 的表面積。因此，稽加了軟焊料球狀之間 性連接的可靠度。 。电極之間的電 本發明的較佳實施例的另一項 :::力，上述裂痕係存在於介金屬化合“了 =擴 使形成於接點一端::二:::::僅是-直線，而 麵的’丨孟屬化合物層中的p、危a、丄 地擴展而橫跨整個銲點。 法容易 【實施方式】 特徵、和優點能】 並配合所附圖式， 為讓本發明之上述和其他目的 明顯易懂，下文特舉出較佳實施例 〇5〇3-A33l48TWF/dwwang 10 200847307 作詳細說明如下： 以下係以一特定的架構，即是具有銅導電柱的晶圓 級晶片尺寸封裝結構來說明本發明的實施例。然而，本 發明亦可應用於用以在封裝體與晶圓或晶片之間形成電 性連接的其他材料。 請參考第2圖，為一剖面圖，係顯示本發明一實施 例之晶圓級晶片尺寸封裝體20。導通墊202係形成於晶 片200中，作為與軟銲料球狀物201接觸與接合結構的 基礎。除了導通墊202之外，導電接腳203係形成於導 通墊202上，而對晶片200的表面輪廓發生改變。當軟 銲料球狀物201銲至晶片200上時，則沿著導通墊202 與導電接腳203的輪廓形成不規則形狀的銲點。介金屬 化合物形成層204係形成於上述銲點中，因此分散於整 個銲點中。因此開始於介金屬化合物形成層204某一端 點的一裂缝例如裂缝205,就無法如同位於現行方法所形 成的直線銲點中的裂缝一般得以順利擴展。此銲點的不 規則形狀會使晶片200與軟銲料球狀物201之間的銲點 的接合強度較高、且接合可靠度亦較高，並阻礙裂缝的 擴展並增加銲點的剪應力強度。此銲點的不規則形狀亦 增加晶片200與軟銲料球狀物201之間接點的表面積， 而亦改善接點的導電性。 第3A圖為一剖面圖，係顯示本發明一實施例之晶圓 級晶片尺寸封裝體30的形成方法中的起使步驟的一矽晶 圓300。經過製程係在矽晶圓300上形成一線路接點 0503-A33148TWF/dwwang 11 200847307 301、一保護層302、與一絕緣層303。一重分佈層 (re-distributed layer ; RDL)304 係提供自線路接點 301 至 矽晶圓300的表面的導電路徑。 應該注意的是絕緣層303可包含各種絕緣材料例如 聚酿亞胺（polyimide)或其他此類的聚合物絕緣體。本文對 第3圖的敘述不應將本發明的絕緣層限制為某些特定的 絕緣材料，事實上在另外及/或替換的實施例中，本發明 之晶圓級晶片尺寸封裝體30可以不具有一絕緣層例如絕 緣層303。 第3B圖為一剖面圖，係顯示本發明一實施例中，形 成一導電柱306與'接腳狀物3 0 7之後的梦晶圓。在弟 3B圖所示的形成晶圓級晶片尺寸封裝體30的製程中， 導電柱306係形成於聚合物絕緣層305中，而接腳狀物 307的形成則穿透光阻層308。接腳狀物307、導電柱 306、與重分佈層304的組合係將一導體提供至線路接點 301。 應該注意的是聚合物絕緣層3 0 5可包含各種的聚合 物絕緣材料例如環氧樹脂、聚驢亞胺、或其類似材料。 上述聚合物絕緣材料的選擇係使聚合物絕緣層305具有 特定的熱膨脹係數，而降低作用於晶圓上的有效應力。 應該再注意的是本發明各種實施例中所形成的接腳 狀物307及其他接腳狀物或凸塊的形成，可使用任何已 用於半導體製程的多道製程技術，包含材料沈積技術、 移除或蝕刻製程、與圖形化或微影製程。其中上述材料 0503-A33148TWF/dwwang 12 200847307 沈積技術例如為物理氣相沈積法（physical vapor deposition ; PVD)、化學氣相沈積法（chemical vapor deposition ; CVD)、電化學沈積法（electrochemical deposition ·，ECD)、分子束蟲晶（molecular beam epitaxy ; MBE)、原子層沉積技術（atomic layer deposition ; ALD)、 電鍍、或其他類似技術；而上述移除或蝕刻製程係包含 溼姓刻與乾截刻’例如為反應性離子鞋刻（reactive ion etch ; RIE)、或其他類似技術；而上述圖形化或微影製程 則使用正性光阻技術或負性光阻技術。 第3C圖為一剖面圖，係顯示本發明一實施例之具有 晶圓級晶片尺寸封裝體30的一矽晶圓300。將光阻層308 自晶圓級晶片尺寸封裝體30移除之後，接腳狀物307則 凸出於矽晶圓300的上表面，而保留聚合物絕緣層3〇5 以便將矽晶圓300連接至其終端裝置時，用以保護矽晶 圓 300。 第3D圖為一剖面圖，係顯示本發明一實施例之晶圓 級晶片尺寸封裝體30。晶圓級晶片尺寸封裝體3〇係經由 軟銲料球狀物309，將矽晶圓3〇〇連接至電路板31〇，而 津人#料球狀物309係銲在石夕晶圓3qq的導電柱3〇6上。 軟銲料球狀物309係形成於接腳狀物3〇7的周圍並將接 腳狀物307封入其中，並提供電路板31〇盥矽晶圓3〇〇 的線路接點之間的一電性連接，軟銲料球狀物3〇9 係使導電柱306、接腳狀物3G7、與接觸板3ΐι發生電性 接觸。藉由將軟録料球狀物3Q9形成於接腳狀物 307的 0503-A33148TWF/dwwang 13 200847307 周圍，係增加了將軟銲料球狀物309固定在矽晶圓300 的銲點的剪應力強度。另外，軟銲料球狀物309、導電柱 306、與接腳狀物307之間較大的表面接觸面積，亦改善 了其與矽晶圓300的電性接觸狀態。 應該注意的是前文對第3A〜3D圖所作敘述中的實施 例之晶圓級晶片尺寸封裝體，僅純粹是本發明之晶圓級 晶片尺寸封裝體中的一個實例，前文對第3A〜3D圖所作 敘述中所提及的特定結構與材料，不應用以限制本發明 的額外或替換性的應用。 第4圖為一剖面圖，係顯示本發明一實施例之晶圓 級晶片尺寸封裝體40。電極401係形成於晶片400中， 作為與軟銲料球狀物403接觸與接合結構的基礎。除了 電極401之外，導電接腳402係形成於電極401上，而 對晶片400的表面輪廓發生改變。當軟銲料球狀物403 銲至晶片400上時，則沿著電極401與導電接腳402的 輪廓形成不規則形狀的銲點。介金屬化合物形成層404 係形成於上述銲點中，因此分散於整個銲點中。因此開 始於介金屬化合物形成層404某一端點的一裂缝例如裂 缝405,就無法如同位於現行方法所形成的直線銲點中的 裂缝一般得以順利擴展。此銲點的不規則形狀會使晶片 400與軟銲料球狀物403之間的銲點的接合強度較高、且 接合可靠度亦較高，並阻礙裂缝的擴展並增加銲點的剪 應力強度。此銲點的不規則形狀亦增加晶片400與軟銲 料球狀物403之間接點的表面積，而亦改善接點的導電 0503-A33148TWF/dwwang 14 200847307 性。 2該注意的是第2與4 _顯示在本發明的各種實 =中’可能形成於導電柱或電極上的接腳狀物的數量 ^ ^而可能形成於導電柱或電極上的接腳狀物的數 :制=到將接腳狀物形成於導電柱或電極上的製程 =本身的限制’本發明的各種實施例不會限制 用的接腳狀物的數量。 之 士第5圖為一流程圖，係顯示實施本發明之一實 所執行的步驟的範例。在步驟巾，係使用 :脂酸亞胺、或類似物質，在一半導體晶圓的：： 上沈_貝-聚合物絕緣層。在㈣5〇1巾，係 =述半導體晶圓上、並於上述聚合物絕_ ^中上料電柱係與上述半導體晶圓的—線路層带 声的上二;^導Γ的一表面係可與上述聚合物：： :的上表面同南、或猶微凸出於其上表面。 :二：藉由沈積、侧、或微影的技術，形 2=述導電::一表面上，其中上述導 係凸出於上逑表面。在步驟5〇3中，係在每個 的上述表面上銲上—軟銲料球狀物，其中上述軟 狀物::將凸出於上述表面的上述導電接腳封入其中：’ 士弟6圖為一流程圖’係顯示實施本發明之 日守，所執行的步驟的範例。在步驟6〇"，係心：“ 分佈層而與一半導體晶圓的一線路層電性接觸？貝：重 咖中’係形成至少-導電柱於上述半導體晶圓上，= 050j-Aj j 148TWF/dwwang 15 200847307 由上述重分佈層使上述導電柱與上述半導體晶圓的上述 線路層電性連接。在步驟602中，係藉由沈積、蝕刻、 或微影的技術，形成一或多個導電接腳於上述導電柱的 一表面上，其中上述導電接腳係凸出於上述表面。在步 驟603中，係在每個導電接腳的上述表面上銲上一軟銲 料球狀物，其中上述軟鲜料球狀物係將凸出於上述表面 的上述導電接腳封入其中。 應該注意的是圖式及其相關敘述所示之本發明的各 種實施例中，係僅用單一的軟銲料球狀物及導電柱來說 明整個晶圓級晶片尺寸封裝體。在實際應用上，在實施 本發明之晶圓級晶片尺寸封裝體及其製造方法時，會使 用到排列成一個陣列之複數個導電柱與軟銲料球狀物， 而不應將本發明限制在只有一個軟銲料球狀物、導電 柱、與接腳狀物的組合之情況。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何本發明所屬技術領域中具有通常知 識者，在不脫離本發明之精神和範圍内，當可作些許之 更動與潤飾，因此本發明之保護範圍當視後附之申請專 利範圍所界定者為準。 0503-A33148TWF/dwwang 16 200847307 【圖式簡單說明】 係顯示一晶圓級晶片尺寸封裝 係顯示本發明一實施例之晶圓 第I圖為一剖面圖 體的單一軟銲料球狀物 第2圖為一剖面圖 級晶片尺寸封裝體。 第3A圖為一剖面圖， 級晶片尺寸封裝體的形成方法、丁纟明—貧施例之晶圓 圓。 去中的起使步驟的一矽晶 第3B圖為一剖面圖，倍 - 成一導’、”、、、不本盔明一實施例中，形 珉柱與一接腳狀物之後 . ^ 筮y日日圓0 弟C圖為一剖面圖，係顯 — 晶圓級晶ϋ θ + έϋΜ 本么明一貫施例之具有 人曰曰乃尺寸封裝結構的—矽晶圓。 第3D圖為一剖面圖，係顯 級晶片尺寸封裝結構。 本“―貫施例之晶圓 乐4圖為-剖面圖’係顯示本發 級晶片尺寸封裝結構。 4例之曰曰圓 弟5圖為一流程圖’係顯示實 時，所執行的步驟的範例。^本發明之-實施例 第6圖為一流程圖，係顯示實施本發明之一實施例 守所執行的步驟的範例。 、 【主要元件符號說明】 1〇、20、30、40〜晶圓級晶片尺寸封筆崎· 工〇〇、200、400〜晶片； ’ 〇503-A33l48TWF/dww； ang 17 200847307 101、201、309、403〜軟銲料球狀物； 102〜銅墊； 103、204、400〜介金屬化合物形成層； 104〜裂痕； 202〜導通墊； 203、402〜導電接腳； 205、405〜裂缝； 300〜碎晶圓， 301〜線路接點； 302〜保護層； 303〜絕緣層； 3 04〜重分佈層； 305〜聚合物絕緣層； 306〜導電柱； 307〜接腳狀物； 308〜光阻層； 310〜電路板； 311〜接觸板； 401〜電極； 500 、 501 、 502 、 503 、600、601、602、603〜步驟 0503-A33148TWF/dwwang 18

Claims (1)

  1. 200847307 、申請專利範圍： 1:-種半導體裴置的製造方法，包含: 形成至少一導命. · 上 層 並中兮道* (co ciive p〇st)於一半導體晶圓 八°a、甩柱係電性連接至該半導體晶圓的一線路 面上形ί:或多個導電接腳於上述至少-導電柱的-表 以及'、上述—或多個導電接腳係自該表面處凸起； 將一軟銲料球狀物銲至上述至 ί個ί::軟銲料球狀物係將凸出於該表面= 多個導電接腳封入其中。 、^ 方法2:7包1專利範圍第1項所述之半導體装置的製造 、…尤積—聚合物介電層於—晶圓表面上，其中至少一 V电柱係形成於該聚合物介電層中。 方述之半__造 中之一： v包柱的表面狀況係擇自下列其 與該聚合物介電層的上表面同高；以及 凸出於該聚合物介電層的上表面。 4·如申請專利範圍第2 方法，其中該聚合物介電層的材 置的製造 族群： 才钭係擇自下列所組成之 環氧樹脂；以及 0503-A33148TWF/dwwang 19 200847307 聚醯亞胺（polyimide)。 5. 如申請專利範圍第1項所述之半導體裝置的製造 方法，更包含： 沈積一重分佈層（re_distributed layer ; RDL)而與該線 路層電性接觸，其中上述至少一導電柱係與該重分佈層 電性接觸。 6. 如申請專利範圍第1項所述之半導體裝置的製造 方法，其中形成上述一或多個導電接腳的步驟包含下列 其中之一： 沈積一材料於上述至少一導電柱的該表面上； 從上述至少一導電柱的該表面上移除該材料的一部 分；以及 圖形化上述至少一導電柱的該表面。 7. —種半導體裝置，包含： 一基底； 一電路層於該基底中； 一線路層於該基底的一第一表面上，該線路層係電 性連接於該電路層； 一或多個電極凸出於該第一表面，上述一或多個電 極係電性連接至該線路層，並具有凸出於上述一或多個 電極的一上表面的一或多個接腳狀物；以及 一軟銲料球狀物連接於該上表面，並將上述一或多 個接腳狀物封入其中。 8. 如申請專利範圍第7項所述之半導體裝置，更包 0503-A33148TWF/dwwang 20 200847307 含·· 一聚合物介電層於該第一表面上，上述至少一電極 係位於該聚合物介電層中。 9. 如申請專利範圍第8項所述之半導體裝置，其中該 聚合物介電層的材料係擇自由下列所組成之族群： 環氧樹脂；以及 聚醯亞胺（polyimide)。 10. 如申請專利範圍第8項所述之半導體裝置，更包 含： 一重分佈層（re_distributed layer ; RDL)，其與該線路 層及上述至少一電極電性接觸。 11. 如申請專利範圍第10項所述之半導體裝置，其中 該線路層與上述至少一電極之間的一電性連接是由該重 分佈層獨自提供。 12. —種半導體裝置的製造方法，包含： 形成一線路層於一半導體晶片中； 沈積一聚合物絕緣層於該半導體晶片的一第一表面 上； 形成一或多個電極，其穿透該聚合物絕緣層，其中 上述一或多個電極係電性連接至該線路層； 形成至少一接腳狀物凸出於上述一或多個電極的一 上表面；以及 將一軟銲料球狀物銲至每一個上述一或多個電極之 上，該軟銲料球狀物係將上述至少一接腳狀物封入其中。 0503-A33148TWF/dwwang 21 200847307 、丨3·如申請專利範圍第12項所述之半導體裝置的製 造方法，更包含： ^移除該聚合物絕緣層的一部分，而使上述一或多個 電極的該上表面凸出於該聚合物絕緣層的上表面。 I4·如申请專利範圍第12項所述之半導體裝置的製 造方法，更包含： " ,沈積一導電層於該半導體晶片上，而與該線路層電 ^生接觸其中該導電層係提供上述一或多個電極盘該線 路層之間的電性連接。 W…亥線 、告方1:如申請專利範圍第12項所述之半導體裝置的製 :脹係數聚合物絕緣層的材料的選擇係根據其熱 16.—種半導體裝置，包含·· 一基底； 一或多個線路層於該基底的-第-表面中； 一聚合物絕緣層於該第一表取 具有一或多個導 忒來合物絕緣層 合物絕緣層而位於該第一夺 係牙透该聚 衣向之間，其令上述一或多 工 對應的上述-或多個線路層的其中之一…、 的一:::料球狀物連接於每-個上述-或多個導電柱 的上表面，並將凸出於上述— ^夕科电柱 面的一或多個導電接腳封入其中。一 ，电柱的該上表 17.如申請專利範圍第16項所述之半導體裝置，更包 0503-A33148TWF/dwwang 200847307 含： 部八上或夕個重分佈層層疊於該基底的該第-表面的— 多：重分物絕緣層下，其中每-個上述-或 的其中之—* $ k妾至與其對應的上述一或多個線路層 上述㈣第17項所述之半導體裝置，其中 或夕個重分配層係提供上述一 ，的上述-或多個線路層的其中之-之二二 中料職圍第16韻叙影何體裝置，盆 中一由下列所組成之族群;、 聚酿亞胺（polyimide)。 20·如申請專利範圍第19頂％、+、> , 中該聚合物絕緣層的材料的選擇導體裝置，其 性質。 的、擇係根據其熱膨脹係數的 0503-A33148TWF/dwwang 23
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