TW200843055A - Semiconductor device package to improve functions of heat sink and ground shield - Google Patents

Semiconductor device package to improve functions of heat sink and ground shield Download PDF

Info

Publication number
TW200843055A
TW200843055A TW096148523A TW96148523A TW200843055A TW 200843055 A TW200843055 A TW 200843055A TW 096148523 A TW096148523 A TW 096148523A TW 96148523 A TW96148523 A TW 96148523A TW 200843055 A TW200843055 A TW 200843055A
Authority
TW
Taiwan
Prior art keywords
substrate
heat dissipation
package structure
pad
semiconductor device
Prior art date
Application number
TW096148523A
Other languages
English (en)
Inventor
Wen-Kun Yang
Diann-Fang Lin
Original Assignee
Advanced Chip Eng Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Chip Eng Tech Inc filed Critical Advanced Chip Eng Tech Inc
Publication of TW200843055A publication Critical patent/TW200843055A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
    • H01L23/08—Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01059—Praseodymium [Pr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Description

200843055 九、發明說明： 【發明所屬之技術領域】 本發明係有關半導體封裝結構及其製造方法，特別係 關於薄型半導體封裝結構。 【先前技術】 於半導體裝置領域中，其裝置之密度不斷地增加；因 此，縮小裝置的尺寸需求也漸增。積體電路的發展係高度 地影響晶片封裝技術’因此當電子元件之尺寸視為趨勢 時乂封裝技術勢必也隨之起舞。基於上述理由，現今封裝 技術的趨勢係朝向球型閑陣列（bga)、覆晶技術 c BGA)、日日片級封裝（CSp)、晶圓級封裝（wLp);其中晶 圓級封裝具有極小的尺相及極優良的電性料優點。^ 用晶圓級封裝技術，可減少成本與製程時間，且完成的晶 圓級封裝結構之尺寸與晶粒大小相同；因此 足電子裝置微小化之需求。 了滿
雖然晶圓級封裝有上述之諸多優點，但存在某些 =了晶圓級封裝之接受度。例如，某些㈣技術需要晶 形成於基板上部表面上。再者，—般半導體晶粒之 過重佈程序重佈之，需要—重佈層至複數個區域陣 列形式的金屬墊。其增層亦增加縣之尺寸。因此，封夺 之厚度係增加。此將牴觸減少晶片尺寸的需求。晶片利用 :::層堆積，因此其結構的散熱與接地屏 要解決的問題。 而 【發明内容】 5 200843055 本發明之目的係提供一種封裝結構，具有較 積、較好的散熱以及接地屏蔽效能，以克服前述問題 =明的目的係提供一基板具有電路以及 枓的通孔，以連接配置於基板反面上的接墊。 本發明的目的係提供—薄型化的封裝結構，且本Μ 的^點係提供—具有高導熱能力的黏著材料。 " 再者，本發明的優點係提供一金屬層，以實 散熱能力；特別地，於高功率裝置，本發明提供 = 地賤用於射頻或高頻裝置。於較佳實施例中，本^明勺 括-作為天線功能的金屬層。本發明提供層疊封裝二 之叹计，利用簡單的製程，以整合裝置並縮小堆疊的 本發明係揭露-種用以改善散熱與接地 以封裝結構，包含：―基板，具有-第-接觸墊3 少具有-通孔（through h〇le)形成於其基板内。—金 Ο 形成於其基板下部表面處，其中其通孔自第—接觸塾祕 V::g)。：晶粒，具有一焊塾(b〇ndin”ad)藉由一具有 冋導…之黏著材料附著於其第一接觸墊上。一介電層，形 ί於其晶粒上。-第二接觸墊形成於其基板之上料面 ^。一重佈層（RDL)，形成於其晶粒上方並輕合其焊墊至 2接觸藝，用以電性連接。一錫球，形成於基板上部表 面上的第二接觸墊。 墓骑狀毛月亦提供Μ製造用以改善散熱與接地屏蔽之半 置封裝結構之方法，包含：提供-基板，其基板具 6 200843055 有第一接觸墊、一第二接觸墊以及至少一個通孔。散佈 #黏著材料於具有一焊墊之晶粒背面上。附著其晶粒於其 第接觸墊。形成增層（build up layer)以耦合其第二接觸 墊與其知墊。藉由塗佈（coating)或印刷（printing)方式形成 頁。卩保濩層於其晶粒與其基板上。置放一錫球於其第二接 觸墊上，以及回焊（refl〇wing)其錫球，藉以形成錫球於其 第二接觸墊上。 【實施方式】
本發明將配合其較佳實施例與隨附之圖示詳述於下。 應可理解者為I發明中所有之較佳實施例僅為例示之用， 並非用以限制。因此除文中之較佳實施例外，本發明亦可 廣泛地應用在其他實施例中。且本發明並不受限於任何實 施例，應以隨附之申請專利範圍及其同等領域而定。、 102。基板 1〇〇 最好由 FR5/FR4/BT(Bismaleimide ⑽ 或金屬/合金等材質所製成。通孔1〇2係填充導電材料，例 ^ ’金屬’最好為銅。一導電層，例如一金屬層1〇4，附 者於基板100之-表面上；以及一導電们06形成於基板 第圖根據本發明之較佳實施例，為本發明封裝結構 之截面圖。參照第一圖，基板100提供形成於其内的通孔 100之另一表面上。利用通孔102連接金屬層1〇4與1〇6, 以完成較佳的散熱目的，特別係用於高功率裝置。再者， 本發明之設計亦可提供高功率裝置極㈣接地屏蔽效能。 此外，其金屬層可作為天線功能。於本發明另—較佳實施 例，用以增進散熱能力的材料塗佈於金屬層104上。錫金 7 200843055 屬塾108形成於金屬層1〇6旁，兩者間具有一距離。上述 的封裝結構，自金屬層104至錫球端點，其厚度最好約為 300微米（Um)’其中锡球厚度約為0.33毫米（mm)。 具有接觸墊112的晶粒(晶片)110藉由黏著材料114 配置於孟屬層106上。黏著材料114係具有優良的導敎能 2 ’以利於消除由晶粒110所產生的熱能。晶粒110厚度 表好為20-75範圍微米間。 r 一感光介電層116形成於晶粒110與基板100之上表 面上。透過微影或曝光顯影製程，形成複數個開口於介電 =二：複數個開口係個別地對位至接觸墊(或輸出/輸 舌你：及於基板1〇0上部表面上的部份錫金屬墊 108。重佈層118,也可稱為導電路線118，藉由選擇性地 移除部份形成於介電層116上的金屬層，形成於介電層116 上。透過輸出/輸入塾112與錫金屬墊⑽， 晶粒110保持電性連接。 ^與 利用保護層uo覆蓋重佈層118，纟中保護層12〇之 材質包括聚亞醯胺樹脂化合物、矽膠。錫球 :錫::塾108上’用以導電。錫請之高度端:ί 徑，約為0.2-0.35毫米。 直 第二圖為本發明之另—較佳實施例。參照第二圖 H二圖的下部金屬層104分割為兩個主要部份，錫全屬 塾以與金屬層128外，第二圖之封裝結構係相似：屬 圖之貫施例。通孔13G形成於基板1GG内，並填充 料(例如金屬或合金)至通孔13〇内，以保持錫金屬塾= 8 200843055 與124間的電性連接。錫球132各別形成於對立於錫球 的錫金屬墊124上。此設計可提供堆疊結構。 第三圖根據本發明之實施例，為一堆疊封裝設計。參 照第二圖所示的封裝結構，藉由稍微修改前述第一圖與第 二圖的封裝結構，堆疊結構（基板）1〇〇。其封裝結構共用形 成於兩者間的錫球。與第二圖相似的結構（基板）3οος疊^ 結構1〇〇上。錫球302兩端係保持上下間電性連接。ς成 f 於結構300上的錫球304可耦合至其他元件，例如，記憶 體裝置。此結構即為層疊封裝結構。 第四圖為第一圖之封裝結構配置於一印刷電路板上之 截面圖。第一圖的封裝結構配置於印刷電路板402上，且 其印刷電路板402具有數個金屬墊4〇4形成於其上。錫球 4〇6(stage type)配置於金屬墊4〇2上，保持晶片（晶粒 與印刷電路板402間電性連接。印刷電路板4〇2頂部與對 立於曰曰粒408的金屬層41〇表面間之距離約微米。因 〇此，形成一覆晶結構於基板400與印刷電路板4〇2間。基 板.400的導電材料構成一用於晶片4〇8的電磁屏蔽（e= shielding) 〇 第五圖係為第三圖之封裝結構配置於一印刷電路板上 之截面圖。第三圖的封裝結構配置於印刷電路板5〇2上， 且其印刷電路板502具有數個金屬墊5〇4形成於其上。錫 球506(Stage type)配置於結構3〇〇上（如第三圖所示），而結 構300係δ又置於金屬墊5〇4，因此，具有顛倒架構㈣以心 down的層疊封裝結構係配置於印刷 電路板 9 200843055 可塗佈增進散熱能力 502上。於本發明另一較佳實施例， 的材料層於金屬層508上。 提供製造用以改善散熱與接地屏蔽之半導體 4置封1,、。構之方法。本發明提供一基板（面板型），具有 預先形成的電路與接觸墊以及通孔。其通孔填人導電材 料，用以保持晶片與金屬層間的電性連接。其金屬層係於 隨後的步驟’配置於基板的反面上。基板 為 肥舰鑛或金屬/合金。於本發明另—較佳實施例，= 有導電材料以及導電塾的另—通孔，其導電材料例如金 屬，填入其通孔。其導電塾，例如，金屬球塾，形成於基 板的通孔上，用以保持導電金屬墊間的電性連接。 隨後，一黏著材料（高導熱能力）配置於基板上，並使 =取放（pick and place)設備，使晶片附著於基板之具有黏 著材料的一側；其中晶片的厚度約2〇_75微米。 * -但晶粒重佈於基板上（面板基底），藉纟濕及/或乾清 洗’執行清洗程相清潔晶粒表面。另—步驟係塗佈介電 層材料於面板表面。隨後，執行微影製程以打通通孔（或引 洞（via h〇le))(接觸金屬塾）以及焊塾。執行電漿清洗步驟清 洗引洞與焊墊之表面。下一步驟係濺鍍鈦/銅作為晶種金屬 層，而後塗佈光阻於介電層與晶種金屬層以形成重佈層之 圖案。電鍍銅/銀或/銅/鎳/銀材料作為重佈層金屬，而後， 去除光阻並溼蝕刻以形成重佈層金屬路線。 而後，下一步驟係塗佈或印刷頂部介電層並打通接觸 金屬墊。可重複上述步驟以形成多個重佈層與介電層，例 200843055 如晶種（seed)層、光阻、電鑛或去除（stdp)/钱刻等等步驟。 錫球係置放於錫金屬接觸塾，隨後藉由回谭錫球使之 個別㈣㈣金屬接㈣。τ個步驟係切割⑽㈣攸）面板 从Γ成封$、Ια構。應可了解「金屬（metal)」可為任何導電 材質、金屬、合金或導電的化合物。於本發明另—較佳實 也例上述方法更包含堆叠另一封裝結構於其封裝結構 上，以形成層疊封裝結構（pop)。
人左♦ /、基板（封I形式）藉由表面黏著技術（SMT)結 ϋ心後’附著基板的錫球以連接印刷電路板之接塾，藉 ==覆晶結構於基板與印刷電路板之間；其中基板㈣ 電材料可構成用於晶粒的電磁屏蔽。 上^ ’、、、’^此領域技藝者，本發明雖以較佳實例闡明如 由然其並非用以限定本發明之精神。在不脫離 圍：所作之修改與類似的配置，均應包含在下述
口月斥’j軌圍内’此範圍應覆蓋所有類似修改 構，且應做最寬廣的詮釋。 【圖式簡單說明】 之戴【圖圖根據本發明之較佳實施例，為本發明封裝結構 裝結本發明之另—較佳實施例，為本發明之封 施例，為本發明堆疊封穿 第二圖根據本發明之較佳實 結構之載面圖。 之封裝結 第四圖根據本發明之較佳實施例，為第一圖 11 200843055 構配置於一印刷電路板上之截面圖。 第五圖根據本發明之較佳實施例，為第三圖之封裝結 構配置於一印刷電路板上之截面圖。 【主要元件符號說明】
100 基板 130 通孔 102 通孔 132 錫球 104 金屬層 300 基板 106 金屬層 302 錫球 108 錫金屬墊 304 錫球 110 晶粒 402 印刷電路板 112 接觸墊 404 金屬墊 114 黏著材料 406 錫球 116 介電層 408 晶粒 118 重佈層 410 金屬層 120 保護層 502 印刷電路板 122 錫球 504 金屬墊 124 錫金屬墊 506 錫球 128 金屬層 508 金屬層 12

Claims (1)

  1. 200843055 十、申請專利範圍： 1 · 一種用以改善散熱與接地屏蔽之半導體裝置封裝結 構，包含： 基板’具有一第一接觸墊與一通孔（thr0Ugh hole)形成 於該基板内； i屬層’形成於該基板下部表面處，並藉由該通孔輕 5至°亥弟一接觸墊’用以散熱（heat dissipation)與接地 屏蔽（ground shielding); f ； 一晶粒，具有一焊墊（b〇nding pa句，藉由一具有高導熱 之黏著材料附著於該第一接觸墊上； 一介電層，形成於該介電層與形成於該基板之上部表面 處之一第二接觸墊上； 一重佈層（RDL)，形成於該晶粒上方並耦合至該焊墊， 用以電性連接； 錫球，形成於该基板之該上部表面上的該第二接觸 c 墊。 2.如申請項1之用以改善散熱與接地屏蔽之半導體裝置 封裝結構，更包含一保護層，形成於該重佈層上。 士申《月項1之用以改善散熱與接地屏蔽之半導體穿置 封裝結構，其中所述之該金屬層的材質包括散熱材料。 4.如申1項1之用以改善散熱與接地屏蔽之半導體裂置 13 200843055 封裝結構，其中所述之該金屬層可作為天線。 5 ·如申請項1之用以改善散熱與接地屏蔽之半導體裝置 封裝結構，其中所述之第二接觸墊形成於該基板下部表 面上，堆疊另一半導體裝置封裝結構，藉以形成一層疊 封裝（package on package, P〇P)結構。 6·如申請項2之用以改善散熱與接地屏蔽之半導體裝置 〜 封裝結構，其中所述之保護層材質包括聚亞醯胺 (polyimide，PI)樹脂化合物、矽膠。 7·如申請項1之用以改善散熱與接地屏蔽之半導體裝置 封裝結構，其中所述之基板之材質包括 FR5/FR4/BT(Bismaleimide triazine)或金屬 /合金。 8· 一種製造用以改善散熱與接地屏蔽之半導體裝置封裴 結構之方法，包含： 提供一基板，該基板具有一第一接觸墊、一第二接觸墊 以及一通孔； 散佈一黏著材料於具有一焊墊之晶粒背面上； 附著該晶粒於該第一接觸墊； 形成增層（build up layer)以耦合該第二接觸墊與該焊 墊； 藉由塗佈（coating)或印刷（printing)方式形成頂部保護 14 200843055 層於該晶粒與該基板上； 置放一錫球於該第二接觸墊上；以及 回焊（reflowing)該錫球，藉以形成該錫球於該第二接觸 墊上。 9·如申明項8之製造用以改善散熱與接地屏蔽之半導體 裝置封裝結構之方法’更包含設置該晶粒與該基板，而 後附著該基板之該錫球至印刷電路板（PCB)的連接墊， 藉以形成一覆晶（flip_chip)結構，其中該基板的該第一 接觸墊構成一用於該晶粒的電磁屏蔽（EM shielding)。 10.如申請項8之製造用以改善散熱與接地屏蔽之半導體 裝置封裝結構之方法’更包含堆疊另—半導體封裝結構 於該半導體封裝結構，藉以形成一層疊封裝結構。 ".如申請項8之製造用以改善散熱與接地屏蔽之半 裝置封裝結構之方&，其中所述之基板 FR4/FR5/BT基板或金屬/合金基板。 12.如申請項8之製造用以改善散熱與接地屏蔽之 裝置封裝結構之方法，其中所述之保護層材質包括 醯胺樹脂化合物、矽膠。 A 13·如申請項8之製造用 以改善散熱與接地屏蔽之半導體 15 200843055 裝置封裝結構之方法，更包含塗佈一材料層，用以消除 由該晶粒所產生的熱能。
    16
TW096148523A 2007-04-17 2007-12-18 Semiconductor device package to improve functions of heat sink and ground shield TW200843055A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/736,461 US20080258293A1 (en) 2007-04-17 2007-04-17 Semiconductor device package to improve functions of heat sink and ground shield

Publications (1)

Publication Number Publication Date
TW200843055A true TW200843055A (en) 2008-11-01

Family

ID=39809828

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096148523A TW200843055A (en) 2007-04-17 2007-12-18 Semiconductor device package to improve functions of heat sink and ground shield

Country Status (7)

Country Link
US (1) US20080258293A1 (zh)
JP (1) JP2008270810A (zh)
KR (1) KR20080093909A (zh)
CN (1) CN101295683A (zh)
DE (1) DE102008019336A1 (zh)
SG (1) SG147390A1 (zh)
TW (1) TW200843055A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI453873B (zh) * 2012-03-27 2014-09-21 Chipsip Technology Co Ltd 堆疊式半導體封裝結構

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5091456B2 (ja) * 2006-10-31 2012-12-05 株式会社村上開明堂 ドアミラー
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
TWI453877B (zh) * 2008-11-07 2014-09-21 Advanced Semiconductor Eng 內埋晶片封裝的結構及製程
US7989950B2 (en) * 2008-08-14 2011-08-02 Stats Chippac Ltd. Integrated circuit packaging system having a cavity
US8106504B2 (en) * 2008-09-25 2012-01-31 King Dragon International Inc. Stacking package structure with chip embedded inside and die having through silicon via and method of the same
CN101777542B (zh) * 2009-01-14 2011-08-17 南茂科技股份有限公司 芯片封装构造以及封装方法
US8084858B2 (en) * 2009-04-15 2011-12-27 International Business Machines Corporation Metal wiring structures for uniform current density in C4 balls
US8693518B2 (en) * 2009-09-09 2014-04-08 Merkle International Inc. High temperature industrial furnace roof system
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8320134B2 (en) 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
CN102148221B (zh) * 2010-02-10 2013-04-24 精材科技股份有限公司 电子元件封装体及其制造方法
US8310050B2 (en) 2010-02-10 2012-11-13 Wei-Ming Chen Electronic device package and fabrication method thereof
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
CN101937885B (zh) * 2010-08-12 2013-03-20 日月光半导体制造股份有限公司 半导体封装件及其制造方法
KR101696644B1 (ko) * 2010-09-15 2017-01-16 삼성전자주식회사 3차원 수직 배선을 이용한 ｒｆ 적층 모듈 및 이의 배치 방법
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
CN102035061A (zh) * 2010-12-10 2011-04-27 广东通宇通讯股份有限公司 一种一体化设计的有源天线散热器
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
DE102011012186B4 (de) * 2011-02-23 2015-01-15 Texas Instruments Deutschland Gmbh Chipmodul und Verfahren zur Bereitstellung eines Chipmoduls
US8487426B2 (en) 2011-03-15 2013-07-16 Advanced Semiconductor Engineering, Inc. Semiconductor package with embedded die and manufacturing methods thereof
JP2013030593A (ja) * 2011-07-28 2013-02-07 J Devices:Kk 半導体装置、該半導体装置を垂直に積層した半導体モジュール構造及びその製造方法
TWI469294B (zh) * 2012-07-11 2015-01-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US9484313B2 (en) * 2013-02-27 2016-11-01 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal-enhanced conformal shielding and related methods
US9788466B2 (en) * 2013-04-16 2017-10-10 Skyworks Solutions, Inc. Apparatus and methods related to ground paths implemented with surface mount devices
CN104157627B (zh) * 2013-05-14 2019-11-08 飞兆半导体公司 半导体组件
KR101832796B1 (ko) * 2013-09-27 2018-02-27 인텔 코포레이션 패키징 빌드-업 아키텍처를 위한 자기장 차폐 장치, 모바일 디바이스 및 형성 방법
JP5975180B2 (ja) 2013-10-03 2016-08-23 富士電機株式会社 半導体モジュール
KR102341755B1 (ko) 2014-11-10 2021-12-23 삼성전자주식회사 반도체 패키지 및 그 제조방법
US20160358891A1 (en) * 2014-12-15 2016-12-08 Intel Corporation Opossum-die package-on-package apparatus
KR102265243B1 (ko) 2015-01-08 2021-06-17 삼성전자주식회사 반도체 패키지 및 그 제조 방법
CN205984953U (zh) * 2015-06-26 2017-02-22 Pep创新私人有限公司 半导体封装
US9781863B1 (en) 2015-09-04 2017-10-03 Microsemi Solutions (U.S.), Inc. Electronic module with cooling system for package-on-package devices
US10037897B2 (en) * 2016-11-29 2018-07-31 Taiwan Semiconductor Manufacturing Co., Ltd. Inter-fan-out wafer level packaging with coaxial TIV for 3D IC low-noise packaging
US10121766B2 (en) * 2016-06-30 2018-11-06 Micron Technology, Inc. Package-on-package semiconductor device assemblies including one or more windows and related methods and packages
EP3285294B1 (en) * 2016-08-17 2019-04-10 EM Microelectronic-Marin SA Integrated circuit die having a split solder pad
KR20180069636A (ko) 2016-12-15 2018-06-25 삼성전자주식회사 반도체 메모리 소자 및 이를 구비하는 칩 적층 패키지
US11264337B2 (en) 2017-03-14 2022-03-01 Mediatek Inc. Semiconductor package structure
US10784211B2 (en) * 2017-03-14 2020-09-22 Mediatek Inc. Semiconductor package structure
US11362044B2 (en) 2017-03-14 2022-06-14 Mediatek Inc. Semiconductor package structure
US11387176B2 (en) 2017-03-14 2022-07-12 Mediatek Inc. Semiconductor package structure
US11171113B2 (en) 2017-03-14 2021-11-09 Mediatek Inc. Semiconductor package structure having an annular frame with truncated corners
US10879220B2 (en) * 2018-06-15 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure and manufacturing method thereof
KR102589684B1 (ko) 2018-12-14 2023-10-17 삼성전자주식회사 반도체 패키지

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0874415B1 (en) * 1997-04-25 2006-08-23 Kyocera Corporation High-frequency package
US6288451B1 (en) * 1998-06-24 2001-09-11 Vanguard International Semiconductor Corporation Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength
US6043109A (en) * 1999-02-09 2000-03-28 United Microelectronics Corp. Method of fabricating wafer-level package
US6204562B1 (en) * 1999-02-11 2001-03-20 United Microelectronics Corp. Wafer-level chip scale package
US7247932B1 (en) * 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
JP2002026198A (ja) * 2000-07-04 2002-01-25 Nec Corp 半導体装置及びその製造方法
SG137651A1 (en) * 2003-03-14 2007-12-28 Micron Technology Inc Microelectronic devices and methods for packaging microelectronic devices
SG148877A1 (en) * 2003-07-22 2009-01-29 Micron Technology Inc Semiconductor substrates including input/output redistribution using wire bonds and anisotropically conductive film, methods of fabrication and assemblies including same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI453873B (zh) * 2012-03-27 2014-09-21 Chipsip Technology Co Ltd 堆疊式半導體封裝結構

Also Published As

Publication number Publication date
US20080258293A1 (en) 2008-10-23
KR20080093909A (ko) 2008-10-22
JP2008270810A (ja) 2008-11-06
CN101295683A (zh) 2008-10-29
SG147390A1 (en) 2008-11-28
DE102008019336A1 (de) 2008-11-06

Similar Documents

Publication Publication Date Title
TW200843055A (en) Semiconductor device package to improve functions of heat sink and ground shield
TWI552265B (zh) 形成孔穴於增進互連結構中以縮短晶粒之間訊號路徑之半導體裝置和方法
TWI502682B (zh) 半導體封裝及鑲嵌半導體晶粒至直通矽晶穿孔基板的對邊之方法
TWI499030B (zh) 在矽穿孔插入物中形成開放孔穴以包含在晶圓級晶片尺寸模組封裝的半導體晶粒之半導體裝置和方法
TWI499000B (zh) 形成雙主動邊之半導體晶粒於扇出晶圓程度晶粒級封裝之半導體裝置和方法
TWI508202B (zh) 雙重模造晶粒形成於增進互連結構之對邊上之半導體裝置和方法
TWI508226B (zh) 在基板的孔穴中鑲嵌具有直通矽晶穿孔的晶粒用以扇入封裝疊加的電互連之半導體裝置和方法
TWI705539B (zh) 半導體封裝方法、半導體封裝和堆疊半導體封裝
TWI479577B (zh) 形成屏障材料於晶粒之周圍以減少翹曲之半導體裝置和方法
TWI460844B (zh) 具有內嵌式晶片及矽導通孔晶粒之堆疊封裝結構及其製造方法
TWI379364B (en) Process of grounding heat spreader/stiffener to a flip chip package using solder and film adhesive
TWI649811B (zh) 用於應用處理器和記憶體整合的薄的三維扇出嵌入式晶圓級封裝
TWI352413B (en) Semiconductor device package with die receiving th
US7119432B2 (en) Method and apparatus for establishing improved thermal communication between a die and a heatspreader in a semiconductor package
TWI590347B (zh) 形成圍繞基板之晶粒附接區域之相鄰的通道及屏障材料之半導體裝置及方法以控制向外流之底部填充材料
TWI534974B (zh) 半導體裝置以及形成具有用於凸塊鎖定而被形成穿過抗蝕刻阻劑傳導層之凹處的基板之方法
TWI413231B (zh) 射頻模組封裝
US7696055B2 (en) Method for manufacturing passive device and semiconductor package using thin metal piece
US20150108635A1 (en) Semiconductor structure and manufacturing method thereof
CN107408547A (zh) 扇出型系统级封装件及其形成方法
KR102362426B1 (ko) 노출된 다이 후면을 갖는 플립 칩 패키지를 위한 emi 차폐
TW201104761A (en) Semiconductor device and method of forming shielding layer after encapsulation and grounded through interconnect structure
TW201104762A (en) Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die
JP2009170802A (ja) 半導体装置
TW201742208A (zh) 封裝結構、疊層封裝元件及其形成方法