TW200824080A - Semiconductor chip having bumps of different heights and semiconductor package including the same - Google Patents

Semiconductor chip having bumps of different heights and semiconductor package including the same Download PDF

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Publication number
TW200824080A
TW200824080A TW096131828A TW96131828A TW200824080A TW 200824080 A TW200824080 A TW 200824080A TW 096131828 A TW096131828 A TW 096131828A TW 96131828 A TW96131828 A TW 96131828A TW 200824080 A TW200824080 A TW 200824080A
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TW
Taiwan
Prior art keywords
wafer
bump
height
pads
lead
Prior art date
Application number
TW096131828A
Other languages
English (en)
Inventor
Ji-Hwan Hwang
Dong-Han Kim
Chul-Woo Kim
Sang-Heui Lee
Kwang-Jin Bae
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200824080A publication Critical patent/TW200824080A/zh

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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

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200824080 25460pif.doc 九、發明說明： 【發明所屬之技術領域】 本發明是有關於半導體晶片以及包含此晶片的半導體 封裝，特別是有關於適用藉由突塊而與電路板連接的半導 體晶片以及包含此晶片的半導體封裝。 【先前技術】
Ο 鼢著當前半導體晶片的尺寸越來越小，用於連接這些 + V脰日日片的成分焊塾（constituent bond pad)亦具有越來 越細的間距。這些細間距焊墊使這些半導體晶片與相關電 路板的連接變得更加困難。例如，在電路板上形成具有相 應細=距的印㈣路U案是較困㈣，且在後續組裝過程 中可忐造成錯位（misalignment)問題以及短路接觸。 圖1繪不習知與電路板1〇連接的半導體晶 面圖。圖2繪示圖1中半導俨曰H川、;匕立卜a 的千 干¥脰曰日片2〇冶剖囬線ΙΙ-ΙΓ的截 面視圖。圖3繪示與形成在電 0哉 12A對庵的半導體n二扳°上的印刷電路圖案 /愿的午日日片2Q的突塊22A的平面圖。 請一併參考圖1至圖3，雷政 體晶片20的晶片區域14。多數^ 3適於安裝半導 在晶片區域14的内緣部上 ％圖案12A形成 上形成的突塊似·體日^ 2G的焊㈣ 在焊墊24上的突塊22Α。突 f此1觸、、、口構具有形成 形成在電路板1GJL的印刷電路~ =焊墊24配置成與 線圖案）對應。 "木12Α(例如，例示的直 6 200824080 25460pif.doc % 一步繪示 、士、丨妒處^ 叫否作卿坪墊24之間的間矩 γ中巧的相鄰焊墊24之間的分開距離亦減 ，例如錯位及，或短路接觸的風險:； 允許形成在電路板10上的電路圖案12入 卜 如焊墊24)的分開距離進一步降低。〜^ (例 的示板1〇連接的半導體晶片2。 Ο ο 的截面視圖S'::::，:片2°沿剖面綠_ U 〇、、'曰不千V體晶片20的穸掄咖二 板1〇^上的印刷電路_12Β的平面圖。 輿電路 的間距較6二為使形成印刷電路圖案12Β 更安全的安裝在電路板1。上 連接更容易，:，2b與焊塾24之間的 在薄膜覆晶㈤二:二種
的細間距為2CW或以下的半導體:^T將突心B 【發明内容】 、日日片2〇連接至電路板。 更密集的連接圖ί°=:;=電路板之間形成 置突的連接元件(例如，焊墊及維方式配 以產生更达、集的連接配置。 三黾路圖案） 7 200824080 25460pif.doc 本發明的實施例亦提供包含有這種半導體晶片的半導 體封裝。 在一實施例中，本發明提供一種半導體晶片，包括多 數個焊墊，配置於半導體晶片上；以及不同高度的多數個 晶片突塊，配置在對應焊墊上。 在另一實施例中，本發明提供半導體封裝，包括多數 個晶片突塊，連接至半導體晶片上的對應焊墊，其中，所 述多數個晶片突塊包括具有第一高度的第一晶片突塊及具 有第二高度的第二晶片突塊，所述第二高度大於所述第一 高度；以及電路板，包括多數個第一内部引線及多數個第 二内部引線，每一第一内部引線包括具有第一高度的第一 引線突塊，每一第二内部引線包括具有第二高度的第二引 線突塊，所述第二高度小於所述第一高度；其中，所述半 導體與所述電路板的電連接是藉由第一晶片突塊與第一引 線突塊以及弟《 —晶片突塊與弟·一引線突塊的各自組合來達 成。 【實施方式】 以下將參照相關圖示，詳細説明本發明之實施例。然 而，本發明可以其它形式實施，而不應解釋成限制於本文 介紹的實施例。在本文中，相同的元件將以相同的參照符 號加以説明。
圖7繪示適用於使用習知COF技術安裝一個或多個半 導體晶片的薄膜10’的平面圖。圖7中的薄膜10·是處於待 接收半導體晶片的狀態。所繪示的薄膜10·是採用習知COF 8 200824080 25460pif.doc 封衣的形式，由聚亞醯胺（p〇lyimide)或其它具有優異熱 ，脹係數或極佳敎性的類似材料製成。然而，本發明的、 靶圍亚不限制於C〇F封裝，而是可以更廣泛地應用於各種 半導體封裝。薄膜1G，上設有晶片安裝區域14 •，用於接收 一個或多個半導體晶片。印刷電路圖案12C延伸進（或至） ，片安裝區域14·，作為内部引線（innerlead)，且可以高 密度地形成在晶片安裝區域14周圍。 ^
一在本發明的一實施例中，薄膜10,内設置一狹縫30， 以讓形成薄膜1〇,的聚亞醯胺材料充分彎曲或彎折。 ϋ圖7所示，印刷電路圖案12C從晶片安裝區域14, 延=出並用作外部引線（outer lead) 16。外部引線16可 在第區域A1被防銲油墨（sower resist)覆蓋，此防銲 油墨防止印刷電路圖案12C在後續處理中受損或電性^ 路上4 纟°的元件（例如，晶片安裝區域14,、印刷電路 圖案12C的内部引線及外部引線，等）可藉由沿線八2切 口J而自々、亞胺基板移除。通常只有當單個C〇f封裳完成 封裝級電性測試之後才進行這種切割製程。 凡 •圖8繪示半導體晶片以C0F封裝或覆晶封裝方式（flip chip package)焊接至電路板的截面視圖。 如圖8所示，習知焊墊202A、202B及202C成三列 形成在半導體晶片200上。在所示的實施例中，高度不同 的晶片突塊204A、204B及204C分別形成在焊墊^2a、 202B 及 2〇2C 上。 — 在所示的範例中，與第一列焊墊202A連接的第一晶 200824080 25460pif.doc 片突塊204A具有為零的第一高度。與第二列焊墊2〇2B連 接的第二晶片突塊204B具有大於零的第二高度。與第三 列焊墊202C連接的第三晶片突塊2〇4C具有大於第二高度 白勺第三高度。在焊墊列向設置的環境下，這種晶片突塊具 ，不同高度的設置允許半導體晶片2〇〇與電路板1〇2以三
、、隹I式连接’即使是在電路板上形成的内部引線的間距極 小的情況下。 、在所不的實施例中，晶片突塊2〇4A、204B及204C， 對應的焊墊202A、202B及202C在每一連接列具有 二同的南度。然而，也不需要總是這樣設置，在一些實施 Μ中，個別列向高度也可以變化。 在本發明一實施例中，晶片突塊204α、2〇4Β及204C 由金（Au)製成。 Η刷笔路圖案10仏、1〇牝及1〇4C被連接的内部引 刀以父錯偏移的方式呈現在連接區域。即…系列第 H利線（印刷電路_ 1Q4A)藉由對應的具有第〆高 ^的弟—引線突塊祕終止於第—列焊墊繼…系列 伸=部ϋί (印刷電路圖案iq4b)以橫向偏移的方式延 的tm1線1Q4A的終止點，且藉由具有第二高度 終止於第二列焊墊難…系列第 ϊϊ 電路圖案1G4C)以橫向偏移的方式延伸 引線1Q4B的終止點，且的
'三=r6C終止於第三列焊塾：C 圖所不的範例中，電路板1〇2可為樹脂（例如咖 10 200824080 25460pif.doc 或ΒΤ)形成的硬式基板，或由聚亞酿胺形成的軟式基板。 分別形成在第—印刷電路圖案1G4A、第二印刷雷路圖案 104Β及第三印刷電路圖案1〇化的引線突塊祕、麵 及106C與分別形成在半導體晶片的焊墊搬A、2_ 及202C上的晶片突塊2〇4A、2_及2〇4c 齡組合高度（咖binedheight)的連接，其中2高^ 值疋義為半導體晶片9〇〇的相盤本 。又 Ο Ο 間分開的距離。一 4表面人印刷電路板102之 晶片突塊與高度變化的引線突塊之 z平面及Y平面的内邻弓丨妗，六网八〜野應是接k件 集内部引線及其伴隨作為x平面密 ==8及_示的實施例，ζ乎面是= 、、版曰日片20〇至印刷電路板102垂直，丫平面是朝 向圖9的内部引線的向上延伸方向，以及X平面是橫向穿 4圊及圖9。#然，这種幾何描述術語完全是任意選擇 :間=:Γ:區分所選擇的f個平面的用於連换的内部引 接允許半物W可被有效及可靠地^至間距^ 20μπι或更小的内部引線。 … 圖9的乂錯偏移的設置在圖1〇的平面圖中進一步給 示。 、曰 a w ί 9及圖1〇，與半導體晶片200相關聯的各列焊蝥 回木 、104B及104C)的連接更容易。在圖10所 200824080 25460pif.doc 不的範例中，第-列谭墊2〇2A及第三列焊塾2〇2c設置成 在行向上氧應。與之相反的是，中間的第二列焊塾 的行，置相對於此方位偏移。需要進一步說明的是，所緣 不的範例僅繪示出印刷電路圖案以及對應的與半導體200 . &表面的連接。孰悉本領域的技術人士當認制，本發明 • 的=、准内邛引線間隔及連接設置可以應用於具有上下兩面 的連接以及具有朝向安裝的半導體晶片側邊端部的另外内 〇 部引線的連接的半導體晶片。 炉,圖7緣不的半導體封裝10〇可使用COF、捲帶載具封 晶片及/或引線突塊來實現三維内部引線 特別Him發明實施例的截面視圖’其特徵在於設置 欲止面對應的引線突塊臓1及晶片突塊細1 〇 合。在此，、此非平面設計成以使兩突塊更加可靠地配 部引结Γ如ί至焊墊202的晶片突塊204B1及連接至内 ^ Γ , 1電路圖案104)的引線突塊106B1的穸 度可各自變化。 旧大塊呵 對應突塊的配合規則）突塊結構有利於 龄示的v开^使存在小的錯位的情況下。除了圖η 例如，w形、Υ 構外，也可採用其它不規則結構， ^凹/凸形、塊狀等。 面視ί I2及圖1场示根據本發明實施例的其它範例的截 12 200824080 25460pif.doc 如圖12，配合 曰 沿自各自連接务"線及晶片突塊106Β2及204Β2形成 shape )。另外，如^伸的方向上變窄的角形（angular 及204B3形成沿自'13所示’配合引線及晶片突塊l〇6B3 在以上摇自連接面延伸的方向上㈣的角形。 似導電性材料製戍靶例中，印刷電路圖案104可由銅或類 形成在印刷電 Ο ο 以及106B3可由金制_案1〇4上的弓丨線突塊1〇沾卜106B2 電路圖案104及^製成’且有一中間鎳層108形成於印刷 雖然本發明P線突塊1〇6Bl、1〇6B2以及臓3之間。 限定本發明:任何=佳實_揭露如上、然其並非用以 和範圍内，當可^習此技，者，在不脫離本發明之精神 範圍當視後附之申二许之更動與潤飾，因此本發明之保護 【圖式簡單說明】轉觀_界定者為準。 圖1繪示習知歲泰 圖2繪示習^鱼^板連接的半導體晶片的平面圖。 圖。 路板連接料導體晶片的截面視 圖3繪示習知半I雕曰 圖案的平面圖。 “版日日及電路板的突塊及印刷電路 圖4繪示其它習知 路板連接的半導體晶片的平面 圖5繪示其它習知 。 、如反’半導體晶片的戴面 圖6繪示其它習知 肢晶片及電路板的突塊及印刷 fSl Λ — .» 圖 視圖 13 200824080 25460pif.doc 電路圖案的平面圖。 圖7繪示使用於習知COF封裝的薄膜的平面圖。 圖8繪示根據本發明實施例的半導體晶片以COF封裝 或覆晶封裝方式焊接至電路板的截面視圖。 圖9、纟會不根據本發明貫施例的半導體晶片及電路板的 突塊的位置的平面圖。 圖10繪示根據本發明實施例的與電路板連接的半導 體晶片的平面圖。 圖11繪示根據本發明另一實施例的半導體晶片的突 塊的範例的截面視圖。 圖12及圖13繪示根據本發明實施例的半導體晶片的 突塊的範例的截面視圖。 【主要元件符號說明】 10 :電路板 10’ ：薄膜 12 A :印刷電路圖案 12B :印刷電路圖案 12C ·印刷電路圖案 14 ·晶片區域 14’ ：晶片安裝區域 16 :外部引線 20 :半導體晶片 22A :突塊 22B :突塊 14 200824080 25460pif.doc 24 焊墊 30 狹缝 40 半導體封裝 60 半導體封裝 100 ··半導體封裝 102 :電路板 104A :印刷電路圖案 104B :印刷電路圖案 104C :印刷電路圖案 106A :引線突塊 106B :引線突塊 106B1 :引線突塊 106B2 :引線突塊 106B3 :引線突塊 106C :引線突塊 108 :中間鎳層 200 :半導體晶片 202 :焊墊 202A :焊墊 202B :焊墊 202C :焊墊 204A :晶片突塊 204B :晶片突塊 204B1 :晶片突塊 15 200824080 25460pif.doc 204B2 :晶片突塊 204B3 :晶片突塊 204C :晶片突塊 A1 :第一區域 A2 ··線 P1 :間距
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Claims (1)

  1. 200824080 25460pif.doc 十、申請專利範圍： 1 1. 一種半導體晶片，包括： 多數個焊墊，配置於半導體晶片上；以及 不同高度的多數個晶片突塊，配置在對應的所述焊墊 上。 2. 如申請專利範圍第1項所述之半導體晶片，其中所 述焊墊在所述半導體晶片上設置成多數列。 0 3.如申請專利範圍第2項所述之半導體晶片’其中每 一所述晶片突塊的各自高度根據對應列的所述焊墊而變 化c 4. 如申請專利範圍第3項所述之半導體晶片，其中相 鄰的焊墊列偏移設置。 5. 如申請專利範圍第4項所述之半導體晶片，其中所 述焊墊列設置成Z字形，且連接至一系列以交錯偏移的方 式設置的内部引線。 6. 如申請專利範圍第1項所述之半導體晶片，其中所 D 述焊墊在所述半導體晶片上呈第一列、第二列及第三列設 置；以及 所述晶片突塊包括： 第一晶片突塊，具有第一高度，且分別連接至第一列 焊墊的其中一個所述焊墊； 第二晶片突塊，具有第二高度，所述第二高度大於所 述第一高度，所述第二晶片突塊分別連接至第二列焊墊的 其中一個所述焊墊；以及 200824080 25460pif.doc 第三晶片突塊’具有第三高度，所述第三高度大於所 述第二高度，所述第三晶片突塊分別連接至第三列焊塾的 其中一個所述焊墊。 7.如申請專利範圍第6項所述之半導體晶片，其中所 述第一晶片突塊的所述第一高度為零。 8·如申請專利範圍第6項所述之半導體晶片，更包括 接收一系列内部引線的晶片安裝區域； 〇 其中，所述第一焊墊列、所述第二焊墊列及所述第三 焊墊列以相鄰列偏移的方式設置，以鄰近所述晶片安裝區 域的邊緣設置的所述弟一焊墊列為起始列，所述第二焊執 列設置於所述第一焊墊列後面且更加遠離所述晶片安裝區 域的所述邊緣，且所述第三焊墊列設置於所述第二焊墊列 後面且更加遠離所述晶片安裝區域的所述邊緣。 9·如申請專利範圍第6項所述之半導體晶片，其中至 少所述第二晶片突塊及所述第三晶片突塊分別終止於不規 . 則形狀的端部。 10. —種半導體封裝，包括： 多數個晶片突塊，連接至半導體晶片上的對應的焊 墊，其中，所述晶片突塊包括具有第一高度的第一晶片突 塊及具有第二高度的第二晶片突塊，所述第二高度大於所 述第一高度；以及 電路板，包括多數個第一内部引線及多數個第二内部 引線，每—戶斤述弟一内部引線包括具有第一高度的第一引 線大塊，每〆戶斤述弟—内部引線包括具有弟一南度的第二 J8 200824080 25460pif.doc 引線突塊，所述第二高度小於所述第一高度； 其中，所述半導體晶片與所述電路板的電連接是藉由 所述第一晶片突塊與所述第一引線突塊以及第所述二晶片 突塊與所述第二引線突塊的各自組合來達成。 11. 如申請專利範圍第10項所述之半導體封裝，其中 所述半導體封裝是從薄膜覆晶封裝及捲帶載具封裝構成的 族群中選擇。 12. 如申請專利範圍第10項所述之半導體封裝，其中 所述半導體封裝是覆晶封裝。 13. 如申請專利範圍第10項所述之半導體封裝，其中 所述半導體晶片的所述焊墊設置成多數列。 14. 如申請專利範圍第13項所述之半導體封裝，其 中，每一所述第一晶片突塊分別連接至第一列的所述焊墊 中的其中一個焊墊，且每一所述第二晶片突塊分別連接至 第二列的所述焊墊中的其中一個焊墊。 15. 如申請專利範圍第10項所述之半導體封裝，其中 每一引線突塊以成角的方式自内部引線延伸且終止於端 部，所述引線突塊的端部寬於連接至所述内部引線的部 位，且每一晶片突塊以成角的方式自所述焊墊延伸且終止 於端部，所述晶片突塊的端部寬於連接至所述焊墊的部位。 16. 如申請專利範圍第10項所述之半導體封裝，其中 每一引線突塊以成角的方式自内部引線延伸且終止於端 部，所述引線突塊的端部窄於連接至所述内部引線的部 位，且每一晶片突塊以成角的方式自所述焊墊延伸且終止 19
    200824080 25460pif.doc 於端部，所逑晶片突塊的端部窄於連接至 17.如申請專利範園帛]〇 :員所述斤迷谭墊的部位。 每-引線突塊包括錄層，所述鎳層形成=體封裝，其中 弓丨線及形成於所述鎳層上的金層之間。、由鋼製成的内部 18·如申請專利範圍第1〇工員戶斤述之 所述半導體晶片的所述焊墊設置成=蛉體封裝，其中 列； ^、第二列及第三 所述晶片突塊更包括具有第三高度 一 所述第三高度大於所述第二高度，且所诚^二晶片突塊， 數個第三内部引線，每—所述第 =電路板更包括多 第二高度的第三高度； 線具有小於所述 戶斤^¥脸與所述電路板的電性連接額外地藉由所试 第m塊與所述第三引線突塊的各自垣合來達成。〜 沙如々申請專利範圍第項所述之半導體封裝，其中 每-所述弟-引線突塊㈣應的所述第U突塊連接， 所述第，晶片突塊與第-列的所述焊塾中的其中一;;焊塾 相關聯； 每’述第二引線突塊與對應的所述第二晶片突塊連 接，所述第二晶片突塊與第二列的所述焊墊中的其中—個 垾墊相關聯；以及 每，所述第三引線突塊與對應的所述第三晶片突塊連 接，戶斤述第三晶片突塊與第三列的所述焊墊中的其中—個 焊塾相_耳外 20，如申請專利範圍第19項所述之半導艘封裝，其中 20 200824080 25460pif.doc 至少每一所述第二晶片突塊及所述第三晶片突塊以及每一 所述第一引線突塊及所述第二引線突塊終止於不規則的端 部。
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