201244040 六、發明說明： 【發明所屬之技術領域】 • 本發明係關於一種可撓性基板及半導體裝置者。 【先前技術】 圖7係從斜上方觀看先前之COF(薄膜覆晶：Chip Film)型半導體裝置之概略圖。 上述半導體裝置具備：可撓性基板701，及搭載於該可 撓性基板701之半導體晶片704。 上述半導體晶片704對可撓性基板701覆晶連接》而且， 在上述半導體晶片704與可撓性基板701之間，通常充填有 樹脂。 圖8係從上方觀看日本特開2001_237265號公報所揭示之 可撓性基板801之要部概略圖。 上述可撓性基板801具備基材8〇〇,其係在一表面具有半 導體晶片搭載區域803者。 在上述半導體晶片搭載區域8〇3，搭載有未圖示之半導 體晶片。更詳細而言，上述半導體晶片之凸起電極以未圖 不之ACF(各向異性導電膜：Anis〇tr〇pic c〇nductive 為中介，藉由熱壓接而連接於内引線8〇6。 上述内引線806從抗銲層812之開口 813露出，並進入半 導體晶片搭載區域8〇3内。 在上述半導體晶片搭載區域803，形成有引導在ACF加 熱/1接時產生之氣泡的導槽8丨4。上述氣泡由導槽814所引 導，從排出口 815向半導體晶片搭載區域8〇3外排出。 164650.doc 201244040 由於上述氣泡其内部會滯留水分及雜質而成為產生故障 之原因，故必須向半導體晶片搭載區域8〇3外排出氣泡。 圖9係從上方觀看日本特開2〇〇4·6462號公報揭示之可撓 性基板901之要部概略圖β 上述可撓性基板901具備形成於半導體晶片搭載區域9〇3 之跨接線911。 在上述半導體晶片搭載區域9〇3，以黏著樹脂為中介搭 載有未圆示之LSI(大規模積體電路）等晶片零件。 上述ea片零件以黏著樹脂為中介加熱壓接於半導體晶片 搭載區域903。此時，由於在上述半導體晶片搭載區域9〇3 形成有跨接線911，因此黏著樹脂之流動性變得良好。 上述跨接線911包含：直線形狀之主幹佈線部921，接線 於該主幹佈線部921 —端之直線形狀之支佈線部922，及接 線於該主幹佈線部921另一端之直線形狀之支佈線部923。 上述主幹佈線部921，係以沿著晶片零件之長方形狀之 下面之長邊方向、即圖9中之左右方向延伸之方式形成。 上述支佈線部922、923延伸之方向，設定為相對於主幹 佈線921之延伸方向成角α。而且，上述支佈線部922、923 從主幹佈線部92 1延伸而接線於内引線906。此處，上述角 α為135±15。。 上述内引線906從抗輝層912的開口 913露出，並進入半 導體晶片搭載區域903内❶在該内引線906上連接晶片零件 之凸起電極。 如上述之可撓性基板901 ’係藉由跨接線911而使黏著樹 164650.doc ⑧ 201244040 月曰之*IL動性良好，以防止在可撓性基板1與晶片零件之 間滯留氣泡。 但，上述可撓性基板8〇1、901各自存在如下之問題。 上述可撓性基板801，其導槽8 14彼此之間隔，較半導體 曰曰片搭載區域803之令央部，其在周緣部較為狭窄。換言 之，用於以上述導槽8M引導上述氣泡之空間雖寬，但用 於將氣泡排出至半導體晶片搭載區域8〇3外之出口即排出 口 81 5卻狹窄。 因此，上述可撓性基板8〇1具有不能將氣泡從排 出口 815 順暢排出之問題。 另方面，上述可撓性基板901中，在跨接線911上未形 成如可撓性基板801之排出口 8丨5之開口。 而且’由於上述晶片零件之凸起電極與内引線9〇6連接 之連接部因為間距狹窄而顯得密集，故要將氣泡從該連接 部彼此之間排出至半導體晶片搭載區域9〇3之外，實質上 係困難的。 因此，由於上述氣泡被圍困在半導體晶片搭載區域9〇3 内，因此具有不能將氣泡排出至半導體晶片搭載區域903 外之問題。 亦即’上述可撓性基板8G1、则兩者均具有將氣泡從半 導體晶片搭載區域内向半導體晶片搭載區域外之排出效果 低的問題。 乂 【發明内容】 [發明所欲解決之問題] 164650.doc 201244040 因此’本發明之目的在於提供—種可撓性基板及具備該 ，可撓性基板之半導體裝置，上述可撓性基㈣可提高氣泡 從半導體晶片搭載區域内向半導體晶片搭載區域外之 效果者》 [解決問題之技術手段] 為解決上述_，本發明之可撓性基板，其特徵在於且 備： …、 基材，其係在一表面具有半導體晶片搭載區域者； 複數之内引線，其係形成於上述基材之上述一表面上 者；及 佈線，其係接線於上述内引線，橫穿上述半導體晶片搭 載區域者。 根據上述構成之可撓性基板，因為上述佈線橫穿半導體 晶片搭载區域，故可藉由佈線順暢地引導半導體晶片搭載 區域内的氣泡至半導體晶片搭載區域外。 因此，可提高氣泡從上述半導體晶片搭載區域内向半導 體晶片搭載區域外之排出效果。 又，因為上述佈線橫穿半導體晶片搭載區域，故在半導 體晶片搭載區域内不會形成迴路。 因此，藉由上述佈線可防止氣泡被圍困在半導體晶片搭 載區域内。 而且’因為上述佈線接線於内引線，故可使佈線具有該 内引線之電位。 在一貫施形態之可撓性基板中，接線於上述佈線之上述 164650.doc ⑧ 201244040 内引線之線寬，與未接線於上述佈線之上述内引線之線寬 不同。 根據上述實施形態之可撓性基板，在使接線於上述佈線 之上述内引線之線寬，比未接線於上述佈線之上述内引線 之線寬為寬時，對於該佈線，例如即使連接半導體晶片電 極中處理最大電流之電極，亦可防止在佈線施加電流時之 燒損。 因此，可確保具備上述可撓性基板與半導體晶片之半導 體裝置之可靠性。 在-實施形態之可撓性基板中’具備形成於上述基材之 上述一表面上之圖案保護膜；且 就上述佈線之上述半導體晶片搭載區域外之部分中，有 至少一部分未被上述圖案保護膜覆蓋因而露出。 根據上述實施形態之可撓性基板，例如在上述佈線連接 半導體晶片之電極時，因為就上述佈線之上述半導體晶片 搭載區域外之部分中，有至少一部分未被上述圆案保：膜 覆盍因而露出，故能夠以該至少一部分為甲介放出半導體 晶片的熱，防止因熱而產生之半導體晶片之故障。 在*-實施形態之可撓性基板中’上述佈線係厚度為㈣ μηα範圍内且線寬為6〜3〇〇 μιη範圍内之金屬箔。 本發明之半導體裝置，其特徵在於具備： 本發明之可撓性基板；及 搭載於上述可撓性基板之上述半導體晶片搭载區域之 禮版b α t 署 164650.doc 201244040 根據上述構成之半導體裝置，因為其具備上述可撓性基 板’故可防止因氣泡而產生之半導體晶片故障，提高其可 靠性。 更詳細而言’在上述可撓性基板與半導體晶片之間例如 充填樹脂之情料’因為可撓性基板之佈線橫穿半導體晶 片搭載區域，故藉由該佈線可將半導體晶片搭載區域内之 樹脂順暢地引導至半導體晶片搭載區域外。 因此’可防止故障起因之氣泡殘留在上述可撓性基板與 半導體晶片之間，提高其可靠性。 此外，因為亦可不需使用用於防止上述氣泡殘留之特別 材料或裝置，故可防止半導體裝置製造成本增加。 在一實施形態之半導體裝置中， 在上述半導體晶片之上述可撓性基板側之表面形成有複 數之凸起電極； 上述半導體晶片之上述可撓性基板侧之表面為長方形 狀； 上述凸起電極形成於上述半導體晶片之上述可撓性基板 側之表面之短邊附近以外之部分。 根據上述貫施形態之半導體裝置，因為上述凸起電極係 形成於半導體晶片之可撓性基板側之表面之短邊附近以外 之部分，故可從半導體晶片之可撓性基板側之表面之短邊 附近排出氣泡。 而且，藉由在上述半導體晶片之可撓性基板側之表面之 長邊附近形成凸起電極’可增加凸起電極之個數。 164650.doc 201244040 在一實施形態之半導體裝置中， 在上述半導體晶片之上述可撓性基板側之表面形成有複 數之凸起電極； 連接於上述佈線之上述凸起電極之電位為接地電位。 根據上述實施形態之半導體裝置，因為連接於上述佈線 之凸起電極之電位為接地電位，故可使其電性特性穩定， 且可得到提高品質的效果。 在一實施形態之半導體裝置中， 在上述半導體晶片之上述可撓性基板側之表面形成有複 數之凸起電極； 上述佈線所連接之上述凸起電極，其處理之電流係上述 半導體晶片向外部輸出之電流。 根據上述實施形態之半導體裝置，因為連接於上述佈線 之凸起電極所處理之電流係半導體晶片向外部輸出之電 流，故能夠以接線於上述佈線之内引線為中介而取出上述 電流。 [發明之效果] 根據本發明之可撓性基板，因為藉由佈線橫穿半導體晶 片搭載區域’可順暢地引導+導體晶片搭載區$内的氣泡 至半導體晶片搭載區域外，故可提高氣泡從上述半導體晶 片搭載區域内向半導體晶片搭載區域外之排出效果。 根據本發明之半導體裝置，因為其具備上述之可撓性基 板，故可防止因氣泡而產生之半導體晶片故障，提高其可 靠性。 冋八 164650.doc 201244040 【實施方式】 (第一實施形態） 圖1係從上方觀看本發明第一實施形態之可撓性基板ι〇ι 之要部概略圖》 上述可撓性基板101，如圖1、圖2所示’其具備：基材 1〇〇，其係在一表面具有以平面觀視呈長方形狀之半導體 晶片搭載區域103者；複數之内引線106，其係形成於上述 一表面上者：及跨接線i i i，其係接線於上述複數之内引 線106中之2條者。而上述跨接線1丨丨係佈線之一例。 上述基材1 00係由例如厚度40 μηι之聚醯亞胺薄膜構成。 上述跨接線111包含第1佈線部丨21、第2佈線部〖22、第3 佈線部123、第4佈線部124及第5佈線部125。 上述第1佈線部12 1沿半導體晶片搭載區域1 〇3之長邊延 伸而橫穿半導體晶片搭載區域1 〇3。即上述第1佈線部 121，係跨及半導體晶片搭載區域1〇3及半導體晶片搭載區 域103外之區域而形成者。 上述第2佈線部122沿半導體晶片搭載區域ι〇3之短邊延 伸。且上述第2佈線部122之一端連接在第1佈線部121之一 端。 上述第3佈線部123沿半導體晶片搭載區域ι〇3之短邊延 伸。且上述第3佈線部123之一端連接在第1佈線部121之另 一端。 上述第4佈線部124沿半導體晶片搭載區域1 〇3之長邊、 相對於第1佈線部121成平行延伸。而且，上述第4佈線部 164650.doc -10- 201244040 124亦與第1佈線部121同樣，係跨及半導體晶片搭載區域 103及半導體晶片搭載區域1〇3外之區域而形成者。且上述 第4佈線部124之一端連接在第2佈線部122之另一端。另一 方面，上述第4佈線部124之另一端接線於内引線1〇6之頂 端。該内引線106之線寬與第4佈線部124之線寬大致相 同。 上述第5佈線部125沿半導體晶片搭載區域103之長邊、 相對於第1佈線部121成平行延伸。而且，上述第5佈線部 125亦與第1佈線部121同樣’係跨及半導體晶片搭載區域 103及半導體晶片搭載區域1〇3外之區域而形成者。且上述 第5佈線部125之一端連接在第3佈線部123之另一端。另— 方面，上述第5佈線部125之另一端接線於内引線1〇6之頂 端。該内引線106之線寬與第5佈線部125之線寬大致相 同。 又，上述第1佈線部121、第2佈線部122、第3佈線部 123、第4佈線部124及第5佈線部125之線寬，均為大致相 同。 此外’連接於上述第4、第5佈線部124、125另一端之内 引線106 ’形成為比其他内引線ι〇6長。 而且’上述第1佈線部12 1與第4佈線部124間之距離，與 第1佈線部121與第5佈線部125間之距離大致相同。 此外’就上述跨接線111之半導體晶片搭載區域1〇3外之 部分中’有一部分未被抗銲層U2覆蓋因而露出。更詳細 而言’在上述半導體晶片搭載區域1〇3外，其中第1佈線部 164650.doc 201244040 121之一部分、第4佈線部124之一部分、及第5佈線部125 之一部分未被抗銲層112覆蓋因而露出。而上述抗銲層112 係圖案保護膜之一例。 此外’上述第1佈線部121之兩端部，第2、第3佈線部 122、123之全部，及第4、第5佈線部124、125之一端部由 抗録層11 2所覆蓋。藉此可提高上述跨接線111之可靠性。 上述内引線106形成為位於抗銲層112之開口 113内。而 且，上述内引線106之形成間距、即内引線間距p，係配合 後述之凸起電極105之形成間距而設定為5〇 μιη。又，上述 内引線106彼此之間隔、即内引線間隙〇為25 μπι。又，上 述内引線106之線寬W亦為25 μιη。 上述所謂内引線間隙G與内引線1 〇6之線寬w，係考慮以 下風險之平衡來設定者，即：蝕刻殘餘、及因蝕刻殘餘而 引起之遷移等致使内引線丨〇6彼此接近之風險，與因内引 線106之圓案殘缺、及電流容量降低等導致細線化而引起 之風險之平衡。 圖2係從斜上方觀看本發明第丨實施形態之半導體裝置概 略圖。再者，圖3係圖2之半導體晶片搭載區域1〇3之放大 圖。此外，圖3令，為易於理解，將樹脂丨1〇作為透明物進 行圖示。 上述半導體裝置，如圖2、及圖3所示，具備：可換性基 板101 ;半導體晶片1()4 ’其係以覆晶連接而連接於上述可 繞ί生基板1G1 搭載於半導體晶片搭載區域⑻者；及樹 脂110，其係覆蓋抗銲層112之開口 113者。 164650.doc ⑧ •12- 201244040 在上述半導體晶片104之下面（可燒性基板1〇1側之表面） $成有複數之凸起電極105。更詳細而言，上述半導體晶 104之下面呈長方形狀’沿此下面之長邊形成有複數之 凸起電極105。藉此’可使後述佈線1〇2之各圖案呈直線形 狀而簡單化。 在上述複數之凸起電極105中，半導體晶片1〇4下面之一 側長邊附近之凸起電極1〇5係輸出側電極，而半導體晶片 下面另側長邊附近之凸起電極105係輸入側電極。 又，在半導體晶片104下面之短邊附近未形成有凸起電極 105 ° 在上述可撓性基板1〇1之一構成部之基材1〇〇之一表面 (半導體晶片104側之表面）形成有佈線1〇2，並以覆蓋該佈 線102大部分之方式形成有抗銲層112。 上述佈線102由厚度為8 μηι之銅箔形成。而且上述佈 ，’泉102之半導體晶片搭載區域丨〇3侧之端部形成為内引線 106。亦即，上述内引線1〇6係佈線1〇2之一部分。 上述樹脂11〇存在於半導體晶片104之周圍。該樹脂11〇 之一部分進入可撓性基板1〇1與半導體晶片1〇4之間隙s。 由於在上述半導體晶片1〇4下面之長邊附近，有凸起電 極105與内引線1〇6在直線上密集排列，故該等實質上如牆 壁般形成封閉可撓性基板1〇1與半導體晶片1〇4之間隙§之 狀態。 另方面，在上述半導體晶片1 04下面之短邊附近則沒 有凸起電極105，跨接線1U之第丨佈線部121沿半導體晶片 164650.doc •13· 201244040 104下面之長邊延伸而橫穿半導體晶片搭載區域1〇3，並從 半導體晶片搭載區域103内朝向半導體晶片搭載區域1〇3外 突出。 如此’藉由在上述半導體晶片1 〇4下面之短邊附近不形 成凸起電極1 05，及使跨接線111之第1佈線部12丨沿半導體 晶片104下面之長邊延伸而橫穿半導體晶片搭載區域1〇3， 可將可撓性基板101與半導體晶片104之間隙S之氣泡，從 半導體晶片104下面之短邊附近排出至半導體晶片搭載區 域103之外。 因此，上述可撓性基板101從半導體晶片搭載區域103内 向半導體晶片搭載區域103外之氣泡排出效果高。 而且，因為上述跨接線ill在半導體晶片搭載區域1〇3内 未形成迴路’故可防止氣泡被圍困在半導體晶片搭載區域 103 内》 在上述第1實施形態中，第2佈線部122形成為位於抗銲 層112之開口 113外之位置，但亦可形成為位於抗銲層112 之開口 113内之位置。即，上述第2佈線部122亦可不用以 抗銲層112覆蓋。 第3佈線部123形成為位於抗銲 但亦可形成為位於抗銲層U2 上述第3佈線部123亦可不用以 在上述第1實施形態中 層112之開口 113外之位置 之開口 113内之位置。即 抗辉層112覆蓋。 在上述第1實施形態中，内引線106之線寬冒為25 ^爪， 但亦可為除此以外之線寬。又，上述内引線1〇6之厚度 164650.doc ]4 201244040 為8 pm ’但亦可為除此外 ^ L ^ W <厚度。亦即’在上述第1實 施形態中’亦可使用由厚产 予度在1〜50 μηι範圍内、線寬在 6〜300叩範圍内之金屬箱所形成之内引線。 在上述第1實施形態中，亦可使用具有比上述内引線1〇6 之線寬為窄的線寬之跨接線。 在上述第1實施形態中，既可使上述跨接線ui中流通電 流，亦可使上述跨接線U1中不流通電流。 (第2實施形態） 圖4係從上方觀看本發明第2實施形態之半導體裝置之要 部概略圖…在圖4中’與^所示的^實施形態之構 成部相同之構成部，均附上與圖丨之構成部相同之參照號 碼而省略其說明。又，在圖4中省略上述半導體裝置具備 之半導體晶片204之圖示。 上述半導體裝置具備：可撓性基板2〇1;及半導體晶片 104，其係以覆晶連接而連接於上述可撓性基板2〇1，且搭 載於半導體晶片搭載區域1〇3者。 上述可撓性基板201具備跨接線211，其係包含第丨佈線 部221、第2佈線部222、第3佈線部223、第4佈線部224及 第5佈線部225者。又，上述跨接線211為佈線之一例。 上述第1佈線部221沿半導體晶片搭載區域ι〇3之長邊延 伸而橫穿半導體晶片搭載區域1 03。即，上述第1佈線部 221 ’係跨及半導體晶片搭載區域1〇3，及半導體晶片搭載 區域103外之區域而形成者。 上述第2佈線部222沿半導體晶片搭載區域103之短邊延 164650.doc 15 201244040 伸。且上述第2佈線部222之一端連接在第1佈線部221之一 端。 上述第3佈線部223沿半導體晶片搭載區域1 〇3之短邊延 伸。且上述第3佈線部223之一端連接在第}佈線部221之另 一端。 上述第4佈線部224沿半導體晶片搭載區域1〇3之長邊、 相對於第1佈線部221成平行延伸。而且，上述第4佈線部 224亦與第1佈線部221同樣’係跨及從半導體晶片搭載區 域103至半導體晶片搭載區域1〇3外之區域而形成者。且上 述第4佈線部224之一端連接在第2佈線部222之另一端。另 一方面，上述第4佈線部224之另一端接線於内引線206之 頂端。該内引線206之線寬與第4佈線部224之線寬大致相 同，且比内引線106之線寬為寬。 上述第5佈線部225沿半導體晶片搭載區域1〇3之長邊、 相對於第1佈線部2 21成平行延伸。而且，上述第5佈線部 225亦與第1佈線部221同樣，係跨及半導體晶片搭載區域 103及半導體晶片搭載區域1〇3外之區域而形成者》且上述 第5佈線部225之一端連接在第3佈線部223之另一端。另一 方面，上述第5佈線部225之另一端接線於内引線206之頂 端。該内引線206之線寬與第5佈線部225之線寬大致相 同，且比内引線106之線寬為寬。 又，上述第1佈線部22 1、第2佈線部222、第3佈線部 223、第4佈線部224及第5佈線部225之線寬，均為大致相 同。 I64650.doc -16- ⑧ 201244040 此外’連接於上述第4、第5佈線部224、225另一端之内 引線20ό ’形成為比其他内引線ι〇6長。 而且，上述第1佈線部221與第4佈線部224間之距離，與 第1佈線部22 1與第5佈線部225間之距離大致相同。 此外，就上述跨接線211之半導體晶片搭載區域1〇3外之 部分中’有一部分未被抗銲層i 12覆蓋因而露出。更詳細 而5，在上述半導體晶片搭載區域1〇3外，其中第1佈線部 221之一部分、第4佈線部224之一部分、及第5佈線部225 之一部分未被抗辉層112覆蓋因而露出。此外，上述第1佈 線部221之兩端部’第2、第3佈線部222、223之全部，及 第4、第5佈線部224、225之一端部由抗銲層U2所覆蓋。 藉此，可提高上述跨接線211之可靠性。而上述抗銲層112 係圖案保護膜之一例。 此外’在上述第1佈線部221及内引線206連接凸起電極 205。 圖5係從圖4之V-V線觀看之概略剖面圖。 在上述半導體晶片204之下面（可撓性基板2〇1側之表面） 形成有凸起電極105、205。且，上述半導體晶片2〇4之下 面呈長方形狀。 在上述第1佈線部221連接之凸起電極205，其形成在半 導體晶片104下面稍微偏離其長邊之處。 在上述内引線206連接之凸起電極205，其形成在半導體 晶片104下面之長邊附近。 上述半導體晶片2 0 4係向未圖示之列印頭供給電壓之列 164650.doc -17- 201244040 印驅動n ’在向上㈣印頭供給電壓時產生之電流會流通 於内引線206及跨接線211。因此，上述内引線2〇6及跨接 線2H為避免因上述電流而燒損，故必須設計為充分降低 電阻之佈線尺寸。具體而言，上述内引線2〇6及跨接線2丄工 用厚度為8 μπι且線寬為40 μιη之銅箔形成。由於該内引線 206及跨接線2U之截面積為32〇 μιη2,故可充分防止内引 線206及跨接線2 11因電流而燒損。 本發明者藉由實驗發現：在對於半導體晶片2〇4實際處 理電流為0.2 Α之具有邊限之設計上，考慮使用1〇倍之電流 2 A之佈線線寬時’佈線之截面積需要3〇〇 gm2。 因此，若現狀之可撓性基板之佈線形成限度即厚度為 1 μπι ’則佈線線寬需要300 μη^反之，若將佈線加厚則可 減小佈線線寬，作為使用於先前之TCP(捲帶式晶片載體封 裝：Tape Carrier Package)等之佈線，若採用厚度為5〇 μηι 之銅箔則可將佈線線寬減小為6 μπι。 此外，在上述可撓性基板201中，亦與可撓性基板1〇1同 樣，可將可撓性基板201與半導體晶片204之間之氣泡從半 導體晶片204下面之短邊附近排出至半導體晶片搭載區域 10 3之外。 因此，上述可撓性基板201從半導體晶片搭載區域1〇3内 向半導體晶片搭載區域103外之氣泡排出效果高。 在上述第2實施形態中’第2佈線部222形成為位於抗銲 層11 2之開口 113外之位置’但亦可形成為位於抗鲜層1 j 2 之開口 113内之位置。即，上述第2佈線部222亦可不用以 I64650.doc . jg. ⑧ 201244040 抗銲層112覆蓋。 在上述第2實施形態中，第3佈線部223形成為位於抗銲 層112之開口 113外之位置，但亦可形成為位於抗銲層112 之開口 113内之位置。即，上述第3佈線部223亦可不用以 抗銲層112覆蓋。 在上述第2實施形態中，半導體裝置亦可具備覆蓋抗銲 層112之開口 113之樹脂。 (第3實施形態） 圖6係從上方觀看本發明第3實施形態之半導體裝置之要 部概略圖。又，在圖6中’與圖丨所示第1實施形態之構成 部相同之構成部，均附上與圖i之構成部相同之參照號碼 而省略其說明。又，在圖6中省略上述半導體裝置具備之 半導體晶片之圖示。 上述半導體裝置係在跨接線i 1丨之第1佈線部12 1連接凸 起電極305，此點與第1實施形態不同。 上述半導體晶片係液晶驅動器。而且，在上述半導體晶 片之下面（可撓性基板1〇1側之表面）形成有凸起電極、 3〇5。且，上述半導體晶片之下面呈長方形狀。 十上述凸起電極3〇5，其形成在半導體晶片1〇4下面稍微偏 離長邊之處。再者，上述凸起電極305之電位為接地電位。 對於近年來由於輸入信號串列化而使動作頻率增高之液 晶驅動晶片而言，高頻電路的設計要素為不可或缺，為使 接地電位穩定化，應將接地電位之電極配置於所需之位 置。因此，將上述凸起電極305形成於半導體晶片之下 I64650.doc -19- 201244040 面’並將其連接在跨接線111之第1佈線部121。 如此，藉由將上述凸起電極305形成於半導體晶片之下 面’並將其連接在跨接線111之第1佈線部121，可提高半 導體裝置之電性功能。 【圖式簡單說明】 圖1係本發明第1實施形態之可撓性基板之要部概略平面 圖。 圖2係本發明第丨實施形態之半導體裝置之概略立體圖。 圖3係圖2之半導體晶片搭載區域之放大圖。 圖4係本發明第2實施形態之半導體裝置之要部概略平面 圖。 圖5係圖4之V-V線之向視剖面圖。 圖6係本發明第3實施形態之半導體裝置之要部概略平面 圖。 圖7係先前之COF型半導體裝置之概略立體圖。 圖8係先前之可棱性基板之要部概略平面圖。 圖9係其他的先前之可撓性基板之要部概略平面圖。 【主要元件符號說明】 100 基材 101、201 可撓性基板 102 佈線 103 半導體晶片搭載區域 105、 205、305 凸起電極 106、 206 内引線 •20- 164650.doc ⑧ 201244040 111、 211 跨接線 112 抗鲜層 121、 221 第1佈線部 122 ' 222 第2佈線部 123、 223 第3佈線部 124、 224 第4佈線部 125、 225 第5佈線部 164650.doc -21 -201244040 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a flexible substrate and a semiconductor device. [Prior Art] Fig. 7 is a schematic view of a conventional COF (Chip Film) type semiconductor device viewed obliquely from above. The semiconductor device includes a flexible substrate 701 and a semiconductor wafer 704 mounted on the flexible substrate 701. The semiconductor wafer 704 is flip-chip bonded to the flexible substrate 701. Further, a resin is usually filled between the semiconductor wafer 704 and the flexible substrate 701. Fig. 8 is a schematic view of a main part of a flexible substrate 801 disclosed in Japanese Laid-Open Patent Publication No. 2001-237265. The flexible substrate 801 is provided with a substrate 8A having a semiconductor wafer mounting region 803 on one surface. A semiconductor wafer (not shown) is mounted on the semiconductor wafer mounting region 8〇3. More specifically, the bump electrode of the semiconductor wafer is connected to the inner leads 8〇6 by thermocompression bonding using an ACF (anisotropic conductive film: Anis〇tr〇pic c〇nductive) which is not shown. The inner lead 806 is exposed from the opening 813 of the solder resist layer 812 and enters the semiconductor wafer mounting region 8〇3. The semiconductor wafer mounting region 803 is formed with a guide groove 8 for guiding air bubbles generated during ACF heating/one connection. The bubble is guided by the guide groove 814, and is discharged from the discharge port 815 to the outside of the semiconductor wafer mounting region 8〇3. 164650.doc 201244040 Since the bubble is trapped inside the inside of the bubble and causes impurities, it is necessary to cause a malfunction. The bubble is discharged to the outside of the semiconductor wafer mounting region 8A. Fig. 9 is a schematic view of the main portion of the flexible substrate 901 disclosed in Japanese Laid-Open Patent Publication No. Hei. In the semiconductor wafer mounting region 9〇3, a wafer component such as an LSI (large-scale integrated circuit) that is not circularly displayed is mounted on the semiconductor wafer mounting region 9〇3. The ea sheet member is heated and pressure-bonded to the semiconductor wafer mounting region 903 by the adhesive resin. At this time, since the jumper 911 is formed in the semiconductor wafer mounting region 9〇3, the fluidity of the adhesive resin is improved. The wiring 911 includes a linear trunk portion 921, a linear wiring portion 922 that is connected to the end of the trunk wiring portion 921, and a linear wiring portion 923 that is connected to the other end of the trunk wiring portion 921. The trunk wiring portion 921 is formed to extend in the longitudinal direction of the lower surface of the rectangular shape of the wafer component, that is, in the horizontal direction in Fig. 9. The direction in which the branch wiring portions 922 and 923 extend is set to be relative to the trunk wiring. The extending direction of the 921 is at an angle α. Further, the branch wiring portions 922 and 923 extend from the trunk wiring portion 92 1 and are connected to the inner lead 906. Here, the above-mentioned angle α is 135±15. The opening 913 of the layer 912 is exposed and enters the semiconductor wafer mounting region 903, and the bump electrode of the wafer component is connected to the inner lead 906. The flexible base as described above 901 ' is made of a jumper 911 to make the adhesive tree 164650.doc 8 201244040 *IL good to prevent air bubbles from remaining between the flexible substrate 1 and the wafer component. However, the flexible substrate 8 described above Each of the first and second 901 has the following problems: The flexible substrate 801 has a gap between the guide grooves 8 and 14 and is narrower than the central portion of the semiconductor chip mounting region 803. In other words, it is used for narrowing at the peripheral portion. Although the space for guiding the bubble by the above-described guide groove 8M is wide, the discharge port 81 5 for discharging the bubble to the outside of the semiconductor wafer mounting region 8〇3 is narrow. Therefore, the above flexible substrate 8〇1 has a problem that air bubbles cannot be smoothly discharged from the discharge port 815. On the other hand, in the above flexible substrate 901, an opening such as the discharge port 8丨5 of the flexible substrate 801 is not formed on the jumper 911. Further, since the connection portion between the bump electrode of the wafer component and the inner lead 9〇6 is dense due to the narrow pitch, air bubbles are discharged from the connection portion to the outside of the semiconductor wafer mounting region 9〇3. Essentially difficult. Therefore, since the air bubbles are trapped in the semiconductor wafer mounting region 9A3, there is a problem that the air bubbles cannot be discharged outside the semiconductor wafer mounting region 903. In other words, the flexible substrate 8G1 has a problem that the discharge effect of the bubbles from the inside of the semiconductor wafer mounting region to the outside of the semiconductor wafer mounting region is low.发明 [Summary of the Invention] [Problems to be Solved by the Invention] 164650.doc 201244040 Therefore, an object of the present invention is to provide a flexible substrate and a semiconductor device including the same, wherein the flexible base (4) is In order to solve the above-mentioned problem, the flexible substrate of the present invention is characterized in that: The semiconductor wafer mounting region is provided on one surface; the plurality of inner leads are formed on the one surface of the substrate; and the wiring is connected to the inner lead and traverses the semiconductor wafer mounting region. According to the flexible substrate having the above configuration, since the wiring traverses the semiconductor wafer mounting region, the air bubbles in the semiconductor wafer mounting region can be smoothly guided to the outside of the semiconductor wafer mounting region by the wiring. Therefore, the discharge effect of the bubbles from the inside of the semiconductor wafer mounting region to the outside of the semiconductor wafer mounting region can be improved. Further, since the wiring traverses the semiconductor wafer mounting region, no loop is formed in the semiconductor wafer mounting region. Therefore, the above-mentioned wiring can prevent the air bubbles from being trapped in the semiconductor wafer mounting region. Further, since the above wiring is wired to the inner lead, the wiring can have the potential of the inner lead. In the flexible substrate of the conventional configuration, the line width of the lead wire in the above-mentioned wiring of the above-mentioned wiring 164650.doc 8 201244040 is different from the line width of the inner lead which is not wired to the above wiring. According to the flexible substrate of the above embodiment, when the line width of the inner lead wired to the wiring is wider than the line width of the inner lead not wired to the wiring, for example, even if the semiconductor wafer is connected to the wiring The electrode that processes the maximum current in the electrode also prevents burnout when current is applied to the wiring. Therefore, the reliability of the semiconductor device including the above flexible substrate and semiconductor wafer can be ensured. In the flexible substrate of the embodiment, 'the pattern protection film formed on the one surface of the substrate is provided; and at least a part of the portion of the wiring outside the semiconductor wafer mounting region is not protected by the pattern The film cover is thus exposed. According to the flexible substrate of the above-described embodiment, for example, when the electrode of the semiconductor wafer is connected to the wiring, at least a part of the portion other than the semiconductor wafer mounting region of the wiring is not covered by the wafer: Since it is exposed, the heat of the semiconductor wafer can be released by the at least one portion, and the failure of the semiconductor wafer due to heat can be prevented. In the flexible substrate of the embodiment, the metal foil having a thickness of (4) μηα and a line width of 6 to 3 μm is used. A semiconductor device according to the present invention includes: a flexible substrate of the present invention; and a lithographic plate mounted on the semiconductor wafer mounting region of the flexible substrate. 164650.doc 201244040 A semiconductor device having the above configuration Since the above-mentioned flexible substrate is provided, it is possible to prevent semiconductor wafer failure due to air bubbles and improve reliability. More specifically, 'there is, for example, a resin filled between the flexible substrate and the semiconductor wafer.' Since the wiring of the flexible substrate traverses the semiconductor wafer mounting region, the wiring can be used in the semiconductor wafer mounting region. The resin is smoothly guided to the outside of the semiconductor wafer mounting region. Therefore, the bubble which prevents the cause of the failure remains between the flexible substrate and the semiconductor wafer, and the reliability thereof is improved. Further, since it is not necessary to use a special material or device for preventing the above-mentioned bubble remaining, it is possible to prevent an increase in the manufacturing cost of the semiconductor device. In the semiconductor device of the embodiment, a plurality of bump electrodes are formed on a surface of the semiconductor wafer on the side of the flexible substrate; a surface of the semiconductor wafer on the side of the flexible substrate is a rectangular shape; and the bump electrode A portion other than the short side of the surface of the semiconductor wafer on the side of the flexible substrate. According to the semiconductor device of the above-described embodiment, since the bump electrode is formed in a portion other than the short side of the surface of the semiconductor wafer on the flexible substrate side, the surface of the semiconductor wafer from the flexible substrate side can be short. Air bubbles are emitted near the sides. Further, the number of the bump electrodes can be increased by forming the bump electrodes ' near the long sides of the surface of the flexible substrate side of the semiconductor wafer. In a semiconductor device according to one embodiment, a plurality of bump electrodes are formed on a surface of the semiconductor wafer on the side of the flexible substrate; and a potential of the bump electrode connected to the wiring is a ground potential. According to the semiconductor device of the above-described embodiment, since the potential of the bump electrode connected to the wiring is at the ground potential, the electrical characteristics can be stabilized, and the effect of improving the quality can be obtained. In the semiconductor device of the embodiment, a plurality of bump electrodes are formed on a surface of the semiconductor wafer on the side of the flexible substrate; and the current of the bump electrode connected to the wiring is processed to be external to the semiconductor wafer Output current. According to the semiconductor device of the above-described embodiment, since the current of the current-based semiconductor wafer to be processed by the bump electrode connected to the wiring is externally outputted, the current can be taken out by interposing the wiring inside the wiring. [Effects of the Invention] According to the flexible substrate of the present invention, since the air bubbles in the +-conductor wafer mounting region $ can be smoothly guided to the outside of the semiconductor wafer mounting region by the wiring crossing the semiconductor wafer mounting region ', the bubble can be improved. The discharge effect in the semiconductor wafer mounting region to the outside of the semiconductor wafer mounting region. According to the semiconductor device of the present invention, since the above-described flexible substrate is provided, it is possible to prevent semiconductor wafer failure due to air bubbles and improve reliability. [Embodiment] (First Embodiment) Fig. 1 is a schematic view of a portion of a flexible substrate 1 according to a first embodiment of the present invention viewed from above. 1 and 2, the substrate 1 is provided with a semiconductor wafer mounting region 103 having a rectangular shape in plan view on one surface, and a plurality of inner leads 106 formed in the above-mentioned one. On the surface: and the jumper iii, which is wired to two of the above-mentioned plurality of leads 106. An example of the above-mentioned jumper wiring is one. The above substrate 100 is composed of, for example, a polyimide film having a thickness of 40 μm. The jumper wire 111 includes a first wiring portion 21, a second wiring portion 22, a third wiring portion 123, a fourth wiring portion 124, and a fifth wiring portion 125. The first wiring portion 12 1 extends along the long side of the semiconductor wafer mounting region 1 〇 3 and traverses the semiconductor wafer mounting region 1 〇 3 . In other words, the first wiring portion 121 is formed to extend over the semiconductor wafer mounting region 1A and the region outside the semiconductor wafer mounting region 103. The second wiring portion 122 extends along the short side of the semiconductor wafer mounting region ι3. One end of the second wiring portion 122 is connected to one end of the first wiring portion 121. The third wiring portion 123 extends along the short side of the semiconductor wafer mounting region ι3. One end of the third wiring portion 123 is connected to the other end of the first wiring portion 121. The fourth wiring portion 124 extends in parallel with respect to the first wiring portion 121 along the long side of the semiconductor wafer mounting region 1 〇3. Further, similarly to the first wiring portion 121, the fourth wiring portion 164650.doc -10- 201244040 124 is formed to extend over the semiconductor wafer mounting region 103 and the semiconductor wafer mounting region 1A3. One end of the fourth wiring portion 124 is connected to the other end of the second wiring portion 122. On the other hand, the other end of the fourth wiring portion 124 is connected to the top end of the inner lead 1?6. The line width of the inner lead 106 is substantially the same as the line width of the fourth wiring portion 124. The fifth wiring portion 125 extends in parallel with respect to the first wiring portion 121 along the long side of the semiconductor wafer mounting region 103. Further, the fifth wiring portion 125 is formed in the same manner as the first wiring portion 121, and is formed in a region other than the semiconductor wafer mounting region 103 and the semiconductor wafer mounting region 1A3. One end of the fifth wiring portion 125 is connected to the other end of the third wiring portion 123. On the other hand, the other end of the fifth wiring portion 125 is connected to the top end of the inner lead 1?6. The line width of the inner lead 106 is substantially the same as the line width of the fifth wiring portion 125. Further, the line widths of the first wiring portion 121, the second wiring portion 122, the third wiring portion 123, the fourth wiring portion 124, and the fifth wiring portion 125 are substantially the same. Further, the inner leads 106' connected to the other ends of the fourth and fifth wiring portions 124, 125 are formed to be longer than the other inner leads ι6. Further, the distance between the first wiring portion 12 1 and the fourth wiring portion 124 is substantially the same as the distance between the first wiring portion 121 and the fifth wiring portion 125. Further, a part of the portion other than the semiconductor wafer mounting region 1?3 of the jumper 111 is not covered by the solder resist layer U2 and is exposed. More specifically, in the semiconductor wafer mounting region 1A, a portion of the first wiring portion 164650.doc 201244040 121, a portion of the fourth wiring portion 124, and a portion of the fifth wiring portion 125 are not provided with the solder resist layer. 112 coverage is thus exposed. The solder resist layer 112 is an example of a pattern protective film. Further, at both end portions of the first wiring portion 121, all of the second and third wiring portions 122 and 123 and one end portion of the fourth and fifth wiring portions 124 and 125 are covered by the resist layer 11 2 . Thereby, the reliability of the above jumper 111 can be improved. The inner lead 106 is formed to be located in the opening 113 of the solder resist layer 112. Further, the pitch of the inner leads 106, i.e., the inner lead pitch p, is set to 5 μm by the pitch of the bump electrodes 105 to be described later. Further, the inner leads 106 are spaced apart from each other, i.e., the inner lead gap 〇 is 25 μm. Further, the line width W of the inner lead 106 is also 25 μm. The line width w of the inner lead gap G and the inner lead 1 〇6 is set by considering the balance of the risk, that is, the etching residue, the migration due to the etching residue, and the like, causing the inner lead wires 6 to approach each other. The risk is balanced with the risk caused by the thinning of the inner lead 106 and the reduction in current capacity. Fig. 2 is a schematic view of a semiconductor device according to a third embodiment of the present invention as seen obliquely from above. Further, Fig. 3 is an enlarged view of the semiconductor wafer mounting region 1〇3 of Fig. 2 . Further, in Fig. 3, for ease of understanding, the resin 丨1〇 is illustrated as a transparent material. As shown in FIG. 2 and FIG. 3, the semiconductor device includes a replaceable substrate 101, and the semiconductor wafer 1 (4') is connected to the usable substrate 1G1 by a flip chip connection and mounted on a semiconductor wafer. The region (8); and the resin 110, which covers the opening 113 of the solder resist layer 112. 164650.doc 8 • 12- 201244040 A plurality of bump electrodes 105 are formed under the semiconductor wafer 104 (surface on the side of the squeezable substrate 1 〇 1). More specifically, the lower surface of the semiconductor crystal 104 has a rectangular shape. A plurality of bump electrodes 105 are formed along the lower side of the lower surface. Thereby, each pattern of the wiring 1 2 described later can be simplified in a straight line shape. In the plurality of bump electrodes 105, the bump electrodes 1 〇 5 in the vicinity of the long side of the lower side of the semiconductor wafer 1 系 4 are output side electrodes, and the bump electrodes 105 near the long sides of the lower side of the semiconductor wafer are input. Side electrode. Further, the bump electrode 105 is not formed in the vicinity of the short side of the lower surface of the semiconductor wafer 104. The surface of the substrate 1 on one of the constituent portions of the flexible substrate 1〇1 (the surface on the side of the semiconductor wafer 104) is formed. There is a wiring 1〇2, and a solder resist layer 112 is formed to cover most of the wiring 102. The above wiring 102 is formed of a copper foil having a thickness of 8 μm. Further, the end portion of the above-mentioned cloth, the semiconductor wafer mounting region 丨〇3 side of the spring 102 is formed as an inner lead 106. That is, the inner lead 1〇6 is a part of the wiring 1〇2. The above resin 11 is present around the semiconductor wafer 104. A part of the resin 11〇 enters the gap s between the flexible substrate 1〇1 and the semiconductor wafer 1〇4. Since the bump electrode 105 and the inner lead 1〇6 are densely arranged in a line in the vicinity of the long side under the semiconductor wafer 1〇4, the substantially flexible substrate 1〇1 and the semiconductor are formed like a wall. The state of the gap §4 of the wafer. On the other hand, there is no bump electrode 105 near the short side under the semiconductor wafer 104, and the second wiring portion 121 of the jumper 1U extends across the semiconductor along the long side of the semiconductor wafer 164650.doc •13·201244040 104 The wafer mounting region 1〇3 protrudes from the inside of the semiconductor wafer mounting region 103 toward the outside of the semiconductor wafer mounting region 1〇3. Thus, the semiconductor wafer is traversed by not forming the bump electrode 105 near the short side under the semiconductor wafer 1 〇4, and extending the first wiring portion 12 of the jumper 111 along the long side of the underside of the semiconductor wafer 104. In the mounting region 1〇3, the air bubbles in the gap S between the flexible substrate 101 and the semiconductor wafer 104 can be discharged from the vicinity of the short side of the lower surface of the semiconductor wafer 104 to the outside of the semiconductor wafer mounting region 103. Therefore, the above-described flexible substrate 101 has a high bubble discharge effect from the inside of the semiconductor wafer mounting region 103 to the outside of the semiconductor wafer mounting region 103. In addition, since the jumper ill does not form a loop in the semiconductor wafer mounting region 1A, it is possible to prevent air bubbles from being trapped in the semiconductor wafer mounting region 103. In the first embodiment, the second wiring portion 122 is formed to be located. The position of the solder resist layer 112 outside the opening 113 may be formed at a position within the opening 113 of the solder resist layer 112. In other words, the second wiring portion 122 may not be covered with the solder resist layer 112. The third wiring portion 123 is formed to be solder-resistable, but may be formed in the solder resist layer U2. The third wiring portion 123 may not be located in the opening 113 at a position outside the opening 113 of the layer 112 in the first embodiment. . That is, the anti-corrosion layer 112 is covered. In the first embodiment described above, the line width of the inner lead 106 is 25 cm, but the line width may be other than this. Further, the thickness of the inner lead 1 〇 6 is 164650.doc ] 4 201244040 is 8 pm ' but may be other than ^ L ^ W < Namely, in the above-described first embodiment, an inner lead formed of a metal case having a thickness in the range of 1 to 50 μm and a line width of 6 to 300 Å can be used. In the first embodiment described above, a jumper having a line width narrower than the line width of the inner leads 1〇6 may be used. In the first embodiment described above, the electric current may flow through the jumper ui or the electric current may not flow through the jumper U1. (Second Embodiment) Fig. 4 is a schematic view of a main part of a semiconductor device according to a second embodiment of the present invention as seen from above. In Fig. 4, the same components as those of the embodiment shown in Fig. 4 are attached. The same reference numerals are given to the same components as those of the drawings, and the description thereof is omitted. Further, in Fig. 4, the illustration of the semiconductor wafer 204 included in the semiconductor device is omitted. The semiconductor device includes a flexible substrate 2〇1 and a semiconductor wafer 104 which is connected to the flexible substrate 2〇1 by a flip chip connection and is mounted on the semiconductor wafer mounting region 1〇3. The flexible substrate 201 includes a jumper 211 including a second wiring portion 221, a second wiring portion 222, a third wiring portion 223, a fourth wiring portion 224, and a fifth wiring portion 225. Further, the jumper wire 211 is an example of wiring. The first wiring portion 221 extends across the long side of the semiconductor wafer mounting region ι 3 and traverses the semiconductor wafer mounting region 103. In other words, the first wiring portion 221' is formed across the semiconductor wafer mounting region 1A3 and the region outside the semiconductor wafer mounting region 103. The second wiring portion 222 extends along the short side of the semiconductor wafer mounting region 103 by 164650.doc 15 201244040. One end of the second wiring portion 222 is connected to one end of the first wiring portion 221 . The third wiring portion 223 extends along the short side of the semiconductor wafer mounting region 1 〇3. One end of the third wiring portion 223 is connected to the other end of the wiring portion 221. The fourth wiring portion 224 extends in parallel with respect to the first wiring portion 221 along the long side of the semiconductor wafer mounting region 1〇3. Further, the fourth wiring portion 224 is formed in the same manner as the first wiring portion 221, and is formed from the semiconductor wafer mounting region 103 to a region other than the semiconductor wafer mounting region 1?. One end of the fourth wiring portion 224 is connected to the other end of the second wiring portion 222. On the other hand, the other end of the fourth wiring portion 224 is connected to the top end of the inner lead 206. The line width of the inner lead 206 is substantially the same as the line width of the fourth wiring portion 224, and is wider than the line width of the inner lead 106. The fifth wiring portion 225 extends in parallel with respect to the first wiring portion 21 along the long side of the semiconductor wafer mounting region 1〇3. In addition, similarly to the first wiring portion 221, the fifth wiring portion 225 is formed so as to extend over the semiconductor wafer mounting region 103 and the semiconductor wafer mounting region 1A3, and one end of the fifth wiring portion 225 is connected. The other end of the third wiring portion 223. On the other hand, the other end of the fifth wiring portion 225 is connected to the top end of the inner lead 206. The line width of the inner lead 206 is substantially the same as the line width of the fifth wiring portion 225, and is wider than the line width of the inner lead 106. Further, the line widths of the first wiring portion 22 1 , the second wiring portion 222 , the third wiring portion 223 , the fourth wiring portion 224 , and the fifth wiring portion 225 are substantially the same. I64650.doc -16- 8 201244040 Further, the inner leads 20 ό ' connected to the other ends of the fourth and fifth wiring portions 224 and 225 are formed to be longer than the other inner leads ι 6 . Further, the distance between the first wiring portion 221 and the fourth wiring portion 224 is substantially the same as the distance between the first wiring portion 22 1 and the fifth wiring portion 225. Further, a part of the portion other than the semiconductor wafer mounting region 1?3 of the jumper wire 211 is not covered by the solder resist layer i12 and is exposed. More specifically, in the semiconductor wafer mounting region 1A, a portion of the first wiring portion 221, a portion of the fourth wiring portion 224, and a portion of the fifth wiring portion 225 are not covered by the anti-corrosion layer 112, and are exposed. . Further, all of the second end portions of the first wiring portion 221, the second and third wiring portions 222 and 223, and one of the fourth and fifth wiring portions 224 and 225 are covered by the solder resist layer U2. Thereby, the reliability of the above jumper 211 can be improved. The solder resist layer 112 is an example of a pattern protective film. Further, the bump electrode 205 is connected to the first wiring portion 221 and the inner lead 206. Fig. 5 is a schematic cross-sectional view taken along line V-V of Fig. 4. The bump electrodes 105 and 205 are formed on the lower surface of the semiconductor wafer 204 (the surface on the side of the flexible substrate 2〇1). Further, the surface of the semiconductor wafer 2〇4 has a rectangular shape. The bump electrode 205 connected to the first wiring portion 221 is formed to be slightly offset from the long side of the semiconductor wafer 104. A bump electrode 205 connected to the inner lead 206 is formed near the long side of the underside of the semiconductor wafer 104. The semiconductor wafer 204 is supplied to a column (not shown) for voltage 164650.doc -17- 201244040 Print drive n 'The current generated when the voltage is supplied to the upper (four) print head will flow through the inner lead 206 and the jumper 211. Therefore, the inner lead 2〇6 and the jumper 2H are not designed to be burned by the above current, and therefore must be designed to sufficiently reduce the wiring size of the resistor. Specifically, the inner lead 2〇6 and the jumper 2 are formed by a copper foil having a thickness of 8 μm and a line width of 40 μm. Since the cross-sectional area of the inner lead 206 and the jumper 2U is 32 〇 μηη2, the inner lead 206 and the jumper 2 11 can be sufficiently prevented from being burned by the current. The inventors have found through experiments that in the design with a margin of 0.2 实际 for the actual processing current of the semiconductor wafer 2 〇 4, when considering the wiring line width of 1 〇 of the current 2 A, the cross-sectional area of the wiring needs 3 〇〇gm2. Therefore, if the thickness of the current flexible substrate is limited to 1 μm, the wiring line width needs to be 300 μη^, and vice versa. If the wiring is thickened, the wiring line width can be reduced, as used in the previous TCP (volume). In the case of a tape carrier package: Tape Carrier Package, etc., if a copper foil having a thickness of 5 μm is used, the wiring line width can be reduced to 6 μm. Further, in the flexible substrate 201, similarly to the flexible substrate 1?1, bubbles between the flexible substrate 201 and the semiconductor wafer 204 can be discharged from the vicinity of the short side of the lower surface of the semiconductor wafer 204 to the semiconductor wafer. Mounting area 10 3 is outside. Therefore, the above-described flexible substrate 201 has a high bubble discharge effect from the inside of the semiconductor wafer mounting region 1A to the outside of the semiconductor wafer mounting region 103. In the second embodiment, the second wiring portion 222 is formed at a position outside the opening 113 of the solder resist layer 11 2, but may be formed at a position inside the opening 113 of the anti-fresh layer 1 j 2 . That is, the second wiring portion 222 may not be covered with the solder resist layer 112 of I64650.doc.jg. 8 201244040. In the second embodiment, the third wiring portion 223 is formed at a position outside the opening 113 of the solder resist layer 112, but may be formed at a position inside the opening 113 of the solder resist layer 112. In other words, the third wiring portion 223 may not be covered with the solder resist layer 112. In the second embodiment described above, the semiconductor device may further include a resin covering the opening 113 of the solder resist layer 112. (Embodiment 3) FIG. 6 is a schematic view of a main part of a semiconductor device according to a third embodiment of the present invention as seen from above. It is noted that the same components as those of the first embodiment shown in Fig. 6 are denoted by the same reference numerals as the components of Fig. i, and the description thereof will be omitted. Further, in Fig. 6, the illustration of the semiconductor wafer included in the semiconductor device is omitted. The semiconductor device is different from the first embodiment in that the bump electrode 305 is connected to the first wiring portion 12 1 of the jumper i 1 . The above semiconductor wafer is a liquid crystal driver. Further, a bump electrode, 3〇5, is formed on the lower surface of the semiconductor wafer (the surface on the side of the flexible substrate 1〇1). Further, the lower surface of the semiconductor wafer has a rectangular shape. The above-mentioned bump electrode 3〇5 is formed at a position slightly below the long side of the semiconductor wafer 1〇4. Furthermore, the potential of the bump electrode 305 is a ground potential. In the liquid crystal drive wafer in which the operating frequency is increased due to the serialization of the input signal in recent years, the design elements of the high frequency circuit are indispensable, and in order to stabilize the ground potential, the electrode of the ground potential should be placed in a desired state. position. Therefore, the above-mentioned bump electrode 305 is formed under the semiconductor wafer I64650.doc -19-201244040 and connected to the first wiring portion 121 of the jumper 111. Thus, by forming the bump electrode 305 on the lower surface of the semiconductor wafer and connecting it to the first wiring portion 121 of the jumper 111, the electrical function of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic plan view of a principal part of a flexible substrate according to a first embodiment of the present invention. Fig. 2 is a schematic perspective view showing a semiconductor device according to a third embodiment of the present invention. 3 is an enlarged view of a semiconductor wafer mounting region of FIG. 2. Fig. 4 is a schematic plan view of a principal part of a semiconductor device according to a second embodiment of the present invention. Figure 5 is a cross-sectional view taken along line V-V of Figure 4. Fig. 6 is a schematic plan view of a principal part of a semiconductor device according to a third embodiment of the present invention. Fig. 7 is a schematic perspective view of a conventional COF type semiconductor device. Figure 8 is a schematic plan view of a principal part of a prior prismatic substrate. Fig. 9 is a schematic plan view of a principal part of another prior flexible substrate. [Description of main component symbols] 100 substrate 101, 201 flexible substrate 102 wiring 103 semiconductor wafer mounting region 105, 205, 305 bump electrodes 106, 206 inner leads • 20-164650.doc 8 201244040 111, 211 jumper 112 Anti-friction layer 121, 221 First wiring portion 122' 222 Second wiring portion 123, 223 Third wiring portion 124, 224 Fourth wiring portion 125, 225 Fifth wiring portion 164650.doc - 21 -