KR102191249B1 - Chip resistor assembly - Google Patents

Abstract

A chip resistor assembly according to an embodiment of the present invention includes a circuit board having a plurality of electrode pads; And a chip resistance element disposed on the circuit board and electrically connected to the plurality of electrode pads, wherein the chip resistance element includes a first surface and a second surface opposite to each other, and the first surface and the second surface A base substrate having two side surfaces connecting the first side and two cross-sections connecting the first side and the second side, a resistance layer disposed on the second side, and each connected to the resistance layer on the second side and separated from each other It is disposed on the resistance layer between the first terminal and the second terminal on the first terminal and the second terminal to be disposed, and on the second surface, and through at least one side surface of the resistance layer, the base substrate A surface of a third terminal including a third terminal extending along the side surface to the first surface of the base substrate, and solder electrically connecting the electrode pad and the third terminal provided on the side surface of the base substrate And the third terminal includes a lower surface disposed on the resistance layer provided on the second surface of the base substrate, two side surfaces disposed on each of the two side surfaces of the base substrate, and the base substrate And an upper surface portion disposed on the first surface of, and each of the two side portions is connected to the lower surface portion and the upper surface portion, so that the third terminal may be integrally formed.

Description

Chip resistance element assembly {CHIP RESISTOR ASSEMBLY}

The present invention relates to a chip resistance device assembly.

The chip-shaped resistance element is suitable for realizing precision resistance, and can play a role of controlling current and dropping voltage in a circuit.

In addition, when the printed circuit board is platformed by designing a printed circuit board so that electronic parts can be replaced, removed, or added according to the specifications of various electronic devices on one printed circuit board, the resistive element is applied to the designed circuit. It may also be used to connect patterns on a printed circuit board as appropriate.

In addition, the resistance element may be used as a pull-up resistor or a pull-down resistor by connecting the pattern of the printed circuit board to power or ground.

However, when a plurality of resistance elements are used to design a circuit that satisfies the specifications of an electronic device, there is a problem in that the mounting area for the plurality of resistance elements in the printed circuit board is essentially increased.

In particular, it is not desirable to increase the mounting area occupied by the resistive element in the printed circuit board because the electronic device is required to be miniaturized and precise.

Republic of Korea Patent Publication No. 2016-0052283

According to an embodiment of the present invention, a chip resistance device having excellent mounting area efficiency on a circuit board and capable of stable connection with a circuit board may be provided.

A chip resistor assembly according to an embodiment of the present invention includes a circuit board having a plurality of electrode pads; And a chip resistance element disposed on the circuit board and electrically connected to the plurality of electrode pads, wherein the chip resistance element includes a first surface and a second surface opposite to each other, and the first surface and the second surface A base substrate having two side surfaces connecting the first side and two cross-sections connecting the first side and the second side, a resistance layer disposed on the second side, and each connected to the resistance layer on the second side and separated from each other It is disposed on the resistance layer between the first terminal and the second terminal on the first terminal and the second terminal to be disposed, and on the second surface, and through at least one side surface of the resistance layer, the base substrate A surface of a third terminal including a third terminal extending along the side surface to the first surface of the base substrate, and solder electrically connecting the electrode pad and the third terminal provided on the side surface of the base substrate And the third terminal includes a lower surface disposed on the resistance layer provided on the second surface of the base substrate, two side surfaces disposed on each of the two side surfaces of the base substrate, and the base substrate And an upper surface portion disposed on the first surface of, and each of the two side portions is connected to the lower surface portion and the upper surface portion, so that the third terminal may be integrally formed.

The chip resistance device according to an embodiment of the present invention has excellent efficiency when mounting a substrate and has an effect of enabling a stable connection with a printed circuit board.

Various and beneficial advantages and effects of the present invention are not limited to the above-described contents, and may be more easily understood in the course of describing specific embodiments of the present invention.

1 is a perspective view showing a chip resistance device according to an embodiment of the present invention.
FIG. 2 is an example of a cross-sectional view of the chip resistance device shown in FIG. 1 taken along line I-I'.
3 is another example of a cross-sectional view of the chip resistance element shown in FIG. 1 taken along line I-I'.
4 is a bottom view of the chip resistance element shown in FIG. 1.
5 is a perspective view illustrating a chip resistance device according to an embodiment of the present invention.
6 is a cross-sectional view taken along line II-II' of the chip resistance device shown in FIG. 4.
7 is a perspective view showing a chip resistance device according to an embodiment of the present invention.
8 is a perspective view illustrating a chip resistor assembly according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

The present embodiments may be modified into other forms or features of various embodiments may be combined with each other. Even if matters described in one embodiment are not described in other embodiments, they may be combined into descriptions of other embodiments unless there is a contradictory or contradictory description in other embodiments.

The shapes and sizes of elements in the accompanying drawings may be exaggerated for clearer description, and elements indicated by the same reference numerals in the drawings may be understood as the same or similar elements. In addition, in this specification, terms such as'upper','upper','lower','lower','cross-section', and'side' are expressed based on the directions of the attached drawings, and in fact, elements are arranged. It may be different depending on the direction of being.

When an element or layer is referred to as “on” or “on” of another element or layer, it includes both directly above the other element or layer as well as intervening another element or layer in the middle. do. On the other hand, when an element is referred to as “directly on” or “directly on”, it indicates that no other element or layer is interposed therebetween.

1 is a perspective view illustrating a chip resistance device according to an embodiment of the present invention, and FIG. 2 is an example of a cross-sectional view taken along line I-I' of the chip resistance device shown in FIG. 1, and FIG. 3 is This is another example of a cross-sectional view of the chip resistance element shown in Fig. 1 taken along line I-I'.

1 and 2, the chip resistance device 100 according to an embodiment of the present invention includes a base substrate 110, a resistance layer 120, and first to third terminals 131, 132, and 133. Include. In addition, a first protective layer 140 and a second protective layer 150 may be further included.

The base substrate 110 is for supporting the resistive layer 120 and securing the strength of the resistive element 100, and is not particularly limited, and for example, an insulating substrate may be used, and the surface is anodized to insulate It may be formed of alumina material.

In addition, the base substrate 110 has a predetermined thickness and may be configured in a thin plate shape having a rectangular shape on one side, and a first side and a second side facing each other, two cross sections facing each other, and facing each other. It can have two sides.

For example, as shown in FIGS. 1 and 2, the first and second surfaces may be upper and lower surfaces of the base substrate 110 facing each other in the thickness direction T. In addition, the two cross-sections are two surfaces of the base substrate 110 facing in the length direction (L), and the two side surfaces are the bases facing each other in the width direction (W) of the base substrate 110 These are the two sides of the substrate 110.

In addition, since the base substrate 110 is formed of a material having excellent thermal conductivity, when a resistance element is used, it may serve as a heat diffusion passage for dissipating heat generated by the resistance layer 120 to the outside.

The resistive layer 120 is disposed on the second surface of the base substrate. In addition, the resistance layer 120 may be connected to the first to third terminals 131, 132, and 133 spaced apart from each other to be used as two resistance elements between the first to third terminals 131, 132, and 133. . Also, unlike the present embodiment, the resistive layer 120 may be provided separated from each other by two resistive elements.

For example, the resistance value of the resistance layer 120 may be determined by trimming. Trimming refers to a process such as cutting for fine adjustment of a resistance value, and may be a process of determining a resistance value set in each resistance unit when designing a circuit.

Although not limited thereto, various metals or alloys or compounds such as oxides may be used for the resistance layer 120. For example, it may include at least one of Cu-Ni-based alloy, Ni-Cr-based alloy, Ru oxide, Si oxide, Mn and Mn-based alloy.

The first terminal 131 and the second terminal 132 are respectively connected to the resistance layer 120 and disposed to be separated from the second surface of the base substrate 110. For example, the first terminal 131 and the second terminal 132 2 The terminal 132 extends to the cross section of the base substrate 110 and portions 131-1 and 132-1 disposed on both sides of the lower surface of the base substrate 110, as shown in FIGS. 1 and 2 It may include the portion (131-2, 132-2). In this form, the first terminal 131 and the second terminal 132 cover one end and the other end of the resistance layer 120, respectively. In addition, the first terminal 131 and the second terminal 132 may each extend to a cross-section of the base substrate 110 and cover a corner where the lower surface of the base substrate 110 and the cross-section meet.

The third terminal 133 is disposed between the first terminal 131 and the second terminal 132 on the second surface of the base substrate 110 and is connected to the resistance layer 120. In addition, the third terminal 133 is disposed to extend to the first surface along the side surface of the base substrate 110.

1 and 2, the third terminal 133 is a lower surface portion 133-1, which is a portion disposed on the lower surface of the base substrate 110, and a portion disposed on the side surface of the base substrate 110. It may be composed of a side portion 133-2 and an upper surface portion 133-3 that is a portion disposed on the upper surface of the base substrate 110.

In this form, the third terminal 133 may extend from the lower surface of the base substrate 110 to the upper surface of the base substrate 110 along the side surfaces.

* When the third terminal 133 has a structure extending only from the lower surface to the side surface, the third terminal 133 may have a problem that the third terminal 133 is separated from the side surface of the base substrate 110 due to an external impact. In the chip resistance device 100 according to an embodiment of the present invention, since the third terminal 133 has an integral shape extending from the lower surface of the base substrate 110 to the upper surface along the side surface, the third terminal 133 and the The bonding strength of the base substrate 110 may be improved.

Specifically, the first to third terminals 131, 132, 133 may each include first to third electrode layers 131a, 132a, 133a disposed on the resistance layer 120, and the first to First to third plating layers 131b, 132b, and 133b disposed on the third electrode layers 131a, 132a, and 133a may be included, respectively.

For example, as shown in FIG. 2, the first terminal 131 includes a first electrode layer 131a and a first plating layer 131b, and the second terminal 132 includes a second electrode layer 132a and a second electrode layer 132a. It includes two plating layers 132b, and the third terminal 133 may include a third electrode layer 133a and a third plating layer 133b.

The first to third electrode layers 131a, 132a, and 133a are disposed to be spaced apart from each other on one surface of the resistance layer 120, and the third electrode layer 133a is a first electrode layer 131a and a second electrode layer 132a. Can be placed between. In addition, the first to third electrode layers 131a, 132a, 133a may be connected to the resistance layer 120, respectively. In addition, the first electrode layer 131a and the second electrode layer 133a may be disposed to cover both sides of the resistance layer 120.

Although not limited thereto, the first to third electrode layers 131a, 132a, 133a may be formed by applying a conductive paste for forming a conductive electrode on the resistance layer 120, and the application method is screen printing. Such methods can be used.

In addition, the first to third electrode layers 131a, 132a, 133a may serve as seeds of a plating process for forming the first to third plating layers 131b, 132b, and 133b.

The first to third electrode layers 131a, 132a, and 133a may be formed of a conductive paste of a material different from the aforementioned resistive layer 120, and the same component as the resistive layer 120 may be used if necessary. .

Referring to FIG. 3, the first and second electrode layers 131a ′ and 132a ′ may cover both side portions of the resistance layer 120, and may cover edges where the lower surface of the base substrate 110 and the cross-section abut. Accordingly, the first and second terminals 131 ′ and 132 ′ including the first and second plating layers 131 b ′ and 132 b ′ may be formed higher along the cross section with respect to the lower surface of the base substrate 110. have.

Meanwhile, as described above, the third terminal 133 may include a lower surface portion 133-1 and a side portion 133-2, and each of the lower surface portion 133-1 and the side portion 133-2 It consists of a third electrode layer 133a and a third plating layer 133b.

In addition, a portion of the third electrode layer 133a may be formed through a deposition process.

Specifically, a portion of the third electrode layer 133a disposed on the side of the base substrate 110 and forming the side portion 133-2 may be formed through a deposition process on the side of the base substrate 110.

As such, the third terminal 133 includes not only the second surface of the base substrate 110 but also the third electrode layer 133a disposed on the side surface of the base substrate 110.

Accordingly, the third terminal 133 may be formed higher than the first terminal 131 and the second terminal 132 along the side surface with respect to the lower surface of the base substrate 110, and the side surface of the base substrate 110 It is possible to secure a joint area with solder.

During the soldering process, a so-called solder in excess phenomenon may occur, which is a problem in which solder is formed in unnecessary places around the electrode pads due to excess solder. Solder balls formed by such over-lead cause a short circuit between electrode pads, causing malfunction and overcurrent.

The chip resistance device according to an exemplary embodiment of the present invention can prevent such overpayment and has sufficient adhesion strength between the electrode pad disposed on the circuit board and the third terminal.

Table 1 below shows the data of Experimental Example 1, in which the mounting state of the chip resistance element is appropriate according to the presence or absence of the side portion.

In Experimental Example 1, a chip resistance device having a third terminal 133 including a side portion 133-2 and a chip resistance device having no side portion were added to the electrode pad of the printed circuit board through a reflow process per unit (lot, time). When 1000 pieces are mounted and an over-lead phenomenon or a cold solder joint phenomenon occurs, the result of discrimination as defective (NG) is shown.

Referring to Table 1, it can be seen that a defect has occurred when a chip resistor element without a side part is mounted on a printed circuit board. In particular, when a chip resistance element without a side portion is mounted on a printed circuit board coated with PSR (Photo Imageable Solder Resist) ink between electrode pads to which the first to third terminals 131, 132, and 133 are joined by solder , The defect rate is remarkably high.

In the chip resistance device according to an exemplary embodiment of the present invention, a defect occurring in the chip resistance device without a side portion does not occur.

Specifically, the third electrode layer 133a includes a third lower electrode layer 133a-1, a third side electrode layer, and a third upper electrode layer 133a-3. Since the third lower surface electrode layer 133a-1, the third side electrode layer, and the third upper electrode layer 133a-3 function as seeds during the plating process, the third plating layer 133b is the third lower electrode layer 133a. -1) It may be formed on the third side electrode layer and the third upper electrode layer 133a-3, including the third bottom plating layer 133b-1 formed on the top.

As described above, in the chip resistance element 100 according to an embodiment of the present invention, the upper surface portion of the third terminal 133 has an integral shape extending from the lower surface of the base substrate 110 to the upper surface along the side surface. It includes (133-3).

Table 2 below shows the data of Experimental Example 2 in which the state of the chip resistance element was tested according to the presence or absence of the upper surface.

Experimental Example 2 shows the results of a taping test and an impact test after mounting for a chip resistance device in which the third terminal 133 includes an upper surface portion 133-3 and a chip resistance device without an upper surface portion. .

Specifically, the taping test is a test in which an impact is applied to the chip resistance element when the chip resistance element is inserted into the tape by misalignment in the taping process of packaging the chip resistance element, and a plurality of printed circuit boards after mounting the chip resistance element This is a test in which an impact is applied to the mounted chip resistance element by stacking and applying a certain shake.

A test was conducted for 1,000 chip resistance elements per unit (lot, time), and when a phenomenon in which the third terminal 133 was separated from the side of the base substrate 110 was identified as defective (NG).

Referring to Table 2, defects occur in the chip resistance element without the upper surface portion, but the chip resistance element according to an embodiment of the present invention does not cause defects that occur in the chip resistance element without the upper surface portion 133-3. Did.

In addition, a first protective layer 140 for protecting the resistance layer 120 from external impact may be disposed on the surface of the resistance layer 120 on which the first to third electrode layers 131a, 132a, 133a are not disposed. have.

Although not limited thereto, the first protective layer 140 may be made of silicon (SiO ₂ ) or glass, and may be formed on the resistance layer 120 and the base substrate 110 by overcoating. I can.

In a specific example, the first protective layer 140 may be composed of an inner protective layer made of glass and an outer protective layer made of polymer. If necessary, the inner protective layer is formed before the trimming process to prevent cracking in the resistance layer 120 during the trimming process, and the outer protective layer is formed after the trimming process. The resistance layer 120 may be protected.

On the other hand, even if the first protective layer 140 is disposed on the resistance layer 120 and the base substrate 110, the first to third terminals 131, 132, 133 protrude from the first protective layer 140 By having a, it is possible to facilitate contact between the first to third terminals 131, 132, and 133 and electrode pads disposed on the substrate when the substrate is mounted.

In addition, a second protective layer 150 may be disposed on the first surface of the base substrate 110. The second protective layer 150 may protect the chip resistance device 100 from external impact. For example, the second protective layer 150 may have a predetermined height to prevent an impact from an upper portion of the chip resistance element 100 from being applied to the side electrode 133-2 of the third terminal.

In addition, the second protective layer 150 may be formed by applying an insulating material, and the application method may use a method such as screen printing.

Meanwhile, the second protective layer 150 may be applied after the third upper electrode layer 133a-3 is formed, and then a plating process may be performed. Accordingly, the third plating layer 133b formed through the plating process may be formed except for a portion of the third upper electrode layer 133a-3 on which the second protective layer 150 is applied.

Meanwhile, the third upper electrode layer 133a-3 may be formed by printing a conductive paste.

4 is a bottom view of the chip resistance element shown in FIG. 1.

Referring to FIG. 4, the chip resistance element includes first to third terminals 131, 132, and 133. In addition, a first protective layer 140 may be included.

Here, the third terminal 133 is not only a portion 133-1 disposed between the first terminal 131 and the second terminal 132 on the lower surface of the base substrate, but also a portion 133 extending to the side of the base substrate. Since -2) is included, it is possible to secure the contact area with the solder during the reflow process and ensure a stable connection with the circuit board.

5 is a perspective view illustrating a chip resistance device according to an embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along ?-?' of the chip resistance device illustrated in FIG. 5.

The chip resistance device 100 ′ shown in FIGS. 5 and 6 is separated from the first surface of the base substrate 110 with the second protective layer 150 ′ compared to the resistance device 100 shown in FIG. 1. There is a difference in that the third terminal 133' is disposed between the disposed and separated second protective layers 150'.

Specifically, since the second protective layer 150 ′ is not applied on the third upper electrode layer 133a-3 ′ of the third terminal 133 ′, the third upper electrode layer 133a-3 ′ during the plating process A third top plating layer 133b-3' may be formed on the top surface, and the third top plating layer 133b-3' extends to both sides of the base substrate 110.

Other configurations can be understood from the chip resistance device described with reference to FIGS. 1 to 4, and thus redundant descriptions will be omitted.

7 is a perspective view showing a chip resistance device according to an embodiment of the present invention.

The difference in that the chip resistance element 100" shown in FIG. 7 is arranged so that the third terminal 133" is separated from the first surface of the base substrate 110 compared to the resistance element 100 shown in FIG. 1 There is this.

For example, the third terminal 133" may be composed of a lower surface portion 133-1, a side surface portion 133-2, and an upper surface portion 133-3, as shown in FIG. 6, and the upper surface The portion 133-3 may extend from the side portion 133-2 and may be separated and disposed on both sides of the width direction W with respect to the second protective layer 150 on the first surface of the base substrate 110 .

Since other configurations and functions can be understood from the chip resistance element described with reference to FIGS. 1 to 4, duplicate descriptions will be omitted.

8 is a perspective view illustrating a chip resistor assembly according to an embodiment of the present invention.

Referring to FIG. 8, a resistance element assembly 10 according to an exemplary embodiment of the present invention includes a circuit board 11 on which a plurality of electrode pads and chip resistance elements 100 are mounted to be spaced apart from each other.

The chip resistance element 100 is connected to a base substrate 110 having a first surface and a second surface, a resistance layer disposed on a second surface of the base substrate 110, and the resistance layer on the second surface, respectively, First and terminal 131 and second terminal 132 disposed to be separated from each other, and connected to the resistance layer on the second surface and disposed between the first terminal and the second terminal, and along the side, the It includes a third terminal 133 extending to the first surface.

In addition, the third terminal 133 includes a lower surface portion 133-1, which is a portion disposed on the lower surface of the base substrate 110, a side portion 133-2, which is a portion disposed on the side surface of the base substrate 110, and It may be composed of an upper surface portion 133-3, which is a portion disposed on the upper surface of the substrate 110.

The chip resistance device assembly 10 of FIG. 8 is illustrated to include the chip resistance device 100 shown in FIG. 1, but the chip resistance device assembly 10 may include the chip resistance device 100 ′ of FIG. 5. In addition, the chip resistance device 100" of FIG. 7 may be included.

Since the chip resistance device 100 can be understood from the chip resistance device described with reference to FIGS. 1 to 7, overlapping descriptions will be omitted.

The circuit board 11 is a part in which an electronic circuit is formed, and an integrated circuit (IC) for specific operation or control of an electronic device is formed so that a current supplied from a separate power source may flow.

In this case, the circuit board 11 may include various wiring lines or may further include other types of semiconductor devices such as transistors. In addition, the circuit board 11 may be configured in various ways as necessary, such as including a conductive layer or a dielectric layer.

The first to third electrode pads 12, 13, and 14 are disposed to be spaced apart from each other on the circuit board 11, and the first to third terminals 131 of the resistive element 100 are formed by solder 15. 132 and 133), respectively.

In FIG. 8, the first electrode pad 12 is connected to the first terminal 131 and the second electrode pad 13 is connected to the second terminal 132. However, according to the design, the first electrode pad 12 ) May be connected to the second terminal 132 and the second electrode pad 13 may be connected to the first terminal 131.

As shown in FIG. 8, the third terminal 133 includes a side portion 133-2 disposed on the side of the base substrate, and electrically connects the third electrode pad 14 and the third terminal. Solder may be disposed on the surface of the side portion.

Accordingly, the chip resistance device assembly 10 according to an exemplary embodiment of the present invention may prevent defects in the occurrence of solder balls, and may improve adhesion strength between the chip resistance device 100 and the circuit board 11.

In addition, since the third terminal 133 includes an upper surface portion 133-2 disposed on the upper surface of the base substrate and extending from the side surface portion 133-2, the third terminal 133 is durable against impact. This is improved.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and variations are possible without departing from the technical matters of the present invention described in the claims. It will be obvious to those of ordinary skill in the field.

100, 100', 100": resistive element
110: base substrate
120: resistance layer
131, 131': first terminal
132, 132': second terminal
133, 133', 133": 3rd terminal
140: first protective layer
150, 150': second protective layer

Claims (5)

A circuit board having a plurality of electrode pads; And
A chip resistance element disposed on the circuit board and electrically connected to the plurality of electrode pads,
The chip resistance element is a base substrate having a first surface and a second surface facing each other, two side surfaces connecting the first surface and the second surface, and two cross-sections connecting the first surface and the second surface , A resistance layer disposed on the second surface, a first terminal and a second terminal connected to the resistance layer on the second surface and disposed to be separated from each other,
It is disposed on the resistance layer between the first terminal and the second terminal on the second surface, and through at least one side surface of the resistance layer, the first of the base base material along the side surface of the base base material. A third terminal extending in the plane, and
Including a protective layer disposed on the first surface,
Solder electrically connecting the electrode pad and the third terminal is disposed on the surface of the third terminal provided on the side surface of the base substrate,
The third terminal may include a lower surface disposed on the resistance layer provided on the second surface of the base substrate, two side surfaces disposed on each of the two side surfaces of the base substrate, and the first of the base substrate Including an upper surface portion disposed on the surface,
The upper surface portion is formed of a plurality of layers including an upper electrode layer and a plating layer disposed on the upper electrode layer and exposing at least a partial region of the upper electrode layer,
The protective layer is disposed on at least a partial area of the exposed area of the upper electrode layer.
The method of claim 1,
Each of the first terminal and the second terminal extends to the cross-section to cover a corner where the second surface and the cross-section meet.
delete delete A circuit board having a plurality of electrode pads; And
A chip resistance element disposed on the circuit board and electrically connected to the plurality of electrode pads; Including,
The chip resistance element is a base substrate having a first surface and a second surface facing each other, two side surfaces connecting the first surface and the second surface, and two cross-sections connecting the first surface and the second surface ,
A resistance layer disposed on the second surface,
A first terminal and a second terminal connected to the resistance layer on the second surface and disposed to be separated from each other,
It is disposed on the resistance layer between the first terminal and the second terminal on the second surface, and through at least one side surface of the resistance layer, the first of the base base material along the side surface of the base base material A third terminal extending in the plane and
Including a protective layer disposed on the first surface,
Solder electrically connecting the electrode pad and the third terminal is disposed on the surface of the third terminal provided on the side of the base substrate,
The protective layer includes a first protective layer and a second protective layer that are spaced apart from each other in two regions on the first surface,
The third terminal includes a lower surface portion disposed on the resistance layer provided on the second surface of the base substrate, two side surfaces disposed on each of the two side surfaces of the base substrate, and the first of the base substrate It includes an upper surface portion disposed on the surface,
The chip resistance device assembly, wherein the upper surface portion is disposed between the first and second protective layers.

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