200843071 九、發明說明： 【發明所屬之技術領域】 本發明係關於可撓基板及例如COF(薄膜覆晶）型、捲帶 型等之半導體裝置。 【先前技術】 在現在之液晶驅動器晶片中，輸入信號藉由串行輸入， 其動作速度更為高速。又，基於液晶面板之大型化，輸出 至液晶面板之電壓變得更高。基於該等原因，上述液晶驅 動器晶片之發熱量變高。 另一方面’上述液晶驅動器晶片更為小型化，單位面積 之發熱量變得更高，在該等相乘效果下愈加發熱，若不採 取積極的散熱方法，就會發生故障。 於日本特開平10_32229號公報中，記載一種具有積極的 散熱構造之具可撓性之半導體裝置。 圖5係顯示從上方看上述半導體裝置之可撓基板1〇1之概 略圖又圖6係顯示從斜上方看搭載於上述可撓基板 上之半導體晶片109之概略圖。 上述可撓基板101，如圖5、圖6所示，主要由聚醯亞胺 薄膜與金屬箔構成，於其上面具有由該金屬箔構成之配線 圖案102。 上述配線圖案102，由内引線112、輸出外引線113、輸 入外引線114及牽引配線115構成。 上述内引線112係連接於半導體晶片1〇9之端子，又，輸 出外引線113係與液晶面板之連接端子，又，輸入外引線 128294.doc 200843071 ii4係與外部電路基板等之連接端子，再者，牵引配線U5 係連接輸出外引線113與輸入外引線114。 又，上述配線圖案1 02主要由銅箔構成，且為與後述半 導體晶片109連接，於該銅箔表面被覆有Sn(錫）。 上述半導體晶片109之下面（可撓基板1〇1側之表面）之周 邊部，藉由鍍Αιι形成有突起電極11〇。 又’半導體晶片1 09對上述可撓基板1 〇 1之連接，係從外 部對内引線112及突起電極110施與熱及壓力而進行。一旦 對内引線112及突起電極11 〇施加熱及壓力，可得到内引線 112之Sn與突起電極110之Au之共晶合金。 通常，與上述半導體晶片109之突起電極間距相配合之 内引線間距相比，用於朝液晶面板或外部電路基板連接之 外引線間距較粗，故牽引配線115其從内引線112到輸入輸 出外引線，成為扇出之圖案。 於上述可撓基板101之上面，於半導體晶片109之下面之 短邊的兩側形成有島狀之底層圖案116。 該底層圖案116，在可撓基板101之上面，以不與搭載半 導體晶片109之區域重疊之方式形成。又，上述底層圖案 116之表面積比各配線圖案1〇2之表面積之合計大。且，上 述底層圖案116連接於半導體晶片109下面之短邊附近之突 起電極110。藉此，由上述半導體晶片1〇9產生之熱傳至底 層圖案116,可於底層圖案116釋放該熱。又，上述底層圖 案116實際上與信號之輸入輸出無關。 又，若以連接於上述半導體晶片109之底層圖案116為接 128294.doc 200843071 地及電源端子，成為從半導體晶片1 09經由該底層圖案1 i 6 傳遞到未圖示之電路基板之接地及電源線之熱路徑，則由 於通常電路基板之電源及接地線比其他信號線寬，故藉由 該信號線可進一步有效率地散熱。 然而，上述可撓基板10 1，從材料節約與輕薄短小之觀 點來看，期望縮小可撓基板101本身，或縮小配線圖案102 之形成區域。因此，本來僅形成有助於電氣動作之配線圖 案102，使可撓基板1〇1具有散熱效果，但在專利文獻}之 半導體裝置中，除了有助於電氣動作之配線圖案i 〇2外，， 亦特意形成散熱專用圖案、即底層圖案116。進而，上述 底層圖案116形成為表面積比各配線圖案1〇2之表面積之合 計還大之島狀。 結果，日本特開平10_32229號公報之半導體裝置，成為 將可撓基板1〇1大型化之形態，具有不能使可撓基板ι〇ι小 型化之問題。 ί發明内容】 [發明所欲解決之問題] 因此’本發明之目的係提供—種可改善散熱性、可小型 化之可撓基板’及具備該可撓基板之半導體裝置。 [解決問題之技術手段] 為解決上述問題，發明去袒古 圖案之散熱效果。 -了本來有助於電氣動作之 本發明之可撓基板，其特徵在於具備： 於一表面具有半導髀曰、、 且日日片搭載區域與金屬箔圖案形成區 128294.doc 200843071 域之基材；及 形成於上述金屬箔圖案形成區域，且由金屬箔形成之複 數個配線圖案； 且於上述金屬箔圖案形成區域之至少一部分，以上述配 線圖案寬度相對於上述配線圖案彼此間之間隔的比率為超 過1且在8.7以下之方式，形成上述複數個配線圖案。 根據上述構成之可撓基板，配線圖案寬度相對於上述配 線圖案彼此間之間隔的比率為超過丨且在8·7以下。即，上 述配線圖案寬度除以配線圖案彼此間之間隔的值為超過i 且在8·7以下。此時，上述配線圖案彼此間之間隔之單位 與配線圖案寬度之單位相同。 因此，上述可撓基板，其配線圖案之表面積變大，可提 面配線圖案之散熱效果，結果可改善散熱性。 又，由於藉由改善上述可撓基板之散熱性，可縮小形成 於金屬箔圖案形成區域之例如底層圖案、或去掉該底層圖 案，故可使可撓基板小型化。 又，若以配線圖案寬度相對於上述配線圖案彼此間之間 的比率在1以下之方式形成複數個配線圖案，則配線圖 案之散熱效果變低。 又，右卩配線圖t X度相對於上述配線圖案彼此間之間 ^的比率超過8·7之方式形成複數個配線圖案，則發生配 線圖案彼此接觸之問題之機率變得非常高。 貝施形怨之可撓基板中，以平面視之，上述複數個 配線圖案之表面積合計係於上述基材之上述一表面之面積 128294.doc 200843071 的50%〜90%之範圍内。 根據上述實施形態之可撓基板，以平面視之，由於上述 複數個配線圖案之表面積合計係於基材之一表面之面積之 50〜90%之範圍内，故可將基材之一表面大部分作為有助 於散熱之區域。 在一實施形態之可撓基板中，以上述配線圖案寬度相對 於上述配線圖案彼此間之間隔的比率為超過1且在8·7以下 # 之方式形成之上述複數個配線圖案，具有扇出構造。 根據上述實施形態之可撓基板，由於以上述比率超過j 且在8.7以下之方式形成之複數個配線圖案具有扇出構 造，故其配線圖案與外部機器之連接容易。 在一實施形態之可撓基板中，上述基材之上述一表面中 之上述半導體晶片搭載區域以外之區域全部為上述金屬猪 圖案形成區域。 根據上述實施形態之可撓基板，由於上述基材之一表面 中之半導體晶片搭載區域以外之區域全部為金屬箱圖案形 成區域，故可增大有助於散熱之區域。 在一貫施形態之可撓基板中，於上述金屬箔圖案形成區 域形成有由金屬箔形成之底層圖案。 根據上述實施形態之可撓基板，由於在上述金屬箱圖案 形成區域中形成有由金屬箔形成之底層圖案，故藉由配線 圖案及底層圖案之散熱效果，可進一步改善散熱性。 在一實施形態之可撓基板中，上述底層圖案之至少一部 分係橫切上述半導體晶片搭載區域。 128294.doc -10- 200843071 根據上述實施形態之可撓基板，在上述半導體晶片搭载 區域搭載半導體晶片時，由於底層圖案之至少一部分橫切 半導體晶片搭載區域，故可增大底層圖案與半導體晶片之 接觸面積，可有效率地將熱從半導體晶片向底層圖案傳 因此，可防止上述半導體晶片因熱而故障。 在一實施形恶之可撓基板中，上述底層圖案上形成有 孔。 根據上述實施形態之可撓基板，由於上述底層圖案上形 成有孔，故底層圖案之表面積變大，可提高底層圖案之散 熱效果。 在一實施形態之可撓基板中，上述孔具有單數或複數 個，且上述孔之平面視形狀為長方形，且 上述孔具有複數個時，上述複數個孔配置為排列於與上 述長方形短邊平行之方向上。 根據上述實施形態之可撓基板，由於上述孔具有複數個 牯，複數個孔配置為排列於與上述長方形短邊平行之方向 上，故可增加孔之數量。 在-實施形態之可撓基板中，上述孔具有單數或複數 個，且上述孔之平面視形狀為圓形或多邊形，且 上述孔具有複數個時，上述複數個孔配置為矩陣狀。 根據上述實施形態之可撓基板，由於上述孔具有複數個 時，複數個孔配置為矩陣狀，故可增加孔之數量。 在-實施形態之可撓基板中’以平面視之，上述複數個 128294.doc -11 - 200843071 配線圖案之表面積、與包括上述孔之側面面積之上述底層 圖案之表面積的合計為上述基材之上述一表面之面積之 50〜90%之範圍内。 根據上述實施形態之可撓基板，以平面視之，由於上述 複數個配線圖案之表面積、與包括孔之側面面積之底層圖 案之表面積的合計為基材之一表面之面積之5〇〜9〇%之範 圍内，故可將基材之一表面之大部分作為有助於散熱之區 域。 在一實施形態之可撓基板中，上述孔係用於使搭載於上 述半導體晶片搭載區域之半導體晶片與上述半導體晶片搭 載區域進行位置對準之位置對準標記。 根據上述實施形態之可撓基板，由於上述孔係用於使搭 載於半導體晶片搭載區域之半導體晶片與該半導體晶片搭 載區域進行位置對準之位置對準標記’故可以不用另外形 成位置對準標記，可防止製造步驟增加。 本發明之半導體裝置，其特徵在於具備·· 本發明之可撓基板；及 搭載於上述半導體晶片搭載區域，且連接於上述複數個 配線圖案之半導體晶片。 根據上述構成之半導體裝置’由於可改善±述可挽基板 之散熱性，故可防止半導體晶片因熱而故障。 [發明之效果] 本發明之可撓基板，由於於金屬_案形成區域之至少 一部分中，以配線圖案宽唐 見度相對於配線圖案彼此間之間隔 128294.doc -12- 200843071 的比率為超過1且在8·7以下之方式形成複數個配線圖案， 故配線圖案之表面積變大，可提高配線圖案之散熱效果, 結果可改善散熱性。 又’由於可藉由提高上述可撓基板之散熱性，縮小形成 於金屬落圖案形成區域之例如底層圖帛、或去掉該底層圖 案，故可使可撓基板小型化。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flexible substrate and a semiconductor device such as a COF (film over-film) type, a tape-reel type, or the like. [Prior Art] In the current liquid crystal driver chip, the input signal is input at a higher speed by serial input. Moreover, the voltage output to the liquid crystal panel becomes higher based on the enlargement of the liquid crystal panel. For these reasons, the heat generation amount of the liquid crystal driver wafer described above becomes high. On the other hand, the above liquid crystal driver wafer is further miniaturized, and the amount of heat generation per unit area is increased, and heat is generated more by these multiplication effects, and failure occurs if an active heat dissipation method is not employed. Japanese Laid-Open Patent Publication No. Hei 10-32229 discloses a flexible semiconductor device having an active heat dissipation structure. Fig. 5 is a schematic view showing the flexible substrate 1〇1 of the semiconductor device as seen from above, and Fig. 6 is a schematic view showing the semiconductor wafer 109 mounted on the flexible substrate as seen obliquely from above. As shown in Figs. 5 and 6, the flexible substrate 101 is mainly composed of a polyimide film and a metal foil, and has a wiring pattern 102 made of the metal foil thereon. The wiring pattern 102 is composed of an inner lead 112, an output outer lead 113, an input outer lead 114, and a traction wiring 115. The inner lead 112 is connected to the terminal of the semiconductor wafer 1〇9, and the output lead 113 is connected to the liquid crystal panel, and the external lead 128294.doc 200843071 ii4 is connected to an external circuit board or the like. The traction wiring U5 is connected to the output outer lead 113 and the input outer lead 114. Further, the wiring pattern 102 is mainly composed of a copper foil and is connected to a semiconductor wafer 109 to be described later, and the surface of the copper foil is covered with Sn (tin). The peripheral portion of the lower surface of the semiconductor wafer 109 (the surface on the side of the flexible substrate 1〇1) is formed with a bump electrode 11 by plating. Further, the connection of the semiconductor wafer 109 to the flexible substrate 1 〇 1 is performed by applying heat and pressure to the inner lead 112 and the bump electrode 110 from the outside. Once heat and pressure are applied to the inner leads 112 and the bump electrodes 11, a eutectic alloy of Sn of the inner leads 112 and Au of the bump electrodes 110 can be obtained. Generally, the lead pitch for connection to the liquid crystal panel or the external circuit substrate is relatively thick compared to the inner lead pitch of the semiconductor wafer 109, and the traction wiring 115 is externally connected to the input and output. The lead wire becomes a fan-out pattern. On the upper surface of the flexible substrate 101, an island-shaped underlying pattern 116 is formed on both sides of the short side of the lower surface of the semiconductor wafer 109. The underlayer pattern 116 is formed on the upper surface of the flexible substrate 101 so as not to overlap with the region on which the semiconductor wafer 109 is mounted. Further, the surface area of the underlying pattern 116 is larger than the total surface area of each of the wiring patterns 1〇2. Further, the underlying pattern 116 is connected to the bump electrode 110 in the vicinity of the short side of the lower surface of the semiconductor wafer 109. Thereby, the heat generated by the semiconductor wafer 1〇9 is transferred to the underlayer pattern 116, and the heat can be released in the underlying pattern 116. Moreover, the above-described underlying pattern 116 is actually independent of the input and output of the signal. Further, when the underlying pattern 116 connected to the semiconductor wafer 109 is connected to 128294.doc 200843071 and the power supply terminal, the ground and power are transmitted from the semiconductor wafer 109 to the circuit substrate (not shown) via the underlying pattern 1 i 6 . In the hot path of the line, since the power source and the ground line of the circuit board are generally wider than other signal lines, the signal line can further efficiently dissipate heat. However, in the above-described flexible substrate 101, it is desirable to reduce the flexible substrate 101 itself or to reduce the formation region of the wiring pattern 102 from the viewpoint of material saving and lightness and thinness. Therefore, only the wiring pattern 102 which contributes to electrical operation is formed, and the flexible substrate 1〇1 has a heat radiation effect. However, in the semiconductor device of Patent Document, except for the wiring pattern i 〇 2 which contributes to electrical operation, A heat-dissipation-dedicated pattern, that is, a bottom pattern 116 is also intentionally formed. Further, the underlayer pattern 116 is formed in an island shape having a larger surface area than the total surface area of each of the wiring patterns 1〇2. As a result, the semiconductor device disclosed in Japanese Laid-Open Patent Publication No. Hei No. 10-32229 has a problem in that the flexible substrate 1〇1 is increased in size, and the flexible substrate cannot be miniaturized. SUMMARY OF THE INVENTION [Problems to be Solved by the Invention] Therefore, an object of the present invention is to provide a flexible substrate which can improve heat dissipation and can be miniaturized, and a semiconductor device including the same. [Technical means to solve the problem] In order to solve the above problems, the heat dissipation effect of the ancient pattern was invented. A flexible substrate of the present invention which contributes to electrical operation, and is characterized in that it has a semi-conducting surface on one surface, and a base of the solar-chip mounting region and the metal foil pattern forming region 128294.doc 200843071 And a plurality of wiring patterns formed in the metal foil pattern formation region and formed of a metal foil; and at least a portion of the metal foil pattern formation region is spaced apart from the wiring pattern by the width of the wiring pattern The plurality of wiring patterns are formed in such a manner that the ratio is more than 1 and not more than 8.7. According to the flexible substrate having the above configuration, the ratio of the width of the wiring pattern to the interval between the wiring patterns is more than 丨 and not more than 8.7. That is, the value of the width of the wiring pattern divided by the wiring pattern is more than i and not more than 8.7. At this time, the unit of the interval between the wiring patterns is the same as the unit of the width of the wiring pattern. Therefore, in the flexible substrate, the surface area of the wiring pattern is increased, and the heat dissipation effect of the wiring pattern can be improved, and as a result, heat dissipation can be improved. Further, by improving the heat dissipation property of the flexible substrate, for example, the underlying pattern formed in the metal foil pattern forming region can be reduced, or the underlying pattern can be removed, so that the flexible substrate can be miniaturized. In addition, when a plurality of wiring patterns are formed so that the ratio of the width of the wiring pattern to the wiring pattern is 1 or less, the heat dissipation effect of the wiring pattern is lowered. Further, when a plurality of wiring patterns are formed so that the ratio of the X-degree of the right-hand wiring pattern to the wiring pattern exceeds 8.7, the probability of occurrence of a problem that the wiring patterns are in contact with each other is extremely high. In the flexible substrate of the Besch, the total surface area of the plurality of wiring patterns is in the range of 50% to 90% of the area of the one surface of the substrate 128294.doc 200843071. According to the flexible substrate of the above embodiment, since the total surface area of the plurality of wiring patterns is in the range of 50 to 90% of the area of one surface of the substrate, the surface of one of the substrates can be large. Partially used as an area to help dissipate heat In the flexible substrate according to the embodiment, the plurality of wiring patterns formed so that the ratio of the width of the wiring pattern to the interval between the wiring patterns is more than 1 and not more than 8·7 or less have a fan-out structure. . According to the flexible substrate of the above-described embodiment, since the plurality of wiring patterns formed so that the ratio exceeds j and is 8.7 or less has a fan-out structure, the connection between the wiring pattern and the external device is easy. In the flexible substrate according to the embodiment, all of the regions other than the semiconductor wafer mounting region of the one surface of the substrate are the metal pig pattern forming regions. According to the flexible substrate of the above embodiment, since all of the regions other than the semiconductor wafer mounting region on the surface of the substrate are metal box pattern forming regions, the region contributing to heat dissipation can be increased. In the flexible substrate of the conventional embodiment, a bottom pattern formed of a metal foil is formed in the metal foil pattern forming region. According to the flexible substrate of the above-described embodiment, since the underlying pattern formed of the metal foil is formed in the metal box pattern forming region, the heat dissipation effect can be further improved by the heat dissipation effect of the wiring pattern and the underlying pattern. In the flexible substrate of one embodiment, at least a portion of the underlying pattern crosses the semiconductor wafer mounting region. 128294.doc -10- 200843071 According to the flexible substrate of the above embodiment, when the semiconductor wafer is mounted on the semiconductor wafer mounting region, at least a portion of the underlying pattern crosses the semiconductor wafer mounting region, thereby increasing the underlying pattern and the semiconductor wafer. The contact area can efficiently transfer heat from the semiconductor wafer to the underlying pattern, thereby preventing the semiconductor wafer from malfunctioning due to heat. In a flexible substrate in which the form is formed, a hole is formed in the underlying pattern. According to the flexible substrate of the above embodiment, since the hole is formed in the underlying pattern, the surface area of the underlying pattern is increased, and the heat dissipation effect of the underlying pattern can be improved. In the flexible substrate of one embodiment, the holes have a singular or plural number, and the holes have a rectangular shape in plan view, and when the holes have a plurality of holes, the plurality of holes are arranged to be arranged in parallel with the short side of the rectangle. In the direction. According to the flexible substrate of the above embodiment, since the hole has a plurality of turns, the plurality of holes are arranged in a direction parallel to the short side of the rectangle, so that the number of holes can be increased. In the flexible substrate according to the embodiment, the holes have a single number or a plurality of holes, and the hole has a circular or polygonal shape in plan view, and when the holes have a plurality of holes, the plurality of holes are arranged in a matrix. According to the flexible substrate of the above embodiment, since the plurality of holes have a plurality of holes, the plurality of holes are arranged in a matrix, so that the number of holes can be increased. In the flexible substrate of the embodiment, the surface area of the plurality of 128294.doc -11 - 200843071 wiring patterns and the surface area of the underlying pattern including the side surface area of the hole are the same as the planar substrate. The area of one surface described above is in the range of 50 to 90%. According to the flexible substrate of the above embodiment, the total surface area of the plurality of wiring patterns and the surface area of the underlying pattern including the side surface area of the hole is 5 〇 to 9 面积 of the surface area of the substrate. Within the range of %, most of the surface of one of the substrates can be used as an area that contributes to heat dissipation. In the flexible substrate according to the embodiment, the hole is a position alignment mark for aligning the semiconductor wafer mounted on the semiconductor wafer mounting region with the semiconductor wafer mounting region. According to the flexible substrate of the above-described embodiment, since the hole is used to position the semiconductor wafer mounted on the semiconductor wafer mounting region with the semiconductor wafer mounting region, the alignment mark can be omitted. To prevent an increase in manufacturing steps. A semiconductor device according to the present invention includes: the flexible substrate of the present invention; and a semiconductor wafer mounted on the semiconductor wafer mounting region and connected to the plurality of wiring patterns. According to the semiconductor device of the above configuration, since the heat dissipation of the usable substrate can be improved, it is possible to prevent the semiconductor wafer from malfunctioning due to heat. [Effects of the Invention] In the flexible substrate of the present invention, the ratio of the width of the wiring pattern to the interval between the wiring patterns 128294.doc -12- 200843071 is exceeded in at least a part of the metal formation region. 1 and a plurality of wiring patterns are formed in a manner of 8.7 or less. Therefore, the surface area of the wiring pattern is increased, and the heat dissipation effect of the wiring pattern can be improved, and as a result, heat dissipation can be improved. Further, since the heat dissipation property of the flexible substrate can be improved, for example, the underlying pattern formed in the metal falling pattern forming region can be reduced, or the underlying pattern can be removed, the flexible substrate can be miniaturized.
又，上述配線圖案，由於可藉由既存技術之金屬落光钮 刻步驟形成，故可藉由現有之設備進行即時大量生產。 又，由於可以不使用上述配線圖案以外之特別的散熱零 件，故亦沒有基於該散熱零件之規格限制、品質、成本i 升專風險問題。 由上述可明瞭，本發明之可撓基板應用於例如液晶顯示 器等上，對於提高性能、品質、價格等之競爭力很有幫 助。 本發明之半導體裝置，由於可改善可撓基板之散熱性， 故可防止半導體晶片由於熱而產生之故障。 【貫施方式】 以下’藉由圖示之實施形態對本發明之可撓基板及半導 體裝置進行詳細說明。 (第1實施形態） 圖1係顯示從上方看本發明第1實施形態之可撓基板1之 概略圖。 上述可撓基板1，係具有由厚度40 μπι之聚醯亞胺薄膜構 成之基材3、及形成於該基材3上面且由厚度8 μιη之銅箔 128294.doc •13- 200843071 構成之配線圖案2的COF(薄膜覆晶）用可撓基板。又，上述 基材3之上面係基材之一表面之一例，上述銅箔為金屬箔 之一例。 上述基材3之上面，包括搭載後述之半導體晶片9之半導 體晶片搭載區域8、及形成有配線圖案2及複數個底層圖案 5、6、7之金屬箔圖案形成區域4。即，上述基材3之上面 中之半導體晶片搭載區域8以外之區域，全部為金屬爷圖 案形成區域4。 (' 上述配線圖案102，具有内引線1 2、輸出外引線丨3及牵 引配線15。 上述底層圖案5、6、7亦與配線圖案2相同，由作為金屬 箔之一例之銅箔形成。 圖2係顯示圖1之框〇:之放大圖。 先前，考慮到蝕刻殘留、藉由蝕刻殘留之移動等配線彼 此間接近之危險、與缺少圖案及電流容量降低等因細線化 Q 之風險的平衡，配線圖案寬度與配線圖案彼此間之間隔設 為 1 : 1 〇 相對於此，在本第1實施形態中，於金屬箔圖案形成區 域4之一部分上，以配線圖案2之寬度界相對於配線圖案2 彼此間之間隔D的比率為超過1且在8.7以下之方式，形成 複數個配線圖案2。具體言之，上述配線圖案2之寬度w為 260 μηι，配線圖案2彼此間之間隔d為30 μπι，配線圖案2 之寬度W除以配線圖案2彼此間之間隔D的值約為8.7。 在本第1實施形態中，散熱方法係基於輸入輸出於半導 128294.doc -14- 200843071 體晶片9之配線圖案2本身者，當然，由於配線圖案2之表 面積越大者可以有助於半導體晶片9之散熱，故作為其條 件，本發明者發現當配線圖案2之寬度w與配線圖案2彼此 間之間隔D之比率（配線寬度/配線間隔）為超過丨且在8·7以 下時’散熱效果以X=1.011 8之1次函數增加。 簡而&之，在對於上述半導體晶片9輸入輸出信號之配 線圖案2中，配線圖案2之寬度w除以配線圖案2彼此間之 間隔D的值為超過1且在8·7以下時，與其他比率相比，散 熱效率變高。 又，不僅上述框α内之配線圖案2，在框α外相互平行之 複數個配線圖案2中，亦以配線圖案2之寬度w除以配線圖 案2彼此間之間隔D的值為超過1且在8·7以下之方式形成。 又’在本第1實施形態中，上述複數個配線圖案2之表面 積與底層圖案5、6、7之表面積的合計，為基材3之上面之 面積的55.5%。 另外’在本發明者之實驗中，配線圖案2之寬度W除以 配線圖案2彼此間之間隔d的值為超過1且在8.7以下時，該 配線圖案2之表面積之合計為基材3之上面之面積的 5 0〜90%。反而言之，為實現上述配線圖案2之基材上面佔 有率50〜90% ’在電氣特性允許之範圍内最好配置底層圖 案5、6、7。即使存在配線圖案2之寬度w除以配線圖案2 彼此間之間隔D的值無法為超過1且在8.7以下之部分，亦 可藉由在該部分上配置底層圖案5、6、7，使上述部分取 得與配線圖案2之寬度W除以配線圖案2彼此間之間隔d的 128294.doc -15- 200843071 值為超過1且在8.7以下之部分同等之效果。 當然，若銅箔面積相對上述可撓基板丨之上面之全面積 的比例為50〜90%，以散熱之觀點來看，可最大限度地有 效使用可撓基板1之上面之面積，可同時改善可撓基板i之 散熱性與使可撓基板1小型化。 圖3係顯示從圖1之ΠΙ_ΙΠ所見之概略截面圖。 - 於上述半導體晶片9之下面（可撓基板1側之表面）形成有 複數個突起電極10。該半導體晶片9之下面之形狀為長方 形。即，上述半導體晶片9為長方體形狀。 上述底層圖案7之一部分橫切半導體晶片搭載區域8。在 杈切該半導體晶片搭載區域8之底層圖案7之一部分連接突 起電極1 0。 由於上述半導體晶片9之中央部離外面空氣最遠，故散 2困難。然而由於在半導體晶片9之下面之長邊附近配置 突起電極10，故不能將配線圖案2從半導體晶片9之中央部 L 拉出。因此，上述底層圖案7之一部分以橫切半導體晶片 搭載區域8之形狀，將突起電極1〇連接於該底層圖案7之一 冑分。藉此，可取得積極將上述半導體晶片9中央部之教 導至外部之熱路徑。 i述底層圖案7 ’由配置於半導體晶片9下面之短邊兩側 之邛刀、與杈切半導體晶片搭載區域8之部分構成。又， -;上述半$體晶片9下面短邊兩側之部分與橫切半導 體晶片搭載區域8之部分被—體化，形成—個时、。 上述突起電極Π)主要沿半導體晶片9下面長邊而配置於 128294.doc -16- 200843071 一直線上，連接於突起電極1〇之内引線12則以在基材3上 直線前進之形態從半導體晶片搭載區域8處拉出，形成為 重複著配線-間隙-配線之條紋狀圖案。 又，上述輸出外引線13，例如連接於液晶面板之電極， 該電極成重複著端子-間隙-端子之梳齒狀。因此，上述輸 出外引線13亦成為與液晶面板之電極形狀相配合之條紋狀 圖案。 又，連結上述内引線12與輸出外引線13之牵引配線15亦 成條紋狀。 上述牵引配線1 5，以牵引配線丨5之寬度除以牵引配線i 5 彼此間之間隔的值為超過1且在8 · 7以下之方式形成。 上述内引線12，以内引線12之寬度除以内引線12彼此間 之間隔的值為超過1且在8 · 7以下之方式形成。 上述輸出外引線1 3，以輸出外引線丨3之寬度除以輸出外 引線13彼此間之間隔的值為超過1且在心7以下之方式形 成。 在上述第1實施形態中，係在金屬箔圖案形成區域4之一 部分，以配線圖案2之寬度W相對於配線圖案2彼此間之間 隔D的比率為超過丨且在8·7以下之方式，形成複數個配線 圖案2 ’但亦可在所有金屬箔圖案形成區域4，以配線圖案 2之寬度W相對於配線圖案2彼此間之間隔〇的比率為超過1 且在8 · 7以下之方式，形成複數個配線圖案2。 在上述第1實施形態中，於金屬箔圖案形成區域4形成複 數個底層圖案5、6、7，然而於金屬箔圖案形成區域4不形 128294.doc -17 - 200843071 成複數個底層圖案5、6、7亦可。 於上述金屬蕩圖案形成區域4未形成複數個底層圖案5、 6、7時，則複數個配線圖案2之表面積之合計在基材3上面 面積之50〜90%之範圍内亦可。 、，在上述第1實施形態中，沒有以配線圖案2之一部分橫切 半導體晶片搭載區域8之方式形成配線圖案2，然而，亦可 以配線圖案之一部分橫切半導體晶片搭載區域 成配線圖案。 1 ^ 在以上述配線圖案之-部分橫切半導體晶片搭載區域8 之方式形成配線圖㈣，配線圖案之—部分橫切半導體晶 片搭載區域8之方向，既可為半導體晶片9下面之長向，亦 可為半導體晶片9下面之短向。 在上述第1實施形態中，於金屬箔圖案形成區域4形成銅 治，然而於金屬箔圖案形成區域4亦可形成銅箔以外之金 屬I即’可將由㈣以外之金屬構成之配線圖案與銅 泊以外之金屬箱構成之底層_案形成於金屬帛圖案形成區 域4上。 (第2實施形態） 圖4係顯示從上方看本發明第2實施形態之可換基板21之 概略圖。X，圖4中，與圖！所示之^實施形態之構成部 相同之構成部，附上與圖丨之構成部相同之參照符號而省 略說明。 上述可撓基板21之半導體晶片搭载區域8上，與上述第工 實施形態相同’搭載有圖3之半導體晶片9。 128294.doc -18- 200843071 孰可挽基板21中’配線圖案2之表面積越大，對散 利，然而為了在有限區域内儘量增大表面積，在底 曰圖木25上形成孔5〇，在底声圖安 一 牡低層圖案26上形成孔51，在 圖案27上形成孔52、53。 -曰 上述孔50形成複數個，各孔5〇之平面視之形狀為長方 形。该專複數個孔50配置為排列於與該長方形之短邊平行 之方向上。 上述孔51形成複數個，各孔51之平面視之形 形。該等複數個孔51配置為矩陣狀。 ，〜角 上述孔52形成複數個，各孔52之平面視之形狀為十字 形。該等複數個孔52配置為夹住半導體晶片搭载區域8。 即，在上述半導體晶片搭載區域8之兩側形成孔Μ。节孔 52亦兼具用於使半導體晶片9與半導體晶片搭載區域^ 位置對準之位置對準標記。 述孔53形成複數個’各孔53之平面視之形狀為圓形。 该等複數個孔5 3配置於非直線狀上。 成為 52、 為基 51 λ 除了上述孔52外，孔50、51、53之深度均為6 不貝牙底層圖案25、26、27之銅箔之孔。 上述複數個配線圖案2之表面積與包括孔5〇、5 1 53側面面積之底層圖案25、26、27之表面積的合計 材3上面面積之56.6%。 如此，由於上述底層圖案25、26、27上形成孔5〇 ^ 52、53，故與上述第！實施形態相比，可增加鋼箔之表面 積’進一步提高散熱性。 128294.doc -19- 200843071 在上述第2實施形態中，孔50、5 1、53分別形成有複數 個，然而孔50、51、53分別為〗個亦可。 在上述第2實施形態中，在底層圖案26上形成複數個平 面視之形狀為三角形之孔5〗，然而在底層圖案26上形成單 數或複數個平面視之形狀為三角形以外之多邊形孔亦可。 在上述第2實施形態中，複數個孔53配置於非直線狀 上，然而複數個孔53配置為矩陣狀亦可。 在上述第2實施形態中，孔5〇、51、53均不貫穿底層圖 案25、26、27之銅箔，然而孔5〇、51、53之至少一者貫穿 底層圖案25、26、27之銅箔而抵達於基材3之上面亦可。 在上述第2實施形態中，上述複數個配線圖案2之表面積 與包括孔5G、51、52、53側面面積之底層圖案25、26、27 之表面積的合計，為基材3上面面積之56·6%，然而在 56.6%以外亦可，只要在基材3上面面積之5〇〜9〇%之範圍 内即可。 本發明亦可為整合上述第丨實施形態所述内容與上述第2 實施形態所述内容者。 【圖式簡單說明】 圖1係本發明之第1實施形態之可撓基板之概略平面圖。 圖2係圖1之框之放大圖。 ° 圖3係圖1之ιπ-πΐ線箭頭方向之概略截面圖。 圖4係本發明之第2貫施形態之可撓基板之概略平面囷 圖5係先前可撓基板之概略平面圖。 ° 圖6係先前半導體裝置之要部之概略立體圖。 128294.doc -20- 200843071 【主要元件符號說明】 1、21 可撓基板 2 配線圖案 3 基材 4 金屬箔圖案形成區域 5 、 6 、 7 、 25 、 26 、 27 底層圖案 8 半導體晶片搭載區域 9 半導體晶片 10 突起電極 50 、 51 、 52 、 53 D 配線圖案彼此間之間隔 W 配線圖案之寬度 128294.doc -21 -Further, since the wiring pattern can be formed by the metal falling-lighting step of the prior art, it can be mass-produced in real time by the existing equipment. Further, since it is possible to eliminate the need for special heat dissipating components other than the wiring pattern described above, there is no specific risk limitation based on the specification, quality, and cost of the heat dissipating component. As apparent from the above, the flexible substrate of the present invention is applied to, for example, a liquid crystal display device, and is useful for improving the competitiveness of performance, quality, price, and the like. In the semiconductor device of the present invention, since the heat dissipation property of the flexible substrate can be improved, the failure of the semiconductor wafer due to heat can be prevented. [Complex] Hereinafter, the flexible substrate and the semiconductor device of the present invention will be described in detail by way of the embodiments shown in the drawings. (First Embodiment) Fig. 1 is a schematic view showing a flexible substrate 1 according to a first embodiment of the present invention as seen from above. The flexible substrate 1 has a substrate 3 composed of a polyimide film having a thickness of 40 μm, and a wiring formed on the substrate 3 and having a thickness of 8 μm of copper foil 128294.doc • 13-200843071. A flexible substrate for COF (film overmolding) of pattern 2. Further, as an example of the surface of one of the upper substrate of the substrate 3, the copper foil is an example of a metal foil. The upper surface of the substrate 3 includes a semiconductor wafer mounting region 8 on which a semiconductor wafer 9 to be described later is mounted, and a metal foil pattern forming region 4 in which a wiring pattern 2 and a plurality of underlying patterns 5, 6, and 7 are formed. That is, all of the regions other than the semiconductor wafer mounting region 8 on the upper surface of the substrate 3 are the metal pattern forming regions 4. ('The wiring pattern 102 has the inner lead 12, the output outer lead 丨3, and the traction wiring 15. The above-described underlying patterns 5, 6, and 7 are also formed of a copper foil which is an example of a metal foil, similarly to the wiring pattern 2. 2 shows an enlarged view of the frame of Fig. 1. Previously, the risk of thinning Q due to the danger of close contact between the etching residue and the movement of the etching residue, and the lack of pattern and current capacity reduction are considered. The interval between the width of the wiring pattern and the wiring pattern is set to 1:1. In the first embodiment, the width of the wiring pattern 2 is opposite to the wiring in one portion of the metal foil pattern forming region 4. A plurality of wiring patterns 2 are formed so that the ratio of the interval D between the patterns 2 is more than 1 and not more than 8.7. Specifically, the width w of the wiring pattern 2 is 260 μm, and the interval d between the wiring patterns 2 is 30 μπι, the width W of the wiring pattern 2 divided by the interval D between the wiring patterns 2 is about 8.7. In the first embodiment, the heat dissipation method is based on input and output in the semi-conductive 128294.doc -14-20084307 The wiring pattern 2 of the bulk wafer 9 itself, of course, can contribute to the heat dissipation of the semiconductor wafer 9 because the surface area of the wiring pattern 2 is larger. Therefore, the inventors found that the width w and the wiring of the wiring pattern 2 are found. When the ratio of the interval D between the patterns 2 (wiring width/wiring interval) is more than 丨 and below 8·7, the heat dissipation effect is increased by a linear function of X=1.011 8 . Simple and < In the wiring pattern 2 in which the output signal of the wafer 9 is input, the width w of the wiring pattern 2 divided by the value of the interval D between the wiring patterns 2 exceeds 1 and is less than or equal to or less than 8.7%, and the heat dissipation efficiency is higher than other ratios. Further, not only the wiring pattern 2 in the frame α but also the plurality of wiring patterns 2 which are parallel to each other outside the frame α, the width w of the wiring pattern 2 divided by the interval D between the wiring patterns 2 exceeds 1 Further, in the first embodiment, the total surface area of the plurality of wiring patterns 2 and the surface areas of the underlying patterns 5, 6, and 7 are the areas of the upper surface of the substrate 3. 55.5%. Also 'in the inventor In the experiment, when the width W of the wiring pattern 2 is divided by the value of the interval d between the wiring patterns 2 to be more than 1 and not more than 8.7, the total surface area of the wiring pattern 2 is 50 of the area of the upper surface of the substrate 3. ～90%. Conversely, in order to realize the above-mentioned wiring pattern 2, the substrate occupation ratio is 50 to 90%. The primer patterns 5, 6, and 7 are preferably disposed within the range of electrical characteristics. Even if the width of the wiring pattern 2 is present. The value of the interval D between the w and the wiring patterns 2 cannot be more than 1 and is less than 8.7, and the underlying patterns 5, 6, and 7 may be disposed on the portion to make the portion and the wiring pattern 2 The width W is divided by the interval d between the wiring patterns 2, and the value of 128294.doc -15-200843071 is equal to or greater than 1 and equal to or less than 8.7. Of course, if the ratio of the area of the copper foil to the total area of the upper surface of the flexible substrate is 50 to 90%, the area above the flexible substrate 1 can be used to the maximum extent, and the surface area can be improved simultaneously. The heat dissipation of the flexible substrate i and the miniaturization of the flexible substrate 1 are achieved. Fig. 3 is a schematic cross-sectional view seen from Fig. 1 of Fig. 1. A plurality of bump electrodes 10 are formed on the lower surface of the semiconductor wafer 9 (the surface on the side of the flexible substrate 1). The shape of the underside of the semiconductor wafer 9 is a rectangular shape. That is, the semiconductor wafer 9 has a rectangular parallelepiped shape. One of the above-described underlying patterns 7 is transverse to the semiconductor wafer mounting region 8. The protruding electrode 10 is connected to a portion of the underlying pattern 7 of the semiconductor wafer mounting region 8. Since the central portion of the semiconductor wafer 9 is farthest from the outside air, it is difficult to disperse. However, since the bump electrode 10 is disposed in the vicinity of the long side of the lower surface of the semiconductor wafer 9, the wiring pattern 2 cannot be pulled out from the central portion L of the semiconductor wafer 9. Therefore, one portion of the underlying pattern 7 is formed to cross the semiconductor wafer mounting region 8 to connect the bump electrode 1 to one of the underlying patterns 7. Thereby, a heat path for actively guiding the central portion of the semiconductor wafer 9 to the outside can be obtained. The underlayer pattern 7' is composed of a trowel disposed on both sides of the short side of the lower surface of the semiconductor wafer 9, and a portion of the diced semiconductor wafer mounting region 8. Further, - a portion on both sides of the short side of the lower half of the body wafer 9 and a portion which is transverse to the semiconductor wafer mounting region 8 are formed into a single body. The bump electrode Π) is disposed along the long side of the lower surface of the semiconductor wafer 9 on the straight line 128829.doc -16-200843071, and the inner lead 12 connected to the bump electrode 1 is linearly advanced from the semiconductor wafer. The mounting area 8 is pulled out and formed into a stripe pattern in which wiring-gap-wiring is repeated. Further, the output outer lead 13 is connected, for example, to an electrode of the liquid crystal panel, and the electrode is formed in a comb-tooth shape in which the terminal-gap-terminal is repeated. Therefore, the output outer lead 13 also has a stripe pattern matching the shape of the electrode of the liquid crystal panel. Further, the traction wires 15 connecting the inner leads 12 and the output outer leads 13 are also stripe-like. The traction wiring 15 is formed such that the width of the traction wiring bundle 5 divided by the distance between the traction wires i 5 is more than 1 and not more than 8.7. The inner lead 12 is formed such that the width of the inner lead 12 divided by the distance between the inner leads 12 is more than 1 and not more than 8.7. The output outer lead 13 is formed such that the width of the output outer lead 丨3 divided by the distance between the output outer leads 13 exceeds 1 and is equal to or less than the core 7. In the first embodiment, in a portion of the metal foil pattern forming region 4, the ratio of the width W of the wiring pattern 2 to the interval D between the wiring patterns 2 is more than 丨 and not more than 8·7. A plurality of wiring patterns 2' are formed, but in all the metal foil pattern forming regions 4, the ratio of the width W of the wiring pattern 2 to the interval 〇 between the wiring patterns 2 is more than 1 and not more than 8.7. A plurality of wiring patterns 2 are formed. In the above-described first embodiment, a plurality of underlying patterns 5, 6, and 7 are formed in the metal foil pattern forming region 4, but in the metal foil pattern forming region 4, 128294.doc -17 - 200843071 is formed into a plurality of underlying patterns 5, 6, 7 can also. When a plurality of underlayer patterns 5, 6, and 7 are not formed in the metal pattern forming region 4, the total surface area of the plurality of wiring patterns 2 may be in the range of 50 to 90% of the area of the upper surface of the substrate 3. In the first embodiment, the wiring pattern 2 is not formed so that one portion of the wiring pattern 2 crosses the semiconductor wafer mounting region 8. However, one of the wiring patterns may be transverse to the semiconductor wafer mounting region to form a wiring pattern. 1 ^ A wiring pattern (4) is formed so as to cross the semiconductor wafer mounting region 8 at a portion of the wiring pattern, and a portion of the wiring pattern transverse to the semiconductor wafer mounting region 8 may be a long direction under the semiconductor wafer 9. It may also be a short direction under the semiconductor wafer 9. In the first embodiment, the copper foil is formed in the metal foil pattern forming region 4. However, in the metal foil pattern forming region 4, the metal I other than the copper foil, that is, the wiring pattern which can be formed of a metal other than the (four) and copper can be formed. The bottom layer of the metal case other than the poise is formed on the metal ruthenium pattern forming region 4. (Second Embodiment) Fig. 4 is a schematic view showing a replaceable substrate 21 according to a second embodiment of the present invention as seen from above. X, in Figure 4, and the figure! The components that are the same as those of the components of the embodiment are denoted by the same reference numerals as the components of the drawings, and the description thereof will be omitted. The semiconductor wafer mounting region 8 of the flexible substrate 21 is the same as that of the above-described embodiment, and the semiconductor wafer 9 of Fig. 3 is mounted. 128294.doc -18- 200843071 The larger the surface area of the wiring pattern 2 in the 孰pable substrate 21, the greater the surface area, but in order to maximize the surface area in a limited area, a hole 5 形成 is formed on the bottom raft 25 A hole 51 is formed in the lower layer pattern 26 of the bottom acoustic pattern, and holes 52, 53 are formed in the pattern 27. - The plurality of holes 50 are formed in a plurality of shapes, and the shape of each of the holes 5 is a rectangular shape. The plurality of holes 50 are arranged to be arranged in a direction parallel to the short sides of the rectangle. The holes 51 are formed in plural, and the planes of the holes 51 are formed in a plan view. The plurality of holes 51 are arranged in a matrix. , the angle of the hole 52 is formed in plural, and the shape of each of the holes 52 is a cross shape. The plurality of holes 52 are arranged to sandwich the semiconductor wafer mounting region 8. That is, the holes are formed on both sides of the semiconductor wafer mounting region 8. The pitch holes 52 also have position alignment marks for aligning the semiconductor wafer 9 with the semiconductor wafer mounting region. The apertures 53 form a plurality of 'each aperture 53' having a circular shape in plan view. The plurality of holes 5 3 are arranged in a non-linear shape. 52 is the base 51 λ except for the hole 52 described above, the depth of the holes 50, 51, 53 is 6 holes of the copper foil of the bottom layer patterns 25, 26, and 27. The surface area of the plurality of wiring patterns 2 is 56.6% of the area of the upper surface of the composite material 3 including the surface areas of the bottom patterns 25, 26, and 27 of the side areas of the holes 5, 5, 53. Thus, since the holes 5〇, 52, and 53 are formed in the above-described bottom patterns 25, 26, and 27, the above-mentioned first! In comparison with the embodiment, the surface area of the steel foil can be increased to further improve heat dissipation. 128294.doc -19- 200843071 In the second embodiment described above, a plurality of holes 50, 51, and 53 are formed, respectively, but the holes 50, 51, and 53 may be respectively. In the second embodiment, a plurality of holes 5 having a triangular shape in plan view are formed on the bottom pattern 26. However, a singular or a plurality of polygonal holes having a planar shape other than a triangle may be formed on the bottom pattern 26. . In the second embodiment, the plurality of holes 53 are arranged in a non-linear shape, but the plurality of holes 53 may be arranged in a matrix. In the second embodiment, the holes 5, 51, and 53 do not penetrate the copper foil of the underlying patterns 25, 26, and 27, but at least one of the holes 5, 51, and 53 penetrates the underlying patterns 25, 26, and 27 The copper foil may reach above the substrate 3. In the second embodiment, the total surface area of the plurality of wiring patterns 2 and the surface areas of the underlying patterns 25, 26, and 27 including the side surfaces of the holes 5G, 51, 52, and 53 are 56. 6%, however, may be other than 56.6%, as long as it is within the range of 5 〇 to 9 〇% of the area of the substrate 3. The present invention may be integrated with the contents described in the above-described second embodiment and the contents described in the second embodiment. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic plan view showing a flexible substrate according to a first embodiment of the present invention. Figure 2 is an enlarged view of the frame of Figure 1. Figure 3 is a schematic cross-sectional view of the direction of the iππ-πΐ line arrow of Figure 1. Fig. 4 is a schematic plan view of a flexible substrate according to a second embodiment of the present invention. Fig. 5 is a schematic plan view of a prior flexible substrate. ° Figure 6 is a schematic perspective view of the main part of the prior semiconductor device. 128294.doc -20- 200843071 [Description of main component symbols] 1. 21 Flexible substrate 2 Wiring pattern 3 Substrate 4 Metal foil pattern forming region 5, 6, 7, 25, 26, 27 Underlying pattern 8 Semiconductor wafer mounting area 9 Semiconductor wafer 10 bump electrodes 50, 51, 52, 53 D spacing between wiring patterns W width of wiring pattern 128294.doc -21 -