JP3446818B2 - Semiconductor device mounting structure and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure in which an IC chip is mounted face down on a heat conductive circuit board through an anisotropic conductive film, and particularly, the IC chip can be mounted on the circuit board at low cost. The present invention relates to a mounting structure of a semiconductor device and a manufacturing method thereof, which can ensure electrical connection of an IC chip and can efficiently dissipate heat generated in the IC chip.

[0002]

2. Description of the Related Art The miniaturization manufacturing technology of semiconductor integrated circuit chips has made remarkable progress. As a result, the chip size has been reduced and the integration of circuits has been increased rapidly, and the operating speed of the IC has also been improved. Therefore, large-scale central processing chips operating with a high-frequency clock signal have appeared. On the other hand, a driving IC chip that can simultaneously drive a large number of loads such as those found in a matrix electrode of a liquid crystal display or a plasma display panel at high speed has appeared. It is an industrially great advantage that complicated signal processing can be performed easily and at low cost by these ICs. However, the following two points have been studied as problems common to these IC chips.

The first problem is that as the number of input / output terminals of the chip has increased due to the increase in the scale of processing functions, the pitch of the electrical connection pads has become narrower, and a connection technology adapted to this has become necessary. It has become. The second problem is that the internal power consumption per unit area of the IC chip has increased due to high-speed operation and driving of a large capacity load, so that a mounting technique for efficiently dissipating the self-heating amount of the chip is required. That is. In particular, recently, it is not uncommon for individual IC chips to consume power of several watts to several tens of watts, and it is considered that the heat dissipation problem will become more and more apparent in the future.

Looking at the mounting structure of the IC chip, a conventional chip package has been developed into a bare chip mounting capable of higher density mounting. Further, in the bare chip mounting as well, regarding the method of electrically connecting the IC chip and the circuit board, instead of individual connection by wire bonding between both terminals, face-down mounting of the IC chip is performed to make all connections on the circuit board side. A method has been developed in which the connection pad and the connection pad on the IC side are connected together. Conventionally, such a collective connection method has dealt with the narrowing of the pitch of the above-mentioned electrical connection pads.

On the other hand, regarding self-heating of the IC chip,
In the past, heat was dissipated by externally attaching a heat dissipation plate to the back surface of the chip mounted face down, so that it was required that the substrate material of the IC chip had high thermal conductivity. When the substrate material of the IC chip is single crystal silicon, the single crystal silicon is about 170 W / (mK).
Since it shows high thermal conductivity, there is no problem to be noted.

However, an IC of a single crystal silicon substrate
Since the cost of the manufacturing process of the IC chip becomes high in the case of the chip, if a material having low thermal conductivity is used as the substrate material in order to eliminate such a disadvantage, this will cause a problem in heat dissipation. As an example, Japanese Patent Application Laid-Open No. 7-333645 discloses an example in which a glass substrate having low thermal conductivity is used as a substrate material. This is to reduce the manufacturing cost by mounting an IC chip, which constitutes a drive circuit formed of a polycrystalline silicon thin film transistor on a glass substrate, face down on the liquid crystal display panel formed on the glass substrate as a drive circuit. It was an invention aimed at. The IC chip having such a configuration can reduce the cost of the IC chip because a polycrystalline silicon thin film transistor can be formed on a glass substrate that is cheaper than single crystal silicon and can have a large area with fewer manufacturing steps. It has the feature that However, when this method is adopted, there is a problem in heat dissipation as described above.
That is, the thermal conductivity on the side of the IC substrate or the liquid crystal display panel is about 1 W / (m · K), which is 1/100 or less of the thermal conductivity of the single crystal silicon. Because almost no heat is dissipated. Since the temperature of the drive circuit in the IC chip rises extremely, eventually aluminum wiring is melted or impurities are thermally diffused into the channel region of the transistor.
Eventually, it leads to malfunction.

For the above reasons, when an IC chip using a substrate material having low heat conductivity is mounted face down,
Rather than attaching a heat sink to the back surface of the IC chip, by forming the circuit board with a material having high thermal conductivity such as metal or ceramics, the heat generated in the IC is mainly conducted to the circuit board side to be radiated. There is a need. Therefore, the smaller the distance between the IC chip and the circuit board, the better the heat conduction to the circuit board side. When the IC chip is mounted face down, there is a method of electrically connecting the connection pads of both the circuit board and the IC chip via bumps such as solder or gold. However, a bumpless connection method has been devised in which an anisotropic conductive film is used instead of bumps to connect between opposing connection pads. In this method, the distance between the IC chip and the circuit board must be reduced. Therefore, the thermal conductivity is improved, and since it is not necessary to perform a bump forming process on the IC chip side, the process can be shortened as compared with the connection method using bumps, which is advantageous in that the cost is low.

FIG. 8 shows a conventional IC according to the bumpless connection system disclosed in Japanese Patent Laid-Open No. 60-225438.
It is a mounting structure figure. In the figure, a wiring pattern 103 is formed on the circuit board 101, and a part of the wiring pattern 103 serves as a pad for electrical connection with the IC chip 106. An aluminum pad (not shown) for connection is arranged at a position facing the wiring pattern 103 on the circuit formation surface of the IC chip 106. Then, the IC chip 106 is mounted face down on the circuit board 101 via the anisotropic conductive film 107. The anisotropic conductive film 107 is a mixture of a binder material made of an epoxy resin and the like or conductive particles made of a metal or a composite material such as a resin. Anisotropic conductive film 1
The IC chip 106 and the circuit board 101 sandwiching 07
By thermocompression bonding to each other at a temperature of about 50 to 180 ° C., the resin in the anisotropic conductive film 107 is eluted, and the conductive particles are electrically connected between the opposing pads. A similar example is also disclosed in JP-A-61-186061.

By the way, since the IC chip which operates at high speed and has large self-heating as described above has a large operating current, a voltage drop due to the resistance component of the wiring pattern of the circuit board becomes a problem, which causes an IC malfunction. Cause of. In order to avoid such a voltage drop, it is effective to increase the sectional area of the wiring pattern. However, as the number of terminals increases due to higher integration and higher functionality of ICs, it becomes difficult to make the wiring thick. Therefore,
It is possible to reduce the resistance by increasing the thickness of the wiring layer.

In order to increase the thickness of the wiring layer, a copper foil having a low electric resistance and a low migration is generally used for the wiring pattern of the circuit board. There are various known methods for forming copper foil wiring, but since the copper foil is considerably thicker in the subtraction method in which the copper foil attached to the substrate is etched, a pattern that can be used for fine patterning of bare chip mounting Cannot be formed. An additive method is known as a method for eliminating such a disadvantage, and in this case, copper foil wiring is formed on a circuit board material by a plating process. Above all, an electrolytic plating method is generally used to form a copper foil wiring having a predetermined pitch and a fine pitch. This is largely because the plating rate is high and the stability of the plating bath is good, and industrial advantages are great. In the electroplating method, a voltage is applied between a thin copper foil wiring pattern formed beforehand on the circuit board by the sputtering method and a copper plate electrode provided separately from the circuit board, and these are immersed in an aqueous copper sulfate solution. Copper is deposited and plated on the surface of the copper foil wiring pattern.

However, using this method, the conventional I of FIG.
When trying to realize the C mounting structure, the wiring pattern 10
Since the electric field suddenly changes at the outer edge of the wiring pattern 103c located at the arrangement end of No. 3, the current during plating is concentrated. FIG. 10 shows E when the copper foil wiring formed on the circuit board 101 in FIG. 8 is formed by electrolytic plating.
It is an electric field distribution diagram in the vicinity of the copper foil wiring in the −E ′ cross section,
The contour lines in the figure represent the strength of the electric field 2 in that region. From the figure, it can be seen that an electric field that is four times as high as that in the other portions is concentrated especially on the outer edge of the wiring pattern 103c. In the case of the electrolytic plating method, the current density in the region where the electric field is strong becomes high and more copper is deposited on the surface of the copper foil, so that the copper foil at that portion becomes thicker.

FIG. 9 is a sectional view taken along the line EE 'of the conventional IC mounting structure shown in FIG. 8. The wiring pattern 103 has a sectional shape which is plated under the electric field distribution conditions shown in FIG. There is. According to it, the wiring pattern 103
Since the copper foil on the outer edge of c is extremely thick, even if the IC chip 106 is mounted via the anisotropic conductive film 107 and thermocompression bonding is performed, the wiring pattern 103a in the array intermediate portion of the wiring pattern 103 is formed. And 103b, there is a large gap between the aluminum pad on the IC chip 106 side and the connection pad on the circuit board 101 side. Therefore, the conductive particles 108 mixed in the anisotropic conductive film 107 float, and good electrical connection cannot be obtained. If this gap is small, it becomes possible to fill the gap with the conductive particles 108. However, particularly when trying to perform fine pitch connection, when the conductive particles 108 existing between the adjacent wiring patterns 103 continuously contact with each other, the wiring patterns 103 are electrically connected and cause a defect. Become. Since these conductive particles 108 are stochastically distributed in the binder material of the anisotropic conductive film 107, it is necessary to use the conductive particles 108 having a particle size sufficiently smaller than the distance between the adjacent wiring patterns 103 in design. There is. However, in this case, it becomes more difficult to fill the gap between the connection pad on the circuit board 101 side and the aluminum pad on the IC 106 side with the conductive particles 108, which causes a connection failure.

In order to solve such a problem, Japanese Patent Laid-Open No. 9-26
Japanese Patent No. 0579 discloses a terminal structure of a flexible wiring board and a mounting structure of an IC chip using the terminal structure. FIG. 11 is a particle structure diagram of a conventional flexible wiring board disclosed in Japanese Patent Laid-Open No. 9-260579. In this known example, the dummy terminals 204 are provided in the IC mounting region 202 with respect to the inner leads 203 formed on the base film 201 so as to eliminate the unevenness of the wiring pitch. When the inner lead 203 of the conventional flexible wiring board shown in FIG. 11 is formed by electrolytic plating, the inner lead 2
It was possible to prevent the metal foil at the edge portion facing the adjacent pattern in the vicinity of the pattern edge of No. 03 from becoming thick due to the electric field concentration.

[0014]

However, even in the terminal structure of the flexible wiring board and the mounting structure of the IC chip using the same disclosed in Japanese Patent Laid-Open No. 9-260579 mentioned above, the following problems are still encountered. was there. Referring to FIG. 11, the circuit pattern tip edge 210 in the IC mounting region 202 has a structure in which there is a space in the vicinity thereof, so that electrolytic concentration occurs at the circuit pattern tip edge 210 during electrolytic plating. There was a problem that the metal foil in this portion becomes thick. FIG. 12 is a cross-sectional view taken along line GG 'of the conventional circuit board of FIG. According to this, since the copper foil on the tip edge 210 of the inner lead 203 becomes extremely thick, when the IC chip 206 is mounted via the anisotropic conductive film 207 and thermocompression bonding is performed, the inner lead 203 is Its tip edge 2
Only 10 is electrically connected to the IC chip 206, and the conductive particles 208 in the anisotropic conductive film 207 float and cannot electrically contribute. Further, the thickness of the copper foil on the tip edge 210 of the inner lead 203 is different between the GG ′ cross section and the HH ′ cross section in FIG. 11. That is,
In the H-H 'cross section corresponding to the corner portion of the IC mounting area, there is a copper foil adjacent in the direction of an angle of 90 degrees, so that the electrolytic concentration is relaxed. As a result, the thickness of the copper foil at the tip edge 210 of the inner lead 203 in this region is
It is smaller than the area of the GG 'cross section. This gives I
In the vicinity of the corner of the C mounting area, the inner lead 20
There is a problem in that a gap is formed between the tip edge 210 of No. 3 and the IC chip 206, causing a poor electrical connection. Further, an epoxy resin as a binder material is present between the IC chip 206 and the heat conductive circuit board, and the thickness thereof is equivalent to the total thickness of the wiring pattern copper foil and the particle diameter of the conductive particles pressure-bonded. To do. The diameter of general conductive particles is 5μ
The thickness of the copper foil is about several tens of μm. However, the thermal conductivity of epoxy resin is 0.3-0.5 W /
Since it is as small as (m · K), the conventional mounting structure has a problem that the heat dissipation is insufficient for the heat generation amount of several watts to several tens of watts as seen in recent LSI chips. .

The present invention has been made in view of the above problems in the prior art, and improves heat dissipation from an IC chip, prevents malfunction of the semiconductor device, and improves operation reliability of the semiconductor device. It is an object of the present invention to provide a mounting structure of a semiconductor device and a manufacturing method thereof.

[0016]

According to a first invention of the present application for solving the above problems, an IC chip is bumplessly faced on a circuit board having a wiring pattern and a dummy pattern via an anisotropic conductive film. In a mounting structure of a semiconductor device down-mounted, the dummy pattern is at least
Part of the mounting area overlaps the mounting area of the IC chip,
The wiring pattern in the area is the wiring adjacent to the wiring pattern.
Make sure that the thickness of the pattern or dummy pattern is uniform.
The dummy pattern that overlaps the mounting area is
Of the active element region or the emitter formed on the IC chip
It is characterized in that it is arranged so as to face the heat region .

[0017] Thus, according to the mounting structure of the semiconductor device according to the first aspect of the invention, the dummy pattern in which an IC chip is disposed on the area already implemented, the distance between the wiring patterns adjacent to each within a predetermined value Since the current density in the pattern becomes uniform because it is installed so that the thickness of the metal foil (for example, copper foil) deposited on the pattern surface in the step of performing electrolytic plating is at least in the IC mounting area. There is an advantage that the patterns are arranged uniformly. Therefore, there is an advantage that it is possible to prevent connection failure caused by uneven pattern thickness, and the thickness of the pressure-bonded surface of the anisotropic conductive film to be thermo-compressed is reduced to a fraction of that of the conventional one, and the thickness from the IC chip to the circuit side is reduced. There is an advantage that heat dissipation is improved. Also, the predetermined value is
It means an interval for equalizing the current density in the vicinity of each surface of the layout of the wiring pattern and the dummy pattern during electrolytic plating.

Further, since the dummy pattern is arranged corresponding to the active element arrangement area or the heat generating area of the IC chip, the heat generated in the heat generating area can be effectively conducted to the circuit board. Therefore, there is an advantage that the thermal design margin of the IC chip is improved and the operation reliability of the semiconductor device is improved.

The second invention of the present application is that a substrate having an insulating film formed on a conductive substrate, that is, a thermally conductive insulating substrate,
A method of manufacturing a semiconductor device, wherein a wiring pattern is formed by an electrolytic plating process, and the IC chip is mounted face down on the wiring pattern via an anisotropic conductive film by bumpless mounting. In the included area
The wiring pattern and the dummy pattern are simultaneously formed
Together with the wiring pattern and the dummy pattern,
How to mount the IC chip during the electrolytic plating process
In the area, the wiring pattern and the dummy pattern
Are arranged so that the thickness of the
The pattern is the IC when the IC chip is mounted.
Facing the active element area or heat generating area formed on the chip
It is characterized by being arranged as follows.

Therefore, according to the method of manufacturing a semiconductor device of the second invention of the present application, during the electrolytic plating step, the IC
Since the wiring pattern and the dummy pattern are arranged so as to make the thicknesses of the wiring pattern and the dummy pattern uniform in the area where the chip is mounted, the electric field at the outer edge of the wiring pattern suddenly changes during electrolytic plating. Without this, the deposition of the metal foil is made uniform, and the pattern thickness is made uniform at least in the IC chip mounting region. Therefore, it is possible to prevent connection failure caused by uneven pattern thickness, the thickness of the anisotropic conductive film to be thermocompression bonded is a fraction of the conventional thickness, and the heat dissipation from the IC chip to the circuit board is improved. There are advantages.

Further, the dummy pattern is the IC chip.
Placed opposite the active element placement area or heat generation area
As a result, the heat generated in the heat generating area is transferred to the circuit.
The heat of the IC chip can be effectively conducted to the substrate.
Improves design margin and improves semiconductor device operation reliability
There is an advantage that

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION A mounting structure of a semiconductor device according to an embodiment of the present invention and a manufacturing method thereof will be described below with reference to the drawings.

First Embodiment FIG. 1 is a semiconductor device mounting structure diagram showing a semiconductor device mounting structure according to a first embodiment of the present invention. The configuration is shown below. As shown in FIG. 1, wiring patterns 3 are formed on the heat conduction circuit board 1, and one end of each pattern serves as a connection pad. The IC chip 6 is face-down mounted via the anisotropic conductive film 7,
The connection pad of the chip 6 and the connection pad of the wiring pattern 3 are electrically connected. Here, the wiring patterns 3 adjacent to each other are arranged within the area where the IC chip 6 is mounted within an arrangement interval within a distance (hereinafter, a predetermined value) at which the electric field in the vicinity of the surface is substantially uniformed. ,
A dummy pattern 5 is provided outside the wiring pattern 3c located at the array end. The dummy pattern 5
The wiring pattern 3 and the wiring pattern 3 are also arranged so as to be within a predetermined value in the area where the IC chip 6 is mounted, and the plurality of wiring patterns 3 are arranged in the area where the IC chip 6 is mounted. The heat dissipation pattern 4 is provided so as to fill the area surrounded by, and the arrangement interval between the wiring pattern 3 and the heat dissipation pattern 4 is also within a predetermined value. Further, the heat dissipation pattern 4 is provided corresponding to a position substantially including the active element disposition region 11 of the IC chip 6 mounted on the heat conductive circuit board 1.

In FIG. 1, copper foil wiring is generally used for the wiring pattern 3, the heat radiation pattern 4, and the dummy pattern 5, and these wirings are mainly formed simultaneously by electrolytic plating. A method of manufacturing a semiconductor device according to the first embodiment of the present invention formed by electrolytic plating will be described below with reference to the drawings. FIG. 4 is an AA ′ when the copper foil wiring formed on the heat conductive circuit board 1 of the semiconductor device mounting structure of Embodiment 1 of the present invention shown in FIG. 1 is formed by electrolytic plating. It is an electric field distribution diagram in the vicinity of the copper foil wiring in the cross section, and the size of the contour line in the figure shows the strength of the electric field 2 in that region. From FIG. 4, the region where the electric field 2 is particularly strong is the outer edge portion of the dummy pattern 5, and the width of the dummy pattern 5 is set and arranged so that this region is outside the region where the IC chip 6 is mounted. . In addition,
The plating film thickness during electrolytic plating is the electric field 2 on the copper foil pattern surface.
, The copper foil of the outer edge portion of the dummy pattern 5 becomes thicker than the other portions.

FIG. 2 is a sectional view taken along the line AA 'of the semiconductor device according to the first embodiment of the present invention shown in FIG. An anisotropic conductive film 7 is interposed on the heat conduction circuit board 1 on which the wiring pattern 3 is formed, and the IC chip 6 is mounted face down on the anisotropic conductive film 7. At this time, the wiring pattern 3 and the IC
The positions of both connection pads of the chip 6 are aligned, and then the IC chip 6 and the thermal conductive circuit board 1
They are thermocompression bonded to each other at a temperature of about 50 to 180 ° C. The anisotropic conductive film 7 is a binder material made of epoxy resin,
This is a mixture of conductive particles 8 made of metal or a composite material such as resin. The resin in the anisotropic conductive film 7 is eluted by thermocompression bonding and the IC chip 6 and the thermal conductive circuit board 1 come close to each other, but the conductive particles 8 left behind are present between the opposing connection pads. . Therefore, the conductive particles 8 are slightly crushed by the pressure applied during the thermocompression bonding, and electrically connect the opposing connection pads. From FIG. 2, the IC chip 6
In the mounting area, since the thickness of the copper foil on the heat conductive circuit board 1 is substantially uniform, the conductive particles 8 are electrically connected in all wiring patterns. On the other hand, FIG. 5 is an electric field distribution diagram in the vicinity of the copper foil wiring in the BB ′ cross section when the copper foil wiring formed on the thermally conductive circuit board 1 in FIG. 1 is formed by the electrolytic plating method. . According to FIG. 5, since the heat dissipation pattern 4 and the wiring pattern 3 are arranged within a predetermined value in the area where the IC chip 6 is mounted, the electric field 2
There is no extremely strong area.

FIG. 3 is a sectional view taken along the line BB 'in FIG. Since the thickness of the copper foil is substantially uniform in the area where the IC chip 6 is mounted, the conductive particles 8 are electrically connected on all the wiring patterns 3 and the active element formed on the IC chip 6 is formed. Since 10 is mounted so as to be located on the heat dissipation pattern 4, the IC chip 6 can be brought close to the heat conductive circuit board 1 also on the heat dissipation pattern 4 via the conductive particles 8. At this time, an epoxy resin, which is a binder material, exists between the IC chip 6 and the heat dissipation pattern 4, and its thickness corresponds to the particle diameter of the thermocompression-bonded conductive particles 8. Since the diameter of the general conductive particles is about 5 μm, the resin thickness on the thermocompression bonding surface is a fraction of that of the conventional mounting structure, and the heat dissipation from the IC chip 6 to the heat conductive circuit board 1 is reduced. The property is improved.

According to the semiconductor device mounting structure and the manufacturing method thereof of the first embodiment of the present invention described above, the wiring pattern 3, the heat radiation pattern 4, and the dummy pattern 5 are formed.
Heat-conductive circuit board 1 formed simultaneously by electroplating
Further, in these patterns, a region where the plated copper foil is thicker than the other portions is located outside the region where the IC chip 6 is mounted. As a result, in bumpless mounting via the anisotropic conductive film, the thickness of the copper foil becomes substantially uniform in the region where the IC chip 6 is mounted, so that the distance between the copper foil and the IC chip 6 is made uniform. Therefore, the electric connection between the IC chip 6 and the wiring pattern can be surely made. Furthermore, the heat dissipation pattern 4 is
It is possible to efficiently dissipate heat to the side of the heat conductive circuit board, improving the thermal design margin of the IC chip, and
The operational reliability of the semiconductor device can be improved.

Second Embodiment Next, a semiconductor device mounting structure and a manufacturing method thereof according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a mounting structure diagram of a semiconductor device according to a second embodiment of the present invention. As shown in FIG. 6, the semiconductor device mounting structure and the manufacturing method thereof according to the present embodiment are partially different from the semiconductor device mounting structure and the manufacturing method according to the first embodiment in that the heat dissipation pattern 4 is It is connected to the GND pattern 9. The GND pattern 9 is provided so as to be connected corresponding to a terminal that becomes a GND electrode among the connection terminals of the IC chip 6. The GND pattern 9 and the wiring pattern 3 and the dummy pattern 5 adjacent to the GND pattern 9 are arranged within a predetermined distance.

Thus, according to the mounting structure of the semiconductor device of the second embodiment and the manufacturing method thereof, each pattern is formed by the electrolytic plating method similarly to the mounting structure of the semiconductor device of the first embodiment and the manufacturing method thereof. The copper foil can be formed to have a uniform thickness, and the region where the plated copper foil is thicker than the other portions is provided outside each region where the IC chip 6 is mounted in each pattern. Therefore, in bumpless mounting via the anisotropic conductive film 7, since the thickness of the copper foil becomes substantially uniform in the region where the IC chip 6 is mounted, the distance between the copper foil and the IC chip 6 is reduced. Therefore, the IC chip 6 and the wiring pattern 3 can be reliably electrically connected. In addition, the heat dissipation pattern 4 is
Since the IC chip 6 mounted on the heat conductive circuit board 1 is arranged corresponding to the position substantially including the active element arrangement region 11, the heat dissipation between the IC chip 6 and the heat conductive circuit board 1 is improved. Is improved and the heat generated in the IC chip 6 can be efficiently radiated, so that the thermal design margin of the IC chip can be improved and the operation reliability of the semiconductor device can be improved, and further, the second aspect of the present invention. According to the semiconductor device mounting structure and the method of manufacturing the same of the embodiment, there is an advantage that an electrostatic shield effect can be provided by connecting the heat dissipation pattern 4 to the GND pattern 9. This is to reduce the switching noise, especially when an IC chip that operates at high voltage amplitude or operates at high speed is mounted, and it is possible to improve the noise margin of the semiconductor device and prevent malfunction of the device. .
Although the heat dissipation pattern 4 is connected to the GND pattern 9 here, the same effect can be obtained by connecting the heat dissipation pattern 4 to another pattern having a predetermined potential.

Third Embodiment Next, a third embodiment different from the semiconductor device mounting method and the semiconductor device manufacturing method according to the first and second embodiments will be described with reference to FIG. 7 is a mounting structure diagram of a semiconductor device according to a third embodiment of the present invention. As shown in FIG. 7, the semiconductor device mounting method and the manufacturing method thereof according to the third embodiment of the present invention are the semiconductor device mounting method of the first and second embodiments of the present invention, and the manufacturing method thereof. The structure is partly different from that of the method, and a part of the heat dissipation pattern 4 arranged corresponding to a position substantially including the active element arrangement area 11 of the IC chip 6 is located in the area where the IC chip 6 is mounted. It has been pulled out. A radiator (not shown) such as a metal plate is attached to a part of the extracted heat radiation pattern 4. It is also possible to connect the extracted heat dissipation pattern 4 to a GND pattern (not shown). Although the heat dissipation pattern 4 is connected to the GND pattern here, the same effect can be obtained by connecting the heat dissipation pattern 4 to another pattern having a predetermined potential.

Further, in the second and third embodiments described above, the IC in which the connection pads are arranged in the two side directions.
Since it is particularly preferable in the case of a chip, it has been described as an example, but it is also effective to use an IC chip in which the connection pads are arranged in the four side directions or the three side directions. Further, in the above-described first to third embodiments, the dummy pattern is arranged adjacent to the array end of the wiring pattern, but in addition to this, the width of the wiring pattern at the array end is widened to arrange the array. The edge portion of the pattern located outside of the IC chip is located outside the area where the IC chip is mounted, or the wiring pattern at the array end is branched, and the wiring pattern of the branched wiring pattern is formed in the area where the IC chip is mounted. Even if the arrangement interval is the same as the arrangement interval of the normal wiring pattern, the same effect can be obtained. Further, in each of the above-mentioned embodiments, the heat conductive circuit board is used. However, when the effect of improving the electrical connectivity of the IC chip and the electrostatic shield function is limited, the heat conductive circuit board is not necessarily used. Need not be used, and can be realized using a normal printed circuit board.

[Brief description of drawings]

FIG. 1 is a mounting structure diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA ′ of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional view taken along the line BB ′ of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is an electric field distribution diagram in the AA ′ cross section of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is an electric field distribution diagram in the BB ′ cross section of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a mounting structure diagram of a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a mounting structure diagram of a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a conventional IC mounting structure diagram.

FIG. 9 is a sectional view taken along the line E-E ′ in the conventional IC mounting structure.

FIG. 10 is an electric field distribution diagram in the EE ′ cross section of the conventional circuit board.

FIG. 11 is a terminal structure diagram of a conventional flexible wiring board.

FIG. 12 is a sectional view taken along the line G-G ′ of the conventional circuit board.

[Explanation of symbols]

1. Thermal conductive circuit board 2. electric field 3. Wiring pattern 3b. Wiring pattern 3c. Wiring pattern 4. Heat dissipation pattern 5. Dummy pattern 6. IC chip 7. Anisotropic conductive film 8. Conductive particles 9. GND pattern 10. Active element 11. Active element placement area 101. Circuit board 103a. Wiring pattern 103b. Wiring pattern 103c. Wiring pattern 106. IC chip 107. Anisotropic conductive film 108. Conductive particles 201. Base film 202. Inner lead connection 203. Inner lead 204. Dummy pattern 206. IC chip 207. Anisotropic conductive film 208. Conductive particles 209. Active element 210. Tip edge

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Claims (2)

(57) [Claims] 1. A mounting structure of a semiconductor device in which an IC chip is face down mounted by bumpless on a circuit board on which a wiring pattern and a dummy pattern are formed via an anisotropic conductive film, wherein the dummy pattern comprises: At least a part of the IC chip
On the mounting area, and the wiring pattern of the mounting area is adjacent to the wiring pattern.
Uniform thickness of wiring pattern or dummy pattern
The dummy pattern which is made to be superposed on the mounting area is mounted.
Active element region or heat generation region formed on the IC chip
A mounting structure of a semiconductor device, which is arranged so as to face the area . 2. A substrate in which an insulating film is formed on a conductive substrate,
It is preferably placed on a thermally conductive insulating substrate by an electrolytic plating process.
A line pattern is formed and anisotropic conductivity is applied on the wiring pattern.
Face down the IC chip with bumpless through the film
A method of manufacturing a semiconductor device to be mounted,The wiring is provided in a region including a region where the IC chip is mounted.
A pattern and a dummy pattern are formed at the same time ,The wiring pattern and the dummy pattern are
Within the area where the IC chip is mounted during the plating process
And the thickness of the wiring pattern and the dummy pattern is
Arranged so as to be uniform, Further, the dummy pattern mounts the IC chip.
The active element region formed on the IC chip or
Arranged to face the heat generation area Characterized by
Manufacturing method of semiconductor device.