JP2008300390A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve heat radiation characteristics of a semiconductor device having a semiconductor chip having large heating value. <P>SOLUTION: The semiconductor device has a wiring board 7 having a main surface 7a and a reverse surface 7b, a dummy chip 1 which is mounted on the wiring board 7 and made of silicon, a VR chip 2 which is made of silicon and mounted on the dummy chip 1 and has a semiconductor element and a surface electrode formed, a logic chip 3 mounted on the wiring board 7, and a plurality of solder balls 9 provided on the reverse surface 7b of the wiring board 7, where the VR chip 2 is a power supply system chip having large heating value and therefore joined with the dummy chip 1 made of silicon as well to increase the volume and increase the heat capacity, thereby reducing the heat resistance and increasing heat radiation effect. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to an improvement in heat dissipation of a semiconductor device having a power source semiconductor chip that generates a large amount of heat.

  In an electronic component mounting substrate, there is a technique for reducing the size of an insulating substrate by releasing heat from a power element by a metal plate and reducing heat conduction from the metal plate by a poor heat conduction layer (see, for example, Patent Document 1). ).

Further, a QFP structure in which a semiconductor chip is mounted on a metal plate (support) is disclosed (for example, see Patent Document 2).
JP-A-8-279664 (FIG. 1) JP 2004-158875 A

  For example, an electronic circuit that controls liquid crystal of an electronic device includes a logic chip (control chip) that performs signal processing, and a semiconductor chip (Voltage for voltage conversion) that controls a power supply voltage for driving the logic chip. Regulator-chips (hereinafter also referred to as VR chips) are assembled as separate semiconductor devices (semiconductor packages) and mounted on a mounting substrate.

  However, if the semiconductor device is manufactured by another semiconductor device, the mounting area of the mounting substrate becomes large, so that it cannot cope with the downsizing of the product.

  As a method for realizing miniaturization of a product, it is conceivable to manufacture a semiconductor chip having a function of a VR chip and a function of a logic chip.

  However, when different functions are integrated into one chip, each element is manufactured by a different process. Further, in the case of one chip, the degree of freedom of combination of semiconductor chips is reduced. Furthermore, the yield of the semiconductor device (package) is reduced. That is, in the case of one chip, if the manufacturing process of any one of the elements becomes defective, the whole package becomes defective, which causes a problem that the yield of the semiconductor device decreases.

  Therefore, in recent years, in order to reduce the size of products, for example, as shown in Patent Document 1, a SIP (System In Package) in which a VR chip and a logic chip are mounted on one wiring board has been proposed. Yes.

  However, since the VR chip converts a high power supply voltage supplied from the outside for the operation of the logic chip, the amount of heat generated from the VR chip is large. For this reason, it has been found that the following problems occur when a VR chip and a logic chip having such a large amount of heat generation are configured by one semiconductor device.

  A logic chip that inputs / outputs signals to / from an external device cannot perform signal processing stably and is not likely to operate when exposed to high temperatures. Therefore, in order to configure a VR chip having a large amount of heat generation and a logic chip for performing signal processing with one semiconductor device, it is necessary to improve the heat dissipation of the VR chip.

  As a semiconductor device capable of improving heat dissipation, for example, a QFP (Quad Flat Package) structure in which a semiconductor chip is mounted on a metal plate as shown in Patent Document 2 (Japanese Patent Laid-Open No. 2004-158875) can be considered. However, a logic chip that performs signal processing with an external device also has a relatively large number of external terminals (for example, 220 pins). Therefore, when the QFP structure is used, the outer size of the package is larger than the structure mounted on the wiring board. Problem arises.

  Therefore, a technique for improving heat dissipation by mounting a VR chip on a metal plate as disclosed in the above-mentioned Patent Document 1 (Japanese Patent Laid-Open No. 8-279664) can be considered.

  However, since the adhesion between the metal plate (aluminum plate or copper plate) and the mold resin is relatively low, there is a problem that a peeling failure occurs between the mold resin for sealing the semiconductor chip and the metal plate in a later process. is there.

  Furthermore, since the thermal expansion coefficient of the VR chip made of a silicon chip is different from that of the metal plate, for example, due to the influence of reflow heat when the manufactured semiconductor device is mounted on the mounting substrate, the VR chip and the metal plate are not affected. The problem is that peeling failure occurs. If the VR chip is peeled off from the metal plate for heat dissipation, it is difficult to efficiently dissipate the heat generated from the VR chip.

  An object of the present invention is to provide a technique capable of improving heat dissipation in a semiconductor device having a semiconductor chip having a large calorific value.

  Another object of the present invention is to provide a technique capable of reducing the package size in a semiconductor device having a semiconductor chip that generates a large amount of heat.

  Another object of the present invention is to provide a technique capable of improving the yield in a semiconductor device having a semiconductor chip that generates a large amount of heat.

  Another object of the present invention is to provide a technique capable of reducing the cost of a semiconductor device having a semiconductor chip that generates a large amount of heat.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the present invention is a wiring substrate having a main surface and a back surface opposite to the main surface, mounted on the main surface of the wiring substrate, made of silicon, and mounted on the chip structure, It has a semiconductor chip on which a semiconductor element and a surface electrode are formed, and a plurality of external terminals provided on the back surface of the wiring board.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  By mounting a semiconductor chip with a large amount of heat generation on a chip structure made of silicon on a wiring board, the thermal resistance of the semiconductor chip can be lowered, and as a result, a semiconductor device having a semiconductor chip with a large amount of heat generation The heat dissipation can be improved.

  A semiconductor chip having a large amount of heat generation is a VR chip. By mounting the VR chip and a logic chip on a wiring board, the package size can be reduced as compared with a lead frame type package.

  In addition, a semiconductor chip having a large amount of heat generation is a VR chip. By mounting this VR chip and a logic chip on a wiring board to form one package, the yield of the semiconductor device can be improved as compared with the one chip. Can do.

  Further, the cost of the semiconductor device can be reduced as compared with a single chip.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment)
FIG. 1 is a plan view showing an example of a structure of a semiconductor device according to an embodiment of the present invention through a sealing body, and FIG. 2 is a cross-sectional view showing an example of a structure cut along line AA in FIG. 3 is a sectional view showing an example of the structure cut along the line BB in FIG. 1, FIG. 4 is a sectional view showing an example of the structure cut along the line CC in FIG. 1, and FIG. FIG. 2 is a circuit block diagram illustrating an example of a circuit configuration of the semiconductor device illustrated in FIG. 1. 6 is a plan view showing an example of a wiring pattern on the main surface of the wiring board mounted on the semiconductor device of FIG. 1. FIG. 7 is an opening of an insulating film (solder resist) on the main surface of the wiring board shown in FIG. FIG. 8 is an enlarged partial sectional view showing an example of the structure of the lower part of the chip in the semiconductor device shown in FIG. Further, FIG. 9 is a manufacturing process flow chart showing an example of a die bonding process in the assembly of the semiconductor device shown in FIG. 1, and FIG. 10 shows an example of a wire bonding process to an individualization process in the assembly of the semiconductor device shown in FIG. It is a manufacturing process flowchart. 11 is a plan view showing the structure of a semiconductor device according to a modification of the embodiment of the present invention through a sealing body, and FIG. 12 is an example of the structure cut along the line AA in FIG. It is sectional drawing shown.

  The semiconductor device of the present embodiment shown in FIGS. 1 to 4 includes a plurality of semiconductor chips including a power supply system chip that generates a large amount of heat, and the plurality of semiconductor chips are mounted on one wiring board. , So-called one package. In the present embodiment, as an example of such a semiconductor device, a semiconductor chip (first semiconductor chip, logic chip, control chip) that performs signal processing, a power supply voltage for driving the semiconductor chip, and the like are controlled. A description will be given by taking up a SIP (System In Package) 8 in which a semiconductor chip for power supply voltage conversion (second semiconductor chip, VR chip) is mounted on one wiring board. In FIG. 1, only the representative wires 5 are shown for the wires 5 that electrically connect the VR chip 2 or the logic chip 3 and the wiring board 7. The display of the wire 5 is omitted.

  The configuration of the SIP 8 will be described. A wiring board 7 having a main surface 7a and a back surface 7b, and a dummy chip (chip structure) mounted on the wiring board 7 and made of silicon and having no semiconductor element and no surface electrode formed thereon. 1 and a VR (Voltage Regulator) chip 2 which is a semiconductor chip mounted on the dummy chip 1 and made of silicon, which is the same material as the dummy chip, and on which a semiconductor element and a surface electrode are formed, and a wiring board 7 It has a plurality of external terminals provided on the back surface 7b.

  As shown in FIG. 2, the main surface 7a and the back surface 7b of the wiring board 7 are opposed to each other, the dummy chip 1 is mounted on the main surface 7a via a paste adhesive 4, and the VR chip 2 is a dummy chip. 1 is also mounted via a paste adhesive 4. That is, the VR chip 2 is laminated on the dummy chip 1 via the paste adhesive 4. Here, the paste adhesive 4 uses, for example, a conductive adhesive containing Ag particles in order to efficiently propagate the heat generated from the VR chip 2 to the dummy chip 1.

  The VR chip 2 is a power source chip made of silicon, which is the same material as the dummy chip 1, and has a large calorific value. Therefore, the VR chip 2 is bonded to the dummy chip 1 also made of silicon in a stacked state to increase the volume. The heat capacity is increased, thereby reducing the thermal resistance and enhancing the heat dissipation effect.

  Further, the VR chip 2 has a semiconductor element and a pad 2c which is a surface electrode formed on the main surface 2a side, and is electrically connected to the wiring substrate 7 by wire connection. The back surface 2 b is bonded to the dummy chip 1 via the paste adhesive 4.

  The VR chip 2 is a chip having a function of transforming the magnitude of the power supply voltage supplied from outside the SIP 8.

  The dummy chip 1 which is a chip structure made of silicon is a so-called silicon chip, but is not formed with a semiconductor element, a surface electrode for wire bonding, or the like. That is, there is no exchange of electrical signals with the outside of the chip, and it is arranged below the VR chip 2 in order to enhance the heat dissipation effect of the VR chip 2 mounted thereon.

  At that time, as shown in FIGS. 1 and 2, the dummy chip 1 has a main surface 2 a in the direction intersecting the thickness direction of the VR chip 2 in the size of the main surface 1 a intersecting the thickness direction. Bigger than the size of. That is, since the dummy chip 1 is for increasing the heat capacity of the VR chip 2 on the dummy chip 1, it is preferable that the volume is as large as possible. However, if the thickness is increased, the package height of the SIP 8 is also increased. Therefore, it is preferable to make the main surface 1a as large as possible so as to increase the volume even if the thickness is small.

  Note that the SIP 8 of the present embodiment further includes a logic chip 3 driven by a power supply voltage transformed by the VR chip 2 on the main surface 7a of the wiring board 7. Specifically, as shown in FIGS. 1 and 4, the VR chip 2 and the logic chip 3 are arranged substantially side by side on the wiring board 7. The logic chip 3 exchanges (inputs / outputs) signal data with the outside of the SIP 8. Like the dummy chip 1 and the VR chip 2, the logic chip 3 is connected to the main surface of the wiring substrate 7 via the paste adhesive 4. 7a. Here, the paste adhesive 4 uses, for example, a conductive adhesive containing Ag particles in order to efficiently propagate the heat generated from the VR chip 2 to the dummy chip 1.

  Further, since the logic chip 3 has a large number of pins, it has an elongated shape as shown in FIGS. 1 and 3, and a paste-like adhesive 4 is interposed at a substantially central portion of the main surface 7 a of the wiring substrate 7. It is installed.

  Furthermore, the logic chip 3 has a pad 3c which is a semiconductor element and a surface electrode formed on the main surface 3a side, and is electrically connected to the wiring board 7 by wire connection in the same manner as the VR chip 2, As shown in FIGS. 3 and 4, the main surface 3 a is disposed facing upward, and the back surface 3 b is bonded to the main surface 7 a of the wiring substrate 7 via the paste adhesive 4.

  In the VR chip 2 and the logic chip 3, the pads 2c and 3c are electrically connected to the bonding electrodes 7c shown in FIGS. 1 and 8 on the main surface 7a of the wiring board 7 by wires 5 such as gold wires. ing.

  As shown in FIGS. 2 to 4, the dummy chip 1, the VR chip 2, the logic chip 3, and the plurality of wires 5 are made of resin by a sealing body 6 formed of a sealing resin on the wiring substrate 7. It is sealed.

  Further, as shown in FIG. 8, a plurality of lands 7g are exposed on the back surface 7b of the wiring board 7, and solder balls 9 as external terminals are joined to the lands 7g.

  Next, an outline of the circuit operation of the SIP 8 of the present embodiment will be described.

  As shown in FIG. 5, the power supply voltage supplied from the outside first enters the VR chip 2. Thereafter, for example, a power supply voltage of 3.0 to 3.6 V that has entered the VR chip 2 is converted to 1.8 V by the VR chip 2, and the power supply voltage of 1.8 V enters the logic chip 3. In the logic chip 3, signal system data is exchanged with the outside by the 1.8 V power supply voltage converted and supplied by the VR chip 2.

  As described above, in the SIP 8, the VR chip 2 converts (reduces) the power supply voltage supplied from the outside to a voltage value corresponding to the logic chip 3, supplies the voltage to the logic chip 3, and operates the logic chip 3. . Therefore, the VR chip 2 is supplied with a power supply voltage of about 3.6 V, for example, and therefore generates a large amount of heat. Therefore, it is necessary to devise how to dissipate heat from the VR chip 2 that generates a large amount of heat.

  In the SIP 8 of the present embodiment, as described above, the VR chip 2 is mounted on the dummy chip 1 made of silicon via the paste adhesive 4 as the heat dissipation means of the VR chip 2. Measures are being taken.

  That is, the VR chip 2 can be bonded to the dummy chip 1 made of silicon in the stacked state to increase the volume and increase the heat capacity, and as a result, the heat resistance can be reduced and the heat dissipation effect can be increased.

  Next, as shown in FIG. 6, on the main surface 7a of the wiring board 7, a solid pattern (wide pattern) made of a conductor is formed in the central chip mounting area (the chip mounting area of the dummy chip 1 and the logic chip 3). As shown in FIG. 1, the dummy chip 1 and the logic chip 3 are mounted on the heat dissipation pattern 7f.

  Therefore, the heat generated from the VR chip 2 is first transmitted to the dummy chip 1 and further transmitted to the heat radiation pattern 7f via the dummy chip 1 to be dissipated, thereby further enhancing the heat radiation effect of the VR chip 2. it can. The heat radiation pattern 7f is preferably made of, for example, a copper pattern similar to the lead wiring 7i and the like.

  Here, the structure of the wiring board 7 incorporated in the SIP 8 of the present embodiment will be described. As shown in FIG. 8, the wiring board 7 is a two-layer board having a core material 7j and wiring layers 7k formed on both front and back surfaces of the core material 7j. That is, on the surface side of the core material 7j, a wiring layer 7k including a heat radiation pattern 7f, which is a solid pattern, a plurality of bonding electrodes 7c, lead wires 7i, and the like is formed. The plurality of bonding electrodes 7c are arranged side by side on both sides in the width direction of the elongated heat radiation pattern 7f as shown in FIGS.

  On the other hand, as shown in FIG. 8, a wiring layer 7k including a plurality of lands 7g, lead wirings 7i and the like is formed on the back surface side of the core material 7j. The core material 7j is made of, for example, glass epoxy resin.

  Further, the wiring on the front surface side and the wiring on the back surface side are electrically connected through the corresponding through-hole wiring 7h. That is, as shown in FIGS. 6 and 8, each bonding electrode 7c is electrically connected to the land 7g on the back surface side through the lead wiring 7i and the through-hole wiring 7h.

  Therefore, the pads 2c of the VR chip 2 and the pads 3c of the logic chip 3 are electrically connected to the corresponding solder balls 9 through the wires 5, the bonding electrodes 7c, the lead wirings 7i, the through-hole wirings 7h, and the lands 7g. Has been.

  In addition, an insulating film 7 d is formed on the uppermost layers of the front and back surfaces of the wiring substrate 7. The insulating film 7d is, for example, a solder resist film. As shown in FIGS. 7 and 8, a plurality of openings 7e are formed in the insulating film 7d on both the front and back surfaces, and the bonding electrodes 7c are exposed on the main surface 7a side, while the back surface 7b. On the side, the land 7g is exposed.

  In SIP 8, since the insulating film 7d is formed on the uppermost layer of the surface (main surface 7a) of the wiring substrate 7, the dummy chip 1 is pasted on the insulating film 7d as shown in FIG. 4 is mounted. In other words, the insulating film 7d is disposed between the heat radiation pattern 7f and the dummy chip 1.

  7 and 8, a plurality of bonding electrodes 7c are formed around the dummy chip 1 on which the VR chip 2 is placed on the main surface 7a of the wiring board 7, and the dummy chip 1 and the VR chip are further formed. A concave dam portion 7m formed by opening an insulating film 7d in a region between 2 and the plurality of bonding electrodes 7c is provided in a U-shape. This dam part 7m prevents the outflow of the paste adhesive 4 which is a die bond agent to the outside.

  That is, when the dummy chip 1 is mounted, the paste-like adhesive 4 that has flowed out from the side of the dummy chip 1 is dropped into the dam portion 7m formed by opening the insulating film 7d, and the paste-like adhesive is obtained. 4 can be prevented from flowing out to the bonding electrode 7 c, and the bonding electrode 7 c can be prevented from being soiled by the paste adhesive 4.

  The dam portion 7m is also formed in a U-shape in a region between the logic chip 3 and the surrounding bonding electrode 7c. As a result, when the logic chip 3 is mounted, the paste-like adhesive 4 that has flowed out of the side of the logic chip 3 is dropped into the dam portion 7m as in the case of the dummy chip 1, and the paste-like adhesive is removed. 4 can be prevented from flowing out to the bonding electrode 7 c, and the bonding electrode 7 c can be prevented from being soiled by the paste adhesive 4.

  The SIP 8 of the present embodiment has the VR chip 2 that generates a large amount of heat. Therefore, the heat dissipation of the VR chip 2 must be improved. Therefore, since the heat radiation pattern 7f, which is a solid pattern, is formed below the dummy chip 1 on which the VR chip 2 is mounted, the dummy chip 1 is originally directly mounted on the heat radiation pattern 7f without the insulating film 7d. Needless to say, it is more effective for heat dissipation.

  However, when the dummy chip 1 is mounted on the wiring board 7 using a conductive adhesive without using the insulating film 7d, different through holes are electrically connected to each other through the paste adhesive 4. Therefore, the dummy chip 1 is mounted on the insulating film 7d even if the heat dissipation effect is somewhat reduced.

  The dummy chip 1 has a major surface 1a larger than the VR chip 2 in consideration of heat dissipation. Therefore, as shown in FIG. 7, the distance between the end portion of the dummy chip 1 and the bonding electrode 7c on the main surface 7a of the wiring board 7 is shortened. Since the dummy chip 1 is mounted via the paste-like adhesive 4, the paste-like adhesive 4 is likely to flow out and a bleed failure is likely to occur. Therefore, the dam portion 7m for preventing the paste-like adhesive 4 from flowing out. Is required.

  Next, a method for manufacturing the SIP 8 of the present embodiment will be described with reference to the manufacturing process flow charts of FIGS.

  First, die bonding shown in step S1 of FIG. 9 is performed. Here, the logic chip 3 is mounted on the main surface 7 a of the wiring board 7 via the paste adhesive 4.

  At that time, the paste-like adhesive 4 that has flowed out from the side of the logic chip 3 is dropped into the dam portion 7m formed by opening the insulating film 7d, and as a result, the bonding electrode 7c of the paste-like adhesive 4 is formed. Can be prevented from flowing out.

  Thereafter, dummy chip bonding shown in step S2 is performed. Here, the dummy chip 1 is mounted next to the logic chip 3 on the main surface 7 a of the wiring substrate 7 via the paste adhesive 4.

  At this time, the paste-like adhesive 4 that has flowed out of the side of the dummy chip 1 is dropped into the dam portion 7m of the insulating film 7d, thereby preventing the paste-like adhesive 4 from flowing out to the bonding electrode 7c. Can do.

  Thereafter, VR chip bonding shown in step S3 is performed. Here, the VR chip 2 is mounted on the main surface 1 a of the dummy chip 1 on the main surface 7 a of the wiring substrate 7 via the paste adhesive 4. That is, the VR chip 2 is laminated on the dummy chip 1 via the paste adhesive 4.

  Thereafter, wire bonding shown in step S4 of FIG. 10 is performed. Here, the pads 3c of the logic chip 3 and the bonding electrodes 7c (see FIG. 7) of the wiring board 7 are electrically connected by wires 5, and the pads 2c of the VR chip 2 and the bonding electrodes 7c of the wiring board 7 are connected by wires. 5 for electrical connection.

  Note that either the wire bonding of the logic chip 3 or the wire bonding of the VR chip 2 may be performed first.

  Thereafter, resin molding shown in step S5 is performed. Here, resin molding is performed by transfer molding or the like using a sealing resin, and a sealing body 6 is formed on the main surface 7a of the wiring substrate 7 to form the logic chip 3, the dummy chip 1, the VR chip 2, and a plurality of wires. 5 is resin-sealed.

  Thereafter, ball mounting shown in step S6 is performed. Here, a plurality of solder balls 9 are joined to the back surface 7b of the wiring board 7 as external terminals.

  Thereafter, individualization shown in step S7 is performed. Here, the sealing body 6 and the wiring board 7 are cut together and separated into individual pieces to complete the assembly of the SIP 8.

  According to the semiconductor device of the present embodiment, on the wiring substrate 7 incorporated in the SIP 8 having the VR chip 2 having a large calorific value, the calorific value is large on the dummy chip 1 made of silicon and is also made of silicon. By mounting the chip 2, the volume of the VR chip 2 is increased by the amount of the dummy chip 1, so that the thermal resistance of the VR chip 2 can be lowered.

  Thereby, the heat dissipation of the SIP 8 (semiconductor device) having the VR chip 2 that generates a large amount of heat can be improved.

  Further, when the VR chip 2 having a large calorific value is mounted and the logic chip 3 is mounted together with the VR chip 2, the VR chip 2 and the logic chip 3 are mounted on the wiring substrate 7 to thereby realize a lead frame type package. Instead, since the SIP8 (semiconductor device) can be realized as a substrate type, the package size of the SIP8 can be reduced.

  Further, when the VR chip 2 having a large heat generation amount is mounted and the logic chip 3 is mounted together with the VR chip 2, the VR chip 2 and the logic chip 3 are made into one package structure, which is compared with the one-chip structure. Thus, the yield of SIP 8 (semiconductor device) can be improved.

  Furthermore, when the VR chip 2 having a large amount of heat generation is mounted and the logic chip 3 is mounted together with the VR chip 2, the VR chip 2 and the logic chip 3 are made into one package structure in comparison with the one chip. Thus, the cost of the SIP 8 (semiconductor device) can be reduced.

  Further, when the VR chip 2 having a large amount of heat generation is provided and the logic chip 3 is mounted together with the VR chip 2, the VR chip 2 and the logic chip 3 are not integrated into one chip by forming a single package structure. The degree of freedom of combination of semiconductor chips can be increased.

  In place of the dummy chip 1 made of silicon or the like, a metal plate such as a copper plate (Cu plate) may be adopted. However, in the case of the metal plate (Cu plate), a sealing resin (mold resin) and Due to the poor adhesion of the silicon chip, a peeling failure occurs.

  Further, in the case of the metal plate (Cu plate), since the thermal expansion coefficient (α) is different from that of the VR chip 2 (silicon chip), the peeling from the sealing resin is likely to occur as described above.

  Therefore, since the dummy chip 1 is made of the same material as the VR chip 2 by using the dummy chip 1 as a silicon chip as in the SIP 8 of the present embodiment, it is not necessary to worry about manufacturing conditions. Furthermore, the adhesiveness with the sealing resin (mold resin) of the dummy chip 1 is securable.

  That is, since the VR chip 2 having a large calorific value is mounted on the dummy chip 1 made of silicon, the adhesion between the dummy chip 1 and the mold resin is better than the adhesion between the metal plate such as a copper plate and the mold resin. The dummy chip 1 and the mold resin can be prevented from peeling off.

  Further, since the dummy chip 1 is made of silicon, the dummy chip 1 and the VR chip 2 having a large heat generation amount have the same thermal expansion coefficient (α). As a result, it is possible to prevent the dummy chip 1 and VR chip 2 from being separated from the mold resin.

  Next, a semiconductor device according to a modification of the present embodiment shown in FIGS. 11 and 12 will be described.

  The semiconductor device of the modification shown in FIG. 11 is the same SIP 10 as the semiconductor device (SIP 8) shown in FIG. 1, and is a package in which a plurality of semiconductor chips including a power supply system chip with a large amount of heat generation are packaged.

  The difference between the SIP 10 and the SIP 8 is that the heat radiation pattern 7f, which is a solid pattern, is not provided in the chip mounting region of the main surface 7a of the wiring board 7. Instead of the heat radiation pattern 7f, a plurality of small dummy patterns 7n are provided. Is provided.

  That is, a plurality of dummy patterns 7n that are much smaller than the heat radiation pattern 7f are provided in the chip mounting area of the main surface 7a of the wiring board 7 of the SIP 10, and the heat generated from the VR chip 2 is generated by the dummy chip 1. The heat is transferred to the dummy pattern 7n through the heat sink to dissipate heat.

  In the SIP 10, similarly to the SIP 8, as shown in FIG. 12, the dummy chip 1 and the logic chip 3 are mounted on the wiring substrate 7 via the paste adhesive 4, and the heat generation amount is large on the dummy chip 1. The VR chip 2 is mounted via a paste adhesive 4.

  In the SIP 10 as well, the VR chip 2 and the logic chip 3 are electrically connected to the wiring board 7 by wire connection, respectively.

  Since the other structure of the SIP 10 of the modified example is the same as that of the SIP 8, redundant description thereof is omitted.

  According to the SIP 10 of the modified example, the VR chip 2 has a large volume of heat on the dummy chip 1 made of silicon and mounted on the dummy chip 1 made of silicon. Therefore, the thermal resistance of the VR chip 2 can be lowered.

  Thereby, even in the SIP 10 (semiconductor device) having the VR chip 2 that generates a large amount of heat, the heat dissipation can be improved.

  Further, when the VR chip 2 having a large calorific value is mounted and the logic chip 3 is mounted together with the VR chip 2, the VR chip 2 and the logic chip 3 are mounted on the wiring substrate 7 to thereby realize a lead frame type package. Instead, since the SIP 10 can be realized by a substrate type, the package size of the SIP 10 can be reduced.

  Further, when the VR chip 2 having a large heat generation amount is mounted and the logic chip 3 is mounted together with the VR chip 2, the VR chip 2 and the logic chip 3 are made into one package structure, which is compared with the one-chip structure. Thus, the yield of the SIP 10 can be improved.

  Furthermore, when the VR chip 2 having a large amount of heat generation is mounted and the logic chip 3 is mounted together with the VR chip 2, the VR chip 2 and the logic chip 3 are made into one package structure in comparison with the one chip. Thus, the cost of the SIP 10 can be reduced.

  Note that the other effects obtained by the SIP 10 shown in FIG. 11 are the same as the effects obtained by the SIP 8, and therefore, the duplicate description thereof is omitted.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the embodiment, SIPs 8 and 10 in which the dummy chip 1 and the logic chip 3 are mounted on the wiring substrate 7 and the VR chip 2 is mounted on the dummy chip 1 are taken as an example of the semiconductor device. As described above, the semiconductor device is not necessarily SIP if the dummy chip 1 made of silicon is mounted on at least the wiring substrate 7 and the semiconductor chip having a large calorific value is mounted on the dummy chip 1. There may be no semiconductor device having a structure other than SIP.

  Also, the semiconductor chip mounted on the dummy chip 1 is not limited to the VR chip 2 and may be another semiconductor chip as long as it generates a large amount of heat, for example, a power source semiconductor chip. Good.

  Further, the number of semiconductor chips other than the dummy chip 1 mounted on the wiring board 7 is not particularly limited, and may be one or plural.

  Further, the dummy chip 1 has been described with respect to the fact that the semiconductor element and the surface electrode are not formed. However, the present invention is not limited to this, and the semiconductor element and the surface electrode may be formed like the VR chip 2. . However, the surface structure of the semiconductor chip on which the semiconductor elements and the surface electrodes are formed is not shown, but it has a multilayer wiring structure in which a plurality of wiring layers and a plurality of insulating layers are alternately stacked. The element and the surface electrode are preferably not formed.

  In this embodiment, the dummy chip 1, the VR chip 2 and the logic chip 3 are mounted using the conductive paste adhesive 4. However, the present invention is not limited to this. For example, a film DAF (Die Attach Film), which is an adhesive, may be used. In the case of DAF, since a part of the adhesive does not flow out to the periphery like a paste-like adhesive, the dam portion 7m can be eliminated and a larger dummy chip 1 can be used. . However, since the structure of the DAF is composed of a structure having adhesive layers on the front and back of the tape base material, it is better to use the conductive paste adhesive 4 described in the present embodiment when considering heat dissipation. preferable.

  The present invention is suitable for an electronic device having a semiconductor chip that generates a large amount of heat.

It is a top view which permeate | transmits and shows an example of the structure of the semiconductor device of embodiment of this invention through a sealing body. It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. It is sectional drawing which shows an example of the structure cut | disconnected along CC line of FIG. FIG. 2 is a circuit block diagram illustrating an example of a circuit configuration of the semiconductor device illustrated in FIG. 1. FIG. 2 is a plan view showing an example of a wiring pattern on a main surface of a wiring board mounted on the semiconductor device of FIG. 1. It is a top view which shows an example of the opening part of the insulating film (solder resist) in the main surface of the wiring board shown in FIG. FIG. 2 is an enlarged partial cross-sectional view illustrating an example of a structure under a chip in the semiconductor device illustrated in FIG. 1. It is a manufacturing process flowchart which shows an example of the die bonding process in the assembly of the semiconductor device shown in FIG. It is a manufacturing process flowchart which shows an example of the wire bonding process-the fragmentation process in the assembly of the semiconductor device shown in FIG. It is a top view which permeate | transmits a sealing body and shows the structure of the semiconductor device of the modification of embodiment of this invention. It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG.

Explanation of symbols

1 Dummy chip (chip structure)
1a Main surface 2 VR chip (semiconductor chip)
2a Main surface 2b Back surface 2c Pad (surface electrode)
3 Logic chip 3a Main surface 3b Back surface 3c Pad (surface electrode)
4 paste adhesive 5 wire 6 sealing body 7 wiring board 7a main surface 7b back surface 7c bonding electrode 7d insulating film 7e opening 7f heat radiation pattern 7g land 7h through-hole wiring 7i lead wiring 7j core material 7k wiring layer 7m dam part 7n Dummy pattern 8 SIP (semiconductor device)
9 Solder balls (external terminals)
10 SIP (semiconductor device)

Claims (12)

A wiring board having a main surface and a back surface facing the main surface;
A chip structure mounted on the main surface of the wiring board and made of silicon;
A semiconductor chip mounted on the chip structure and having a semiconductor element and a surface electrode formed thereon;
A semiconductor device comprising: a plurality of external terminals provided on a back surface of the wiring board.   2. The semiconductor device according to claim 1, wherein the semiconductor chip has a function of transforming a magnitude of a power supply voltage supplied from outside the semiconductor device.   3. The semiconductor device according to claim 2, wherein a logic chip to which a power supply voltage transformed by the semiconductor chip is supplied is mounted on a main surface of the wiring board, and the semiconductor chip and the logic are mounted on the wiring board. A semiconductor device, wherein chips are arranged side by side.   2. The semiconductor device according to claim 1, wherein a semiconductor element and a surface electrode are not formed on the chip structure.   2. The semiconductor device according to claim 1, wherein an insulating film is formed on a main surface of the wiring substrate, and the chip structure is mounted on the insulating film.   6. The semiconductor device according to claim 5, wherein a heat radiation pattern made of a conductor is formed on a main surface of the wiring board.   7. The semiconductor device according to claim 6, wherein the insulating film is disposed between the heat dissipation pattern and the chip structure.   6. The semiconductor device according to claim 5, wherein the chip structure and the semiconductor chip are mounted via a paste adhesive.   9. The semiconductor device according to claim 8, wherein a plurality of bonding electrodes are formed around the semiconductor chip on the main surface of the wiring board, and the insulating film is formed in a region between the semiconductor chip and the plurality of bonding electrodes. A semiconductor device, wherein a dam portion formed by opening is provided.   2. The semiconductor device according to claim 1, wherein the wiring board is a two-layer board having a core material, and wiring layers are formed on both front and back surfaces of the core material.   11. The semiconductor device according to claim 10, wherein the core material is made of glass epoxy resin.   2. The semiconductor device according to claim 1, wherein the size of the surface of the chip structure in the direction intersecting the thickness direction is larger than the size of the surface in the direction intersecting the thickness direction of the semiconductor chip. A semiconductor device.

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